SUB-0.7V 5-GHz DIRECT-CONVERSION RECEIVER FRONT-END
2.3 Folded-Cascode Low-Noise Amplifier
2.3.1 Design Considerations
Input matching is an important consideration for connection with external components.
Described in microwave theory, signal is partially reflected as soon as passing through an interface between two different mediums. In other words, in circuits, two stages with unequal input/output impedances stand for two different mediums. Hence, to minimize signal reflection, input impedance of a LNA has to be designed to 50 Ω (the characteristic impedance in wireless communication system).
A feasible method of creating an input resistance of 50 Ω in a common-source amplifier is inductive source degeneration, which is illustrated in Fig. 18. To simplify the analysis, consider a MOS model that includes only a transconductance and a gate-source capacitance.
In the case, it is not hard to show that the input impedance has the following form:
m 1
From Eq. (2.12), it is realized that source inductor can efficiently eliminate the imaginary part;
therefore, proper choice of gm, Ls, and Cgs yields a 50-Ω resistance.
Fig. 18 Input impedance of common-source with inductive source degeneration.
Practically, input matching is also affected by other inevitable factors. In general, there are parasitical capacitances existing on I/O pads, furthermore, if a chip under test is bonded on
a printed circuit board for measurement, bond-wires contribute parasitical inductance. Take these parasitics into account, a revised model with parasitics of a pad and a bond-wire is shown in Fig. 19. It is convenient to use Smith chart to decide proper value of Cpad and Lbw so that the input impedance Zin can achieve 50 Ω.
Fig. 19 Revised model of input impedance.
Another important issue to LNA is noise performance. We are going to analyze the noise performance of the LNA, which is common-source topology with inductive source degeneration, and design an optimum dimension of the MOS transistor to obtain minimum noise contribution.
The noise figure of the LNA can be computed by analyzing the circuit shown in Fig. 20.
In this circuit, Rs and Rg represent the resistance of voltage source and gate resistance, respectively; i represents the channel thermal noise of the device. Besides, if the device is d2 biased so that the channel is inverted, fluctuations in the channel charge will induce a physical current in the gate due to capacitive couple [40]. It is called “induced gate noise” and represented ig2 in Fig. 20.
Fig. 20 Noise model of input stage.
Analysis based on this circuit neglects the noise contribution of subsequent stages to the amplifier; thus, the noise figure formulates as [41]:
(
In this equation, γ is the coefficient of channel thermal noise, L is the channel length, νsat and εsat are the saturation velocity and the velocity saturation field strength, respectively, Vod is the overdrive voltage, and PD is the power consumption. Moreover, P
(
ρ,PD)
denotes a high-order polynomial. The detailed contents are derived in [41]. Besides, consider a simple second-order model of the MOSFET transconductance can be employed which accounts for high-field effects in short-channel devices. Assume that Id has the form [42]2
Having established an expression for Id, we can formulate the power consumption of the
amplifier as follows,
As Eq. (2.13) and (2.16) expressed, they reveal that channel width is an implicit function of noise figure.
Consequently, the decidable parameters are Vdd, PD, W and L. An alternative method of optimization fixes the power consumption and adjusts ρ to find the minimum noise figure;
also, minimum channel length and 0.6-V supply voltage are chosen in 0.18-μm CMOS technology. In conclusion, Fig. 21 indicates the relation between channel width and noise figure with fixed power consumption each curve. It is convenient to decide proper channel width with restricted power consumption so that the optimum noise figure is obtained.
Transconductance of input-stage MOS transistor and load impedance dominate the voltage gain in common-source amplifier. The transconductance is fixed while the dimension of MOS transistors and bias condition has been decided for input matching and noise optimization. Hence, sufficiently high load impedance or other advanced circuit structure with identical input stage is then expected. Besides, in RF circuits, LC-tank is a common choice for load if fabrication technology is able to provide inductors with adequate quality factors because loads with higher quality factor cause higher gain. On the other hand, although high-Q load increases gain effectively, linearity is contrarily degraded. An LNA operating nonlinearly causes intermodulation while signals with various frequencies are received simultaneously; as a result, the frequencies of other undesired signals output from LNA are close to that of received signals. Here is an illustration in Fig. 22 for example. The LNA receives two signals at ω1 and ω2, respectively, and then outputs signals at ω1,ω2, 2ω1-ω2 and 2ω2-ω1. If the difference between ω1 and ω2 is small, the signals at 2ω1-ω2 and 2ω2-ω1 appear in the vicinity of ω1 and ω2. As the power of ω1 and ω2 increases, the power of 2ω1-ω2 and
2ω2-ω1 grows up in cube. Thus, the additional signals may fall in adjacent channels and corrupt normal receiving.
Fig. 21 Minimum NF curves related to channel width and power consumption.
Fig. 22 Intermodulation phenomenon [3].
2.3.2 Circuit Implementation
In addition to the considerations mentioned in the previous subsection, the most important issue in this thesis is low-voltage operation. With the targeted supply voltage down
to 0.6 V, there are limited numbers of suitable LNA topologies. Conventional cascode amplifiers require high supply voltage headroom, while single transistor amplifiers are prone to instability problem. In order to operate under a very low supply voltage, a folded cascode structure is adopted since it eliminates one level of transistor stacking [43].
Fig. 23 shows the schematic of differential LNA in the receiver, and Table V lists the detailed parameters of each device. In this schematic, MOS transistors Mn1 and Mn2, whose dimensions are decided by the illustration in Fig. 21 for low-noise consideration, act as common-source amplifiers; Mp1 and Mp2, which are common-gate amplifiers, perform current buffers with load inductors Ld1 and Ld2. As a result of this circuit topology, more voltage headroom can be used to bias the MOS transistors in saturation region, leading to an improved linearity. Also, reverse isolation is enhanced as conventional cascode structure behaves. Inductors Lc1 and Lc2 behave as DC current sources. They provide the necessary DC bias current without requiring extra voltage headroom, while presenting high impedances to the RF signals when resonating with the parasitic capacitances of the MOS transistors.
Besides, an additional advantage is to nullify the parasitic capacitances of the MOS transistors, resulting in an improvement of the noise figure [44]. Due to a specific quality factor of on-chip spiral inductor, the impedance of the inductor is limited at resonance compared to the impedance seen at the sources of the PMOS transistors Mp1 and Mp2. Thus, a portion of RF signals will be lost to the tank on account of current division. Finally, inductors Ls1 and Ls2 are used for matching the input resistance as mentioned in the previous subsection.
Fig. 23 Folded-cascode LNA.
Table V Detailed Parameters of the LNA Mn1, Mn2 50 μm / 0.18 μm Mp1, Mp2 115 μm / 0.18 μm
Ls1, Ls2 1 nr (0.805 nH) Lc1, Lc2 5.5 nr (14.5 nH) Ld1, Ld2 2 nr (2.04 nH) Rn1, Rn2, Rp1, Rp2 10 kΩ