Discussions and Comparisons

First, the problem of frequency shift in the QVCO circuit is discussed. By reviewing the layout, it is found that the interconnections between the spiral inductors and the QVCO core are too long to increase equivalent inductances due to parasitic effects. Except parasitic capacitances and resistors, the parasitic inductances of metal routes are not extracted by Calibre. Hence, a complete analysis of parasitics has to be adopted to obtain an accurate simulation results. The layout of spiral inductors including metal routes in the QVCO is simulated by ADS Momentum simulator. Each spiral inductor is analyzed by a method of two-port S-parameter network. Fig. 63 and Fig. 64 present the equivalent inductances and quality factors of each spiral inductor. An average inductance is 2.43 nH at 5 GHz, increasing 1.24 nH compared to the inductor model provided by TSMC. The quality factor is down to an

average value of 3.85. For the low quality factors, the output power of QVCO also reduces, resulting in a low conversion gain of receiver. Applying the analysis results of these spiral inductors with metal routes to the QVCO circuit, the revised simulated oscillation frequency of the QVCO can be tuned from 3.62 GHz to 3.8 GHz under a tuning voltage of 0 V to 1 V, and the output power decreases to -1 dBm. The revised simulation of oscillation frequency is close to the measured results.

Fig. 63 Equivalent inductances of spiral inductors in the QVCO.

Fig. 64 Equivalent quality factors of spiral inductors in the QVCO.

In addition, the receiver is re-simulated to verify measurement results. The oscillation signal of the QVCO is set to a frequency of 4.65 GHz, which is identical to the measured oscillation frequency. Fig. 65 plots the revised simulated conversion gain of the receiver, which is down to 14.2 dB. Revised simulated noise performance of the receiver is presented in Fig. 66. The SSB noise figure is 21.5 dB. Fig. 67 plots the IF output power related to RF input power, and the revised simulated 1-dB compression point is obtained with a value of -26.2 dBm. DC offset voltage is 3 mV with an injected input power of -50 dBm, shown in Fig.

68. Table XIII lists a summary of comparing the revised simulation with measurement, and it is observed that the revised post-simulation results are close to measurement.

Fig. 65 Revised post-simulation of conversion gain.

Fig. 66 Revised post-simulation of SSB noise figure.

Fig. 67 Revised post-simulation of 1-dB compression point.

Fig. 68 Revised post-simulation of DC offset.

Table XIII Summary of Revised Post-Simulation

Post-simulation Revised

Post-simulation Measurement

Technology TSMC 0.18-μm CMOS 1P6M

Supply voltage 0.6 V 0.6 V 0.65 V/0.7 V Power consumption 4.4 mW 4.4 mW 8.14 mW VCO tuning range 5.14-5.36 GHz 3.624-3.806 GHz 3.617-3.797 GHz Conversion gain 21.7 dB 14.2 dB 12.6 dB SSB noise figure 13.5 dB 21.5 dB 24 dB

P-1dB -33.6 dBm -26.2 dBm -24 dBm

DC offset 4 mV 3 mV < 3 mV

In order to alleviate the injury to circuit performance due to parasitic effects, the signal paths should be as short as possible in metal routes. A spiral inductor of center-tap type is applied to substitute the original spiral inductor of standard type. With two spiral inductors combined together, a center-tap spiral inductor can be connected to a differential circuit and thus shortens the interconnections between the inductor and core circuit while chip area is saved. Two center-tap spiral inductors are introduced into the original QVCO, shown in Fig.

69, and their equivalent inductances are 798 pH at 5 GHz, shown in Fig. 70. With a changed channel width of MOS transistors Mv1-Mv8, from 32.5 μm to 25 μm, a re-designed QVCO can be integrated with the designed receiver. Fig. 71 plots the tuning range of the re-designed QVCO compared with the original design. Besides, a summary of the re-designed receiver is listed in Table XIV.

Fig. 69 Layout configuration of the re-designed QVCO.

Fig. 70 Equivalent inductances of re-designed center-tap inductor.

Fig. 71 Simulated tuning range of the re-designed QVCO.

Table XIV Summary of the Re-Designed Receiver

Post-simulation Measurement

Post-simulation of re-designed receiver

Technology TSMC 0.18-μm CMOS 1P6M

Supply voltage 0.6 V 0.65 V/0.7 V 0.6 V Power consumption 4.4 mW 8.14 mW 3.8 mW VCO tuning range 5.14-5.36 GHz 5.07-5.3 GHz 5.134-5.366 GHz Conversion gain 21.7 dB 12.6 dB 21.2 dB

SSB noise figure 13.5 dB 24 dB 13.7 dB

P-1dB -33.6 dBm -24 dBm -32.5 dBm

DC offset 4 mV < 3 mV 4 mV

Another critical issue in measurement is to confirm the DC voltage of the net between Mi3 and Mi5 (Mi4 and Mi6) in the I-channel downconverter, which has to be adequate to ensure that Mi3 and Mi5 (Mi4 and Mi6) are in saturation region. A simulation including

device mismatches is utilized to simulate process variation on devices. Suppose a variation in the dimensions of MOS transistors is 10%, the DC voltage of the net between Mi3 and Mi5 varies in a range of 74 mV to 125 mV; in this range, Mi3 and Mi5 are also in saturation region, shown in Fig. 72. To avoid this problem, a modified circuit is proposed and presented in Fig.

73, where Mi5 and Mi6 are used to substitute for the original current source so that Mi3 and Mi4 are confirmed in saturation region.

Fig. 72 Simulated DC voltage with device variations on Mi3 and Mi5.

Fig. 73 Modified downconverter.

Table XV compares the designed receiver with three similar arts [12], [15] and [33]. A regular supply voltage of 2.5 V is applied to the first design, realized in 0.25-μm digital CMOS technology. It employs a double downconversion heterodyne architecture with a LO frequency of 2.6 GHz and applies offset cancellation to the baseband amplifiers. Placing the image around the zero frequency, the receiver achieves an image rejection ratio of 62 dB with no external components while minimizing the flicker noise upconversion in the first mixing operation. The design exhibits a low noise figure of 6.4 dB but an output offset voltage of 25 mV. The second design adopts a direct-conversion architecture and proposes a novel offset compensation circuit as the loads of mixer, which is introduced into this thesis. Under a low supply voltage of 1.1 V, this receiver fits the IEEE 802.11a specification and performs a low DC offset of less than 3 mV. The last design under a lower supply voltage of 0.8 V introduces a heterodyne architecture. Although this design performs a low noise figure of 7 dB and a good IIP3 of -1 dBm, it uses numerous inductors to achieve adequate conversion gain under a low supply voltage but covers a lot of chip area. Also, for a conventional double-balanced mixer operating well under such low supply, MOS devices with relatively large widths are adopted. Image-reject capability, a critical issue in heterodyne architecture, should be taken into consideration in this receiver.

Finally, a comparison of performance between the designed receiver and the IEEE 802.11a specification is listed in Table XVI. It is indicated that the re-designed receiver is able to fit the specification.

Table XV Comparison of Performance with Other Proposed 5-GHz Receivers

Technology 0.18-μm CMOS 0.25-μm CMOS

0.18-μm CMOS

0.18-μm CMOS

Architecture Homodyne Heterodyne Homodyne Heterodyne Supply voltage 0.6 V/0.7 V 0.6 V 2.5 V 1.1 V 0.8 V

Table XVI Comparison of Performance with IEEE 802.11a Specification

Post-simulation Measurement Post-simulation

of re-design Requirement Frequency band 5.14-5.36 GHz 4.56-4.68 GHz 5.134-5.366 GHz 5.15-5.35 GHz

P-1dB

-29.4 dBm

(without buffer) -24 dBm

-28.3 dBm

(without buffer) > -30 dBm SSB noise figure 13.5 dB 24 dB 13.7 dB < 15 dB

CHAPTER 4