CONCLUSIONS AND FUTRUE WORKS
4.2 Future Works
The re-designed circuits with modified spiral inductors should be fabricated to verify their functionalities. For more practicability, an automatic gain control (AGC) circuit, a channel select filter, and an ADC can be included to test the received packet error rate (PER), which is able to indicate linearity, noise and DC offset completely.
For time-varying DC-offset cancellation, a dynamic offset calibration scheme should be
adopted to cancel the DC offsets entirely. Besides, an additional circuit to introduce external LO signal to a receiver can make the measurement of other circuits in a receiver more convenient. Further, a frequency synthesizer can be included to acquire a stable LO signal.
REFERENCES
[1] IEEE Std. 802.11a, Part 11, Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High-speed Physical Layer in the 5 GHz Band, Sep. 1999.
[2] B. Razavi, “Challenges in Portable RF Transceiver Design,” IEEE Mag. Circuit and Devices, vol. 12, pp. 12-25, Sep. 1996.
[3] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice Hall, 1998.
[4] C. B. Guo et al., “A Fully Integrated 900-Mhz CMOS Wireless Receiver with On-Chip RF and IF Filters and 79-dB Image Rejection,” IEEE J. Solid-State Circuits, vol. 37, pp.
1084-1089, Aug. 2002.
[5] J. C. Rudell et al., “A 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications,” IEEE J. Solid-State Circuits, vol. 32, pp. 2071-2088, Dec. 1997.
[6] A. A. Abidi, “Direct-Conversion Radio Transceivers for Digital Communications,” IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, Dec. 1995.
[7] R. Hartley, “Modulation System,” U.S. Patent No.1666206, Apr. 1928.
[8] D. K. Weaver, “A Third Method of Generation and Detection of Single-Sideband Signals,” in Proc. IRE, vol. 44, Dec. 1956, pp. 1703-1705.
[9] A. Springer, L. Maurer, and R. Weigel, “RF System Concepts for Highly Integrated RFICs for W-CDMA Mobile Radio Terminals,” IEEE Trans. Microwave Theory and Techniques, vol. 50, pp. 254-267, Jan. 2002.
[10] B. Razavi, “A 2.4-GHz CMOS Receiver for IEEE 802.11 Wireless LAN’s,” IEEE J.
Solid-State Circuits, vol. 34, pp. 1382-1385, Oct. 1999.
[11] A. R. Behzad et al., “A 5-GHz Direct-Conversion CMOS Transceiver Utilizing Automatic Frequency Control for the IEEE 802.11a Wireless LAN Standard,” IEEE J.
Solid-State Circuits, vol. 38, pp. 2209-2220, Dec. 2003.
[12] B. Razavi, “A 5.2-GHz CMOS Receiver with 62-dB Image Rejection,” IEEE J.
Solid-State Circuits, vol. 36, pp. 810-815, May 2001.
[13] R. Harjani, J. Kim, and J. Harvey, “DC-Coupled IF Stage Design for a 900-MHz ISM Receiver,” IEEE J. Solid-State Circuits, vol. 38, pp. 126-134, Jan. 2003.
[14] Y. J. Jung et al., “A Dual-Mode Direct-Conversion CMOS Transceiver for Bluetooth and 802.11b,” in Proc. 29th ESSCIRC, Sep. 16-18, 2003, pp. 225-228.
[15] Y. Ding, Design of Low Voltage 5-GHz CMOS Direct-Conversion Front-End Receiver, M. thesis, Coll. of Electrical Engineering and Computer Science, National Chiao-Tung University, Hsinchu, Taiwan, Jul. 2004.
[16] K. Y. Lee et al., “Full-CMOS 2-GHz WCDMA Direct Conversion Transmitter and Receiver,” IEEE J. Solid-State Circuits, vol. 38, pp. 43-53, Jan. 2003.
[17] T. Yamaji and H. Tanimoto, “A 2GHz Balanced Harmonic Mixer for Direct-Conversion Receivers,” in Proc. CICC, May 5-8, 1997, pp. 193-196.
[18] Z. Zhang, Z. Zhiheng, and J. Lau, “A 900 MHz CMOS Balanced Harmonic Mixer for Direct-Conversion Receivers,” in RAWCON 2000, Sep. 10-13, 2000, pp. 219-222.
[19] I. Vassiliou et al., “A Single-Chip Digitally Calibrated 5.15-5.825-GHz 0.18-μm CMOS Transceiver for 802.11a Wireless LAN,” IEEE J. Solid-State Circuits, vol. 38, pp.
2221-2231, Dec. 2003.
[20] P. Zhang et al., “A 5-GHz Direct-Conversion CMOS Transceiver,” IEEE J. Solid-State Circuits, vol. 38, pp. 2232-2238, Dec. 2003.
[21] M. Lehne, J. T. Stronick, and U. Moon, “An Adaptive Offset Cancellation Mixer for Direct Conversion Receivers in 2.4GHz CMOS,” in Proc. ISCAS, vol. 1, May 28-31, 2000, pp. 319-322.
[22] J. Stonick et al., “Adaptive DSP Compensation for Analog Distortions in 2.4 and 5.8 GHz Transceivers,” CDADIC Technical Report, Jul. 1999.
[23] B. Razavi, Design of Analog CMOS Integrated Circuits, Boston, MA: McGraw-Hill, 1999.
[24] B. Razavi, “Design Considerations for Direct-Conversion Receivers,” IEEE Trans.
Circuits and Systems II, vol. 44, pp. 428-435, Jun. 1997.
[25] T. Melly et al., “A 1.3V Low-Power 430 MHz Front-End Using a Standard Digital CMOS Process,” in Proc. CICC, May 11-14, 1998, pp. 503-506.
[26] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd Ed., Boston, MA:
McGraw-Hill, 1999.
[27] B. Ravazi, “A 900-MHz CMOS Direct Conversion Receiver,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 12-14, 1997, pp. 113-114.
[28] S. Zhou and M. C. Chang, “A CMOS Passive Mixer with Low Flicker Noise for Low-Power Direct-Conversion Receiver,” IEEE J. Solid-State Circuits, vol. 40, pp.
1084-1093, May 2005.
[29] M. Zargari, “A 5-GHz CMOS Transceiver for IEEE 802.11a Wireless LAN Systems,”
IEEE J. Solid-State Circuits, vol. 37, pp. 1688-1693, Dec. 2002.
[30] C. H. Park, O. Kim, and B. Kim, “A 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I/Q Matching.” IEEE J. Solid-State Circuits, vol. 36, pp.777-783, May 2001.
[31] S. H. Wang et al., “A 5-GHz Band I/Q Clock Generator Using a Self-Calibration Technique,” in Proc. 28th ESSCIRC, Sep. 24-26, 2002, pp. 807-810.
[32] A. Parssinen, “A 2-GHz Wide-Band Direct Conversion Receiver for WCDMA Applications,” IEEE J. Solid-State Circuits, vol. 34, pp. 1893-1903, Dec. 1999.
[33] M. N. El-Gamal, K. H. Lee, and T. K. Tsang, “Very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications,” in Proc. IEE Circuits Devices Syst., vol. 149, Oct.-Dec. 2002, pp. 355-362.
[34] C. H. Chang, The Design of High-Output-Power RF Power Amplifier Using MOS Devices with Positive Substrate Bias, M. thesis, Coll. of Electrical Engineering and
Computer Science, National Chiao-Tung University, Hsinchu, Taiwan, Jul. 2004.
[35] H. T. Friis, “Noise Figure of Radio Receivers,” in Proc. IRE, vol. 32, Jul. 1944, pp.
419-422.
[36] H. S. Kao and C. Y. Wu, “An Improved Low-Power CMOS Direct-Conversion Transmitter for GHz Wireless Communication Applications,” in APCCAS 2002, vol. 1, Oct. 28-31, 2002, pp. 5-8.
[37] S. Y. Hsiao and C. Y. Wu, “A Parallel Structure for CMOS Four-Quadrant Analog Multipliers and Its Application to a 2-GHz RF Downconversion Mixer,” IEEE J.
Solid-State Circuits, vol. 33, pp. 859-869, Jun. 1998.
[38] C. Y. Wu and H. S. Kao, “A 2-V Low-Power CMOS Direct-Conversion Quadrature Modulator with Integrated Quadrature Voltage-Controlled Oscillator and RF Amplifier for GHz RF Transmitter Applications,” IEEE Trans. Circuits and Systems II, vol. 49, pp.
123-134, Feb. 2002.
[39] C. Y. Wu and C. Y. Chou, “A 5-GHz CMOS Double-Quadrature Receiver for IEEE 802.11a Applications,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 12-14, 2003, pp.
149-152.
[40] A. V. Ziel, “Gate Noise in Field Effect Transistors at Moderately High Frequencies,” in Proc. IEEE, vol. 51, pp. 461-467, Mar. 1963.
[41] D. K. Shaeffer and T. H. Lee, The Design and Implementation of Low-Power CMOS Radio Receivers, Norwell, MA: Kluwer Academic, 1999.
[42] N. G. Einspruch, Ed., VLSI Electronics: Microstructure Science, vol. 18, chap. 1, pp.
1-37, Academic Press, NY, 1989.
[43] E. Abou-Allam and T. Manku, “A Low Voltage Design Technique for Low Noise RF Integrated Circuits,” in Proc. ISCAS, vol. 4, May 31-Jun. 3, 1998, pp. 373-377.
[44] H. Samavati, H. R. Rategh, and T. H. Lee, “A 5-GHz CMOS Wireless LAN Receiver Front End,” IEEE J. Solid-State Circuits, vol. 35, pp. 765-772, May 2000.
[45] C. Y. Wu and H. S. Kao, “A 1.8 GHz CMOS Quadrature Voltage-Controlled Oscillator (VCO) Using the Constant-Current LC Ring Oscillator Structure,” in Proc. ISCAS, vol. 4, May 31-Jun. 3, 1998, pp. 378-381.