Simulation Results

Post-simulation is completed by HPICE for transient analysis and ADS simulator for other simulations with process parameters of TSMC 0.18-μm mixed signal 1P6M salicide 1.8V/3.3V RF SPICE models. The following are the post-simulation results of all circuits constructing the receiver.

■ LNA

LNA, locating on the first stage of the receiver, provides input matching, voltage gain and low-noise contribution for the receiver in a specific frequency band. Fig. 29 presents the simulated input matching (S11) of lower than -10 dB in a frequency range of 5.05 GHz to 5.45 GHz. Fig. 30 exhibits that the voltage gain is larger than 20.5 dB in the desired band. Fig.

31 is the simulation result of noise figure related to frequency. If the dimensions of the input MOS device are optimized for noise, the resultant noise figure is close to the minimum noise figure. To evaluate the linearity performance, two-tone test is introduced [3]. Two near-frequencyed signals are introduced into the LNA and then the LNA outputs signals of first order and third order, which is mentioned in subsection 2.3.1. Fig. 32 plots the power relation of the two terms on a logarithmic scale. The horizontal coordinate of the two-curved intersection point, called IIP3 (input third intercept point), is a parameter for linearity estimation. Also, 1-dB compression point (P1-dB), another parameter for linearity estimation, is obtained from Fig. 32.

Fig. 29 Simulated S11 of the LNA.

Fig. 30 Simulated voltage gain of the LNA.

Fig. 31 Simulated noise figure of the LNA.

Fig. 32 Two-tone test plot of simulated IIP3 of the LNA.

■ Downconverter

Fig. 33 shows the DC transfer characteristics of the downconverter with input voltages vRF and vLO between ±200 mV and ±300 mV, respectively, and the corresponding maximum differential output swing is ±174 mV. In practice, the IEEE 802.11a standard regulates a maximum input power of -30 dBm, after amplified by the designed LNA, signal power increases to -10 dBm, i.e. ±100 mV, so the maximum input amplitude fed into the downconverter is around ±100 mV; therefore, the corresponding maximum differential output swing is ±93 mV with a maximum-scaled linearity error of 7% (7 mV/100 mV = 7%). An output buffer stage follows the downconverter. Fig. 34 is the results probed at the output of the buffer. The quadrature downconverted IF signals are at a frequency of about 10 MHz. For partial positive-substrate-biased MOS transistors, an issue of power dissipation resulting from bulk current is considered. The bias statuses of positive-substrate-biased MOS transistors are listed in Table VIII.

Fig. 33 Simulated DC transfer characteristics of the downconverter.

Fig. 34 Simulated quadrature IF waveforms (solid-line: I-channel, dot-line:

Q-channel).

Table VIII Simulated Bias Statuses of Positive-Substrate-Biased MOS Transistors Bulk-biased voltage Bulk-biased current

Mbi1-Mbi4, Mbq1-Mbq4 0.35 V 45.6 nA Mi5, Mi6, Mq5, Mq6 0.3 V 9.38 pA

Mi7, Mq7 0.3 V 6.84 pA

■ Quadrature voltage-controlled oscillator

Fig. 35 presents the LO spectrum, where a desired tone at 5.25 GHz is observed. Fig. 36 and Fig. 37 are sequentially quadrature LO waveforms and the plot of tuning range, respectively. The quadrature VCO oscillates from 5.14 GHz to 5.36 GHz with under a tuning voltage of 0 V to 1 V. When the oscillation frequency is 5.25 GHz, the phase noise is -106.4 dBc at 1-MHz offset, shown in Fig. 38.

Fig. 35 Simulated LO spectrum.

Fig. 36 Simulated quadrature LO waveforms (solid-line: I-channel, dot-line:

Q-channel).

Fig. 37 Simulated tuning range of the quadrature VCO.

Fig. 38 Simulated phase noise of the quadrature VCO.

■ Overall

Fig. 39 plots the simulated conversion gain of the receiver. By sweeping the frequency of RF signal with an LO frequency of 5.24 GHz, the conversion is about 21.7 dB in the desired band, and the corner frequencies at 150 kHz and 10 MHz are observed. Noise performance of the receiver is presented in Fig. 40. Selecting the noise bandwidth from 150 kHz to 10 MHz, the SSB noise figure is 13.5 dB after calculation. Two-tone test is applied to simulate the linearity of the receiver. Two RF signals at 5.245 GHz and 5.255 GHz are fed into the receiver

and downconverted by a LO frequency of 5.24 GHz and then the receiver outputs IF signals of first order and third order. Fig. 41 plots the output power of the two terms relative to RF input power on a logarithmic scale. The input third order intercept point (IIP3) and 1-dB compression point are acquired. The output buffer is taken into account in this simulation, and the 1-dB compression point would increase a value of 4.2 dB if the output buffer is excluded.

For second-order distortion, the input second order intercept point (IIP2) is also simulated and plotted in Fig. 42.

As a result of a DC-offset compensation circuit applied to the receiver, DC offset voltage is also simulated. A RF signal with an identical frequency to LO signal is fed into the receiver to simulate self-mixing phenomenon. After self-mixing, a DC offset voltage is appeared at the output terminals of the downconverter and thus influences bias status. By sweeping the power levels of input RF signal, the DC offset voltages at differential IF output terminals are plotted in Fig. 43. With an injected input power of -50 dBm, the DC offset voltage is about 4 mV.

Besides, the DC offset voltages at the outputs of each stage are listed in Table IX. In conclusion, a simulation summary of the receiver is listed in Table X.

Fig. 39 Simulated conversion gain of the receiver.

Fig. 40 Simulated noise figure of the receiver.

Fig. 41 Two-tone test plot of simulated IIP3 of the receiver.

Fig. 42 Two-tone test plot of simulated IIP2 of the receiver.

Fig. 43 Simulated DC offset at each stage.

Table IX Detailed Simulated Results of DC Offset at Each Stage Injected input power LNA output Downconverter output Buffer output

-60 dBm 0.36 μV 1 mV 3 mV

-50 dBm 0.93 μV 2 mV 4 mV

-40 dBm 1.69 μV 8 mV 13 mV

-30 dBm 2.97 μV 20 mV 36 mV

-20 dBm 24.1 μV 61 mV 108 mV

Table X Post-Simulation Summary of the Receiver

Technology TSMC 0.18-μm CMOS 1P6M

Supply voltage 0.6 V

Frequency band 5.15-5.35 GHz

S11 (< -10 dB) 5.05-5.45 GHz

Power consumption 1.45 mW

Conversion gain 1 dB

Noise figure 21 dB

Downconverter

Power consumption 0.48 mW

Tuning range 5.14-5.36 GHz

KVCO 220 MHz/V

Output power 3 dBm

Quadrature VCO

Power consumption 2.5 mW

Conversion gain 21.7 dB

SSB noise figure 13.5 dB

-29.4 dBm (without buffer) P-1dB

-33.6 dBm (with buffer)

IIP3 -24 dBm (with buffer)

DC offset (with an injected power of -50 dBm at receiver input)

4 mV Overall

Power consumption 4.4 mW

CHAPTER 3

EXPERIMENTAL RESULTS

The receiver front-end are designed and fabricated. This chapter describes layout, measurement setup and experimental results. The measured results are taken into discussions and compared with post-simulation results.