CHAPTER 4. THE FORWARD CONVERTER USING THE PROPOSED
4.3 Design procedure
2
(
) )(
(
3 2 2
3 3 1
2 2 3
2 1
1 −
⋅ ⋅ +
⋅
⋅
⋅
−
= ⋅
m o s
o m
s o
c
N
L n
V T n
n I n n n L
T n n V n V L
L (4.24)
or
1
2 3
2 2 2
1 2
2
3 2 2 2
1
2
) (
) 1
(
N
m s o
o o
m c c
o s
c
L L
n T V n
V I
t Sin V n V
V n T V
V
L −
⋅
⋅ ⋅ +
−
⋅
−
=
ω
(4.25)
4.3 Design Procedures
The method for designing the circuit of control loop and determining the voltage stresses of components voltage for the proposed converter is similar to that for designing the conventional forward converter. However, the transformer design needs more calculations and considerations since three windings are designed in this converter. The design method for transformer is shown as following.
1) Windings turns ratio n1/n2/n3: The turn ratio n2/n3 can be obtained from equations (4.1)-(4.2) by using the substitutions of the given Vm,min, Vm,max, Vo, Dmax, and ωt1,min, where Vm,min and Vm,max is the amplitude of minimum line voltage and maximum line voltage respectively, Vo is typical output voltage, Dmax is the maximum duty ratio, and 0.4≦Dmax≦0.45. The corner angle ωt1,min,
0< tω 1,min ≤π4, can be obtained as long as Vm,min is chosen. The detailed steps for obtaining the turn ratio n2/n3 is depicted as follows:
(i) Let VC2 be chosen lower than 420V at Vin=265V.
(ii) Assume that VC2 is proportional to Vin. Then VC2≒85×(420/265)=134.7V at Vin=85V.
(iii) Let Vo=48V, Dmax=0.4 then 48=134.7×(n3/n2)×0.4, n3/n2≒0.8.
(iv) Let ωt1,min=0.24, Vm,min≒120V, Vo=48V, Dmax=0.4, and n2/n3=1.2. Then the substitutions of all the data to equation (4.3) gives n1/n2≒1.0.
2) Magnetic inductance Lm and LN1: Magnetizing current iLm stores energy to charge bulk
capacitor, so it is recommended to 20 percent of the primary load current.
Lm s C
m i
T D L V
∆
= 2⋅ max , (4.26)
where %∆iLm ≈iN2(t1,M1)⋅20 .
The inductance LN1 can be yielded in equation (4.27)
2 2 1/ ( 1)
n L n
LN m = , (4.27) where n2 can be obtained by solving Faraday’s law,
) /(
) ( 2 max
2 V D T AdB
n = C ⋅ s e . (4.28) Ae is effective area of core and dB is flux density change in transformer core.
3) Series inductance L1: The inductance L1 can be yielded by putting above parameters in equation (4.25).
4) To confirm dB<Bmax : The maximum change value of magnetic flux density has to limit under maximum magnetic flux density for the selected magnetic material.
Given Lm⋅diLm = N2 ⋅dB⋅Ae or
Ae N
di dB Lm Lm
⋅
= ⋅
2
, where diLm can be calculated by substituting DTs for (t-t0,M2) in equation (4.14), Ae is the effective area of the selected magnetic core.
] )
(
[ 1 0, 2 2 DTs L t V
i di
m C M
N
Lm = + ; max
2
Ae B N
di Lm m
⋅ <
⋅ .
4.4 Experimental Results
The proposed structure has been tested under the specifications of 85V~265V/ac input voltage range, 50V/dc output voltage, and 100w output power. The turn ratio of n1/n2/n3 is 27/23/12 and the inductance L1<<LN1, where L1=30uH and transformer core PQ32/20 is used.
The transformer core employed in previous similar converter should be EER35 in [4] and [7].
Although numerous previous similar converters have the transformer core size similar to that of the proposed converter in similar given output power and switching frequency, the boost
inductors sizes, 58uH-240uH in [4], 1.4mH in [7] or 1.7 times the magnetic inductance [28], are several times the L1 in the proposed converter. The sizes of the boost inductors employed in [4] and [7] are still several times of L1 when flowing a similar line current in the proposed converter. Figure 4.9 illustrates the line current in a full line cycle. Experiments have verified that the harmonic distribution complies with a standard of IEC 61000-3-2. Table 4.1 demonstrates that the detailed harmonic distribution of the prototype design meets the requirements of class D.
Figure 4.10 illustrates dynamic response switching between a half and a full load under 110V/ac input voltage. The output voltage of the prototype displays a fast response and stable regulation. Moreover, Fig. 4.11 illustrates the voltages across the bulk capacitor for different input voltages under a full load. The voltage of the bulk capacitor depends on Vac and turn-ratio n1/n3 but it is almost independent of load current. The maximum voltage can be held below 450V/dc, a popular commercial voltage in the market for electrolytic capacitors, by adjusting turn-ratio n1/n3.
Vac, 100V/div
Iac, 1A/div
Vac, 100V/div
Iac, 1A/div
Fig. 4.9 iac & Vac waveform at Vac=110v ,Io=1.5A
Vo, 20V/div Vac, 100V/div
iac, .5A/div
Io, 1A/div Vo, 20V/div Vac, 100V/div
iac, .5A/div
Io, 1A/div Vo, 20V/div Vac, 100V/div
iac, .5A/div
Io, 1A/div Vo, 20V/div Vac, 100V/div
iac, .5A/div
Io, 1A/div
Fig. 4.10 Dynamic response waveforms for Vac, iac, Vo and Io when Vac=110V, Vo=50V and Io=0.5A/1A
Vc2, voltages across bulk capacitor
150 200 250 300 350 400 450
85V 110V 150V 220V 260V
Vac
Vc2
2A/Io 1A/Io 0.6A/Io
Fig. 4.11 Voltage stress of bulk capacitor VC2 and line voltage Vac
Table 4.1 The major harmonic components of the line current iac(A)
Harmonic number
Table 4.2 illustrates the voltage stress in S1, voltage across bulk capacitor C2 and efficiency η. The voltage stress in S1 is over 450V when input voltage Vin is over 260V.
Therefore, an extended type with two switches forward converter can be adopted if user wants to reduce the voltage stress in S1. The efficiency is penalized due to part of the power being processed twice. Moreover, that the converter operates in DCM at the current iN1 also causes the efficiency being slightly decreased.
4.5 Extension Circuit
The voltage stress across main switch in primary side will be over 500V when the proposed Forward converter is applied in wide range input voltage up to 265V. The high voltage stress will cause two drawbacks, expensive cost in MOSFET and high switching loss in the MOSFET. Therefore, an extension circuit is introduced to prevent the switch from the high voltage stress.
The extreme voltage stress on main switch can be obtained from equation (4.17).
2 1
1 1
1 2 2
2 2
) ) (
( C
N N in
C C
ds V
L L n
L V n
V V
V <
⋅ +
− +
= , (4.29) Based on the data of prototype, the maximum voltage stress Vds is no more than 860V where V is 430V at input voltage 265V.
Table 4.2 Voltage stress of S1, Voltage across bulk capacitor C2 and efficiency η.
Vin [V] VS1 [V] VB [V] η[%]
90 315 221 72 110 326 241 74 130 332 258 75.4 220 431 371 76 230 452 389 76.5 260 482 425 76.1
Figure 4.12 is the extension circuit, a twin-transistors type Forward converter, based on the proposed Forward circuit. The circuit adds a switch S2 and the switch’s operation is synchronous in S1. Except the additional switch, there is no difference in comparing to the proposed Forward converter. The additional transistor can share a half voltage-stress in the single transistor Forward converter. Therefore, the high voltage stress issue can be released via the proposed twin-transistors Forward converter.
N1N2 N3
Fig. 4.12 The proposed twin transistors forward converter.
CHAPTER 5
THE FULL-BRIDGE CONVERTER USING THE PROPOSED INPUT CURRENT SHAPER
A Full-bridge AC/DC converter, with the functions of harmonic current elimination and fast output transient response, is proposed as shown in Figure 5.1. The circuit is a single-stage AC/DC converter consisting of 4 switches S1-S4, an input filter C1, a bulk capacitor C2, an inductor L1 and a transformer with two primary windings N1&N2, where N1 plays a role of magnetic feedback winding. The winding N1, inductor L1and diode D5&D6 form an input current shaper. The winding N1, inductor L1, diode D6&D3 (or D5&D1), switch S2 (or S4) and bulk capacitor C2 forms a boost circuit. The winding N2&N3, a bulk capacitor C2, switches S1-S4, diodes D7, D8, inductor L2 and output capacitor C3 forms a full-bridge converter. The switches S1~S4 are always MOSFETs so D1~D4 are the body diode in switches S1~S4.
The control method adopts a conventional fixed-frequency voltage mode control. The experimental results have shown that even using a popular fixed-frequency controller TL494, the line current of the proposed ac/dc converter can comply with the standard IEC 61000-3-2 and the converter also can have fast load dynamic response.
RL Vac Lf
Cf
Dr
C1
C2
L1
D1
D2 D3
D4
D5
D6 S1
S2 S3
S4
n1 : n2: n3
iac
iN1
iD5
iD6 iN2
iS4
iS2 iS1 iS3
V+C1
-VC2 +
-VL1 +
-C3 L2
D7
D8 iD7
iD8
iL2 VO +
-VN2
+
-VN3 +
-VN1
+
-im VD6+
-RL Vac Lf
Cf
Dr
C1
C2
L1
D1
D2 D3
D4
D5
D6 S1
S2 S3
S4
n1 : n2: n3
iac
iN1
iD5
iD6 iN2
iS4
iS2 iS1 iS3
V+C1
-VC2 +
-VL1 +
-C3 L2
D7
D8 iD7
iD8
iL2 VO +
-VN2
+
-VN3 +
-VN1
+
-im VD6+
-Fig. 5.1 Proposed Full-bridge AC/DC converter
5.1 Basic Operation Theories
The operation principle of the proposed converter is somewhat similar to the boost-based forward AC/DC single-stage isolated power-factor-corrected power supply in the Chapter 4.
Magnetic energy is stored in inductor L1, used as an energy-flow switch, when switch S1&S2
are on. Electric energy will be delivered to bulk capacitor C2 through L1 when switch S1&S2
turn off. Windings N2 and N3 provide the energy storing and transferring components of the full-bridge stage. Winding N1 provides a path to charge L1 and also transfers the line energy to output loads in the duty on duration. In the duty off duration while L1 still conducts, winding N1 also induce current iN1×(n1/n3) to secondary side. However, when the line voltage is greater then the winding voltage VN1/2 in the duty on duration, the power line can more strongly charges C2 through L1 and winding N1. In the charging duration of C2, the line current |iac| is greater than zero and grows fast as the waveform shown in time duration t1-t3 of Fig. 5.2.
Thus, the slope of VC2 is positive during t1-t3 and negative in other duration in each half line cycle. The resulting waveform of VC2 is sketched in Fig. 5.2. In this circuit the capacitor C2 is arranged with a capacitance similar to that used in conventional AC/DC full-bridge converters.
Since C2 is large so that VC2 can approximate to its average voltage, VC2,av. The proposed circuit has two operation modes. Figure 5.2 shows these two operation modes that appear mirror-symmetrically in each quarter of a line cycle. Figure 5.3 shows the relative voltage and current waveforms in one switching cycle in two operation modes.
In this circuit, L2 is designed in the operation of continuous conduction mode. Since VC2 is almost invariant, the duty ratio D can be approximate to constant one in the whole line cycle for fixed load. The circuit analysis will be presented in the following sections. Therefore, a duty cycle D will be assumed constant in these two operation modes and the analysis of L2 will be taken according to the theorem of voltage-second balance in steady state design consideration.
M1
Fig. 5.2 Operation modes in one half of line cycle
t0,M1
Fig. 5.3 Voltage and current waveforms in a switching cycle in the two modes
5.1.1 Operation Modes M1 or M4 (during t0-t1 or t3-Tl /2)
Within this mode, the line current |iac| and iN1 are zeros. The operation principle of the converter is the same as that working in the conventional full-bridge converter. Since C2 is large enough, VC2 can approximate to a constant value during a line cycle. The output conductance L2 and capacitance C3 provide a good low pass. Thus the output voltage can be regarded to a constant value and can be obtained as
n D V n
Vo = C ⋅ ⋅
2 2 3
2 , (5.1)
where D is defined as
1 , 0 1 , 2
1 , 0 1 , 1
M M
M M
t t
t t
−
− in mode M1 or
2 , 0 2 , 3
2 , 0 2 , 1
M M
M M
t t
t t
−
− in mode M2. Since the
capacitance C2 is assigned large, VC2 is assumed constant. Thus, for fixed load the duty ratio D can be assumed approximate to a constant in mode M1 and M2.
Since M2 starts at the time when VC1 reach toVN1. Thus, the time bound of mode M1 can be obtained by
3 1 2
1 2
BD 2
V D n
V n n
VC n o
⋅ ⋅
=
⋅
= (5.2)
or
) (
sin
3 1 1
1 D n
n V t V
m o
⋅ ⋅
= −
ω (5.3)
Fig. 5.4 Current loops while (a) S1&S2 turn on, (b) S1&S2 turn off, (c) S3&S4 turn on, and (d) S3&S4 turn off in M1/M4
1) In t0,M1≦t<t1,M1 S1&S2 and D7 are on, D5, D6, and D8 are off. The capacitor C2 discharges through S1, N2 and S2 to ground. The magnetic current iLm has an initial value that flows in inverse direction at t0,M1 and is left in the previous operation and the magnetic energy will be transferred to load through N3 in the duration when iLm is still negative. The magnetic current keeps increasing linearly and changes to positive direction before t1,M1. The induced current iN3 flows through D7, L2, C3, and RL. Since VC1 is smaller than VN1/2, L1 will not conduct in this mode.
2) In t1,M1≦t<t2,M1 D7 and D8 are turned on, S1 and S2 are off. Since L2 is large and operates in CCM, iL2 is always large and forces both output regulators D7 and D8 conducting in the whole duty off duration.
3) In t2,M1≦t<t3,M1 S3&S4 and D8 are on, D5, D6, and D7 are off. The operation functions held in t0,M1-t1,M1 duration will also symmetrically happen in the other half circuit. The capacitor C2 discharges through S3, N2 and S4 to ground. The magnetic current iLm has an initial value that flows in inverse direction at t2,M1 and left in the previous operation and the magnetic energy will be transferred to load through N3 in the duration when iLm is still positive.
Vac Lf Cf
Dr
C1
C2 L1
D1
D2 D3
D4
D5
D6 S1
S2 S3
S4
n1 : n2: n3
iac
iN1
iD5
iD6 iN2
iS4
iS2 iS1 iS3
VC1 +
-VC2 +
-VL1 +
-C3 L2 D7
D8 iD7
iD8
iL2 VO +
-VN2
+
-VN3 +
-VN1
+
-im VD6+
-iC2
RL Vac Lf
Cf
Dr
C1
C2 L1
D1
D2 D3
D4
D5
D6 S1
S2 S3
S4
n1 : n2: n3
iac
iN1
iD5
iD6 iN2
iS4
iS2 iS1 iS3
VC1 +
-VC2 +
-VL1 +
-C3 L2 D7
D8 iD7
iD8
iL2 VO +
-VN2
+
-VN3 +
-VN1
+
-im VD6+
-iC2
RL
(d) t3,M1≦t<t4,M1
The magnetic current keeps decreasing linearly and changes to negative direction before t3,M1. The induced current iN3 flows through D7, L2, C3, and RL. Since VC1 is smaller than VN1/2, L1
will not conduct in this mode.
4) In t3,M1≦t<t4,M1 D7 and D8 are turned on, S3 and S4 are off. Since L2 is large and operates in CCM, iL2 is always large and forces both output regulators D7 and D8 conducting in the whole duty off duration.
Summing the descriptions above give the following results:
⎩⎨
⎪⎪
For the purpose of iL2 operating in CCM, the inductance L2 has to conform to the following constraint. Let iD7≧0 at t2,M1 in equation (5.7) can obtain the constraint.
) and S2. Simultaneously D7 starts to turn on and the power is delivered to the load. When S1
and S2 turn off, the current iN1 starts to charge capacitor C2 through L1, winding N1, D5, D6, D1, and D3 and linearly decreases to zero at time t2,M2. Simultaneously D7 and D8 will continuously turn on and the power is delivered to the load. Figure 8 shows current loops in
three operation stages in mode M2/M3.
1) In t0,M2-t1,M2 S1, S2, D6, and D7 are on, D5 and D8 are off. The capacitor C2 begin to discharge through N2, S1, and S2 to ground. That the input voltage Vac is larger than VN1/2 results in the difference voltage of Vac-VN1/2 dropped across on L1. Hence the current iN1
begins to linearly increase from t0,M2 to t1,M1. When the current iN1 linearly increases as shown in Fig. 5.4 (a), the current iN1 will induce part of iN3 while the other part is provided by iN2. Since winding N2 is connected to VC2 through S1 and S2, the current im will increase linearly from negative to positive one as shown in Fig. 5.3. Therefore, iN2 must provide the current needed by im and part of iN3, the other part of which is provided from N1.
2) In t1,M2-t2,M2 D1, D3, D5, andD6 are on, S1 and S2 turn off. This duration ends at the time when iN1 falls to zero. The current iN1 starts to decrease and simultaneously provides a path to charge C2 through L1, N1, D5, D6, D1, and D3. While consider the current continuity of the bottom part of winding N1, the net current iD8 – iD7 of winding N1, will induce net current iD6-iD5 to winding N3. The output inductance current iL2, that is designed to operate in CCM, will force both the diodes D7 and D8 conducting together. Therefore, VN3 is approximate to zero and results in VN1 being approximate to zero too. Consequently, the remaining magnetic current im will be diverted to windings N3. Thus, im can be formulated by
2 5 1 6 2 7 3
8 ) ( )
( n
i n n i
i n i
im = D − D ⋅ + D − D ⋅
3) In t2,M2-t3,M2 D7 and D8 are on, D1, D3, D5,D6 , and S1 and S2 turn off. The current iN1 is zero . This situation implies that the energy stored in L1 has released to C2. The magnetic current im keeps almost a constant value since winding N3 is still in shorted-circuit state and diverts to winding N3. In this duration, the difference of iD8 and iD7 is kept near constant.
4) In t3,M2-t6,M2 These time durations have same operation theory as described in the three statements above held in t0,M2-t1,M2.
The related equations are explained as followings. equations.
s
⎪⎪
⎪⎪
5.2. Analysis of Converter Operation