Fabrication and Characterization of Quantum Well MOSFET
3.2 Device Characterization [1]
3.2.1 DC Measurement
The I-V behaviors of the transistors were characterized in terms of the output and the transfer characteristics. The figures of merit (FOMs) representing device logic performance can be extracted and evaluated by DC measurement. The principles and operational definitions of the extracted FOMs are briefly described in the following paragraphs.
Threshold Voltage (VT)
The VT is a fundamental parameter for MOSFET modeling and characterization.
This parameter, which stands for the onset of significant drain current flow, has been given several operational definitions. Most of the proposed procedures are based on the measurement of the drain current versus gate voltage (ID-VG) characteristics of the transistor. Typical extraction methods bias the transistor at low drain voltage, so that the device operates in the linear region.
There are three commonly used methods that bias device in the linear region: 1) constant current (CC) method, which defines VT as the gate voltage corresponding to the constant drain current, ID of 1mA/mm; 2) transconductance linear extrapolation (TLE) method, which defines VT as the gate voltage axis intercept of the linear extrapolation of the gm-VG curve at its maximum first derivative point; 3) extrapolation in the linear region (ELR) method, which defines VT as the gate voltage axis intercept of the linear extrapolation of the ID–VG curves at its maximum transconductance point.
It is obvious that CC method determines VT in a simple manner, but the CC method has the severe disadvantage of being totally dependent of the arbitrarily chosen value of the ID level. On the other hand, the assumptions behind TLE method are that: 1) in weak inversion region, gm increases exponentially with VG; 2) in the transition region between weak and strong inversion, gm increases linearly with VG; 3) in the strong inversion region, gm decreases with VG due to the series resistance and
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mobility. In this work, we choose the most popular one － ELR method to extract device VT.
Subthreshold Swing (SS)
The SS is the FOM reflects the electrostatic control of the transistor. The SS is defined as:
The SS of surface channel MOSFETs can be expressed as:
) thermionic limit of MOSFETs. However, for nowadays nano-scale logic MOSFETs, the SS increases with the scaled gate length due to SCEs. Moreover, the SS degradation is also attributed to the interface states between gate oxide and semiconductor. The introduction of high-k gate stack makes the SS degradation more significant, since the interface is poorer than Si/SiO2 system. This issue is even worse for III-V MOSFETs with high-k gate stack, because of the large amount of interface states on the III-V surface. Note that the SS of QW-MOSFETs is different from surface channel MOSFETs. The equation and the details of derivation are presented in the Appendix (A.3).
Drain-induced Barrier Lowering (DIBL)
The DIBL is also a parameter monitoring the short channel effects. The DIBL is defined as: phenomenon can be understood from Fig. 3.5, in which the surface potential of long channel and short channel MOSFETs are plotted. As the VD increases, the conduction band edge near the drain side is pulled down. For long channel devices, this phenomenon does not have strong influence on the leakage, since the pulled-down
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region does not reach the source side. However, for short channel devices, the surface potential near the source side is pulled down by the VD, resulting in a significant drain leakage and a lowering in device VT.
In practice, we prefer to use two drain biases, 0.5 V and 50 mV, to extract the value of DIBL, since the devices studied in this work is for low-power logic application, the VD is expected to be lower than 1 V.
3.2.2 RF Measurement
The microwave characteristics are usually characterized by using vector network analyzer (VNA) to obtain the scattering parameters. Typical FOMs, such as fT and maximum oscillation frequency (fmax), can be extracted by interpreting the scattering parameters. The principles and operational definitions of scattering parameters and the extracted FOMs are introduced as the follows.
Two-port Scattering Parameters
The scattering parameters, or called S-parameters, are the fundamental to microwave characteristics of a linear network. It is difficult to measure Z-, Y-, or H-parameters since the device are unstable at open/short conditions. S-parameters measurement uses the matched load (50Ω) instead of open/short circuit conditions, so it is easier to be obtained at high operation frequency. Therefore, the FOMs of device RF characteristics can be extracted by S-parameters, such as gain, return loss, voltage standing wave ratio (VSWR), and reflection coefficient and amplifier stability.
The relationship between the reflected, incident power waves and the S-parameter matrix is expressed as:
)
The electrical field of the signal going into and leaving the ports are denoted as a and b, respectively. And the subscripts, 1 and 2, represents the input port and the output port respectively.
Therefore, s11 is the input voltage reflection coefficient, defined as b1/a1 at a2 = 0;
s12 is the reverse voltage gain, defined as b1/a2 at a1 = 0; s21 is the forward voltage gain, defined as b2/a1 at a2 = 0; s22 is the output port voltage reflection coefficient,
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defined as b2/a2 at a1 = 0.Therefore, the properties of two-port network are then given by:
Current gain cut-off frequency (fT)
The fT is a more appropriate FOM for digital circuits, in which speed is the primary concern. The operational definition of fT is the frequency corresponding to the current gain (h21) becomes unity (0 dB), where h21 is given by:
For surface channel MOSFET, the fT can be approximated as:
)
where C’par is the total input parasitic capacitance.
Maximum oscillation frequency (fmax)
The fmax is more relevant for analog applications, since it is defined as the frequency corresponding to the power gain/ unilateral gain becomes unity (0 dB). The unilateral gain, U, is given by
(3.7)
For surface channel MOSFET, the fmax can be approximated as:
)
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Table 3.1 The fabrication process of InAs QW-MOSFET.
Modules Steps Remarks
1. Device isolation Photolithography
Mesa isolation InGaAs/InAlAs etching H3PO4: H2O2: H2O =1:1:80
InP etching
HCl: H3PO4: H2O = 1:1:1 PR strip
AEI Etch depth: 220 nm (to buffer layer) 2. EBL alignment
mark formation
Photolithography
Metallization Native oxide etching HCl: H2O =1:10
Ti/Au = 50/150 nm
250℃ annealing for 30 sec 3. Cap-recess E-beam
lithography
Resist: ZEP-520A
Cap etching Critic acid-based solution
Succinic acid-based solution
PR strip ZDMAC
Metallization Au/Ge/Ni/Au=20/40/140/250 nm
Lift-off process 6. Gate formation E-beam
lithography
Resist: PMGI/ZEP-520A Metallization Ti/Au = 50/250 nm
Lift-off process 7. Passivation Device
passivation
PECVD 100-nm Si3N4 Photolithography
Via etching PR strip
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Fig. 3.1 Process flow of buried-channel gate-last QW-MOSFET.
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Fig. 3.2 Cross-sectional SEM image of cap-recess EBL (a) resist profile (b) resist thickness. The resist used in this EBL is ZEP-520A.
(a)
(b)
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Fig. 3.3 SEM image of the gate stripe. The gate length of the fabricated QW-MOSFETs in this work is about 250 nm.
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Fig. 3.4 Schematic device structure of the InAs QW-MOSFETs in this work.
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Fig. 3.5 Effect of DIBL on the threshold voltage of short channel devices.
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Chapter 4
Device Bandgap Engineering
In order to investigate the bandgap engineering of composite channel, we used both theoretical and experimental approaches. For the theoretical analysis, a technology computer aided design (TCAD) tool, nextnano, was used to capture and visualize the theoretical analysis. For the experimental study, three kinds of QW-MOSFETs with different epitaxial structures were fabricated and characterized.
Through DC and RF measurements, the experimental analysis was also conducted in order to examine the effect of epitaxial structure on the performance of InAs QW-MOSFETs.
4.1 Effect of Epitaxial Structure on Carrier Confinement and Mobility 4.1.1 Thickness of InAs-core and InGaAs Sub-channels
In order to study the influence of InAs-core thickness on the carrier confinement in the InAs-core and the apparent mobility of the entire epitaxial structure, two In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As/In0.52Al0.48As structures with different composite channel thickness (i.e., InGaAs/InAs/InGaAs of 5/5/5 and 5/2/5 nm) were simulated. The band diagrams, the eigenvalues of sub-bands, and the wavefunction (i.e., |φ|2) in each sub-band of these two quantum well (QW) systems were solved by Poisson-Schrödinger solver. The numerical results are shown in Fig. 4.1 and Fig. 4.2.
In Fig. 4.1, we can see that the first sub-band “height”, which is defined as the difference between first sub-band and the condition band of InAs, of thin-core structure is higher than the thick one (i.e., 112 mV vs. 74 mV). Obviously, this result is due to the thickness of center InAs layer. The InAlAs/InGaAs/InAs/InGaAs/InAlAs structure is essentially a QW system, in which the thickness of composite channel determines the “width” of this QW. The thinner InAs-core corresponds to higher and more discrete eigenvalues (i.e., larger energy separation between sub-bands).
In Fig. 4.2, the electron distribution of the structures with thin-core (blue) and thick-core (black) are shown. We can see that the thin-core structure has higher peak
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in the center. However, it does not lead to more electrons dwell in the InAs layer, since the total number of the electrons in the core is the area under the probability curve within the InAs layer. In this case, the thin-core structure has fewer electrons in the high-mobility InAs layer due to the scaled InAs thickness. Therefore, the apparent mobility of the simulated thin-InAs structure is lower than the thick one in this case.
This result suggests that the scaling of the InGaAs/InAs/InGaAs structure should employ the scaling of both InAs and InGaAs layer; otherwise the reduced area in the InAs region will slightly degrade the apparent mobility of the entire structure.
This suggestion can be verified by the experimental result. Three epitaxial structures (shown in Tables 4.1, 4.2, and 4.3) with InGaAs/InAs/InGaAs of 4/5/4, 3/2/3, and 1/2/1 nm are grown by molecular beam epitaxy (MBE), and their Hall mobility are characterized to examine the effect of the composite channel thickness on the apparent mobility. It is shown that the measured Hall mobility of 4/5/4-structure is 13,500 cm2V-1s-1, which is higher than 3/2/3-strucuture (11,500 cm2V-1s-1) and 1/2/1-structure (11,100 cm2V-1s-1). We can see that although the 3/2/3-structure and 1/2/1-sturcture has the same InAs-core thickness, thinner InGaAs sub-channel leads to lower Hall mobility since more carriers dwells outside the high-mobility InGaAs/InAs/InGaAs composite channel. The previous deduction can also be verified by simulations. The In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As/ In0.52Al0.48As QW systems with two kinds of InGaAs/InAs/InGaAs thicknesses, 3/2/3 and 1/2/1 nm, are shown in Fig. 4.3. Even though the peak population of in InAs region for 1/2/1-structure is higher than 3/2/3-structure, the 1/2/1-strcucture has more electrons outside the composite channel, leading to the small mobility degradation. The result of Hall measurements also manifested the fact that the thickness ratio (TR) of InGaAs sub-channel to InAs-core, TR = tInGaAs/tInAs, should be scaled during the optimization of composite channel.
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4.1.2 Indium Composition of InGaAs Sub-channels
In order to study the influence of InGaAs sub-channel In composition on the carrier confinement in the InAs-core and the apparent mobility of the entire epitaxial structure, two In0.52Al0.48As/InxGa1-xAs/InAs/InxGa1-xAs/In0.52Al0.48As structures with different InxGa1-xAs sub-channel In composition (70% vs. 30%) were simulated. The purpose of choosing the large difference in In composition in the simulation is to easily visualize and address the effect of sub-channel In composition. The band diagrams, the eigenvalues of sub-bands, and the wavefunctions of these two QW systems are shown in Fig. 4.4.
In Fig. 4.4, the black line denotes the conduction band edge of the QW system with higher In composition (high-In%), and the blue line is for lower In composition (low-In%); the wavefunction in the first sub-band for low-In% and high-In% are in pink and red, respectively. We can see that there is no significant difference in the first sub-band “height” (i.e., 0.19 V for low-In% and 0.18 V for high-In%), since the thickness of every layers are the same.
In Fig. 4.5, the electron distribution of the structures with low-In% (blue) and thick-core (black) are shown. We can see that the low-In% structure has higher peak in the center. Because the InAs-thickness of low-In% and high-In% is the same, the higher peak probability corresponds to the higher apparent mobility. This result suggests that we are able to improve the carrier confinement in the InAs-core and the apparent mobility by using the sub-channel with slightly lower In composition.
However, the In composition cannot be too low; otherwise it will degrade the apparent mobility since some portion of electrons travel through the lower-mobility InGaAs sub-channel.
To sum up, not only the thickness of InAs and InGaAs layers but also the In composition of InGaAs sub-channels should be optimized to achieve good electrostatic control and carrier mobility. Although the buried channel QW-MOSFET prevents the electrons from surface scattering and preserves the high-mobility-essence of InAs channel, buried channel MOSFETs usually has poor subthreshold behaviors due to the increased gate-to-channel distance. Hence the immunity to SCEs is also an important issue to QW-MOSFET.
The improvements in controlling SCEs can be obtained by the scaling of gate-to-channel distance (i.e., gate-to-2DEG distance, more precisely for the case of
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QW-MOSFETs). This goal can be realized by reducing the thickness of InP etch stop layer, InAlAs barrier layer, and InGaAs/InAs/InGaAs composite channel. The epitaxial structures used for the fabrication of QW-MOSFETs with different optimization strategies will be presented in the next section.