國立交通大學
材料科學與工程學系
碩
士
論
文
先進砷化銦量子井金氧半場效電晶體:
元件能隙工程與遲滯效應
Advanced InAs Quantum Well MOSFET:
Device Bandgap Engineering and Hysteresis Effect
學
生 : 林 明 輝
指 導 教 授 : 張 翼 博士
先進砷化銦量子井金氧半場效電晶體:
元件能隙工程與遲滯效應
Advanced InAs Quantum Well MOSFET:
Device Bandgap Engineering and Hysteresis Effect
學 生:林明輝 Student:Ming-Huei Lin
指導教授:張 翼 博士 Advisor:Dr. Edward Yi Chang
國 立 交 通 大 學
材 料 科 學 與 工 程 學 系
碩 士 論 文
A Thesis
Submitted to Department of Materials Science and Engineering College of Engineering
National Chiao Tung University in Partial Fulfillment of the Requirements
for the Degree of Master of Science
in
Materials Science and Engineering December 2013
Hsinchu, Taiwan, Republic of China
i
先進砷化銦量子井金氧半場效電晶體:
元件能隙工程與遲滯效應
學生:林明輝 指導教授:張 翼 博士 國立交通大學 材料科學與工程學系 摘 要 本研究著重於兩個關於砷化銦金氧半場效電晶體的重要議題:砷化銦複合通 道 (InGaAs/ InAs/ InGaAs) 之能隙工程與介面能態所引致的遲滯現象之研究。關於元件能隙工程,吾人首先藉數值模擬以探究元件磊晶結構對載子侷限能 力和遷移率的影響。吾人亦探討幾種用於元件製作及量測的磊晶結構。透過實驗 結果之驗證,吾人發現複合通道厚度及次通道銦含量之極佳化有益於元件電流之 提升與短通道效應之抑制。 關於遲滯效應,吾人探究遲滯現象之物理原因及其對偏壓變化之相依性。吾 人提出一個物理機制以解釋遲滯現象中的閥值電壓偏移,此機制亦可藉實驗結果 驗證。吾人藉著推導出之方程式,研究遲滯現象對不同的偏壓變化之相依性。另 外,吾人亦提出一種萃取電晶體介面能態的方法。此法免如傳統方法般使用 MOS 電容,可評估電晶體閘極堆疊結構之介面性質。 此外,吾人推導幾個關於砷化銦量子井場效電晶體的物理模型,如閥值電壓 及閘極電容,以對元件電性有綜覽性之理解。 關鍵詞: 先進金氧半場效電晶體、砷化銦量子井金氧半場效電晶體、 元件能隙工程、遲滯效應、高介電常數閘極介電質/金屬閘極、 閥值電壓不穩定性
ii
Advanced InAs Quantum Well MOSFET:
Device Bandgap Engineering and Hysteresis Effect
Student: Ming-Huei Lin Advisor: Dr. Edward Yi Chang
Department of Materials Science and Engineering National Chiao Tung University
A
BSTRACTThis thesis focuses on two important issues in InAs quantum well MOSFETs: the bandgap engineering of the InGaAs/InAs/InGaAs composite channel as well as the hysteresis phenomena incurred by the interface states at the high-k/semiconductor interface.
With respect to the device bandgap engineering, the influence of device epitaxial structures on carrier confinement and apparent mobility was firstly investigated by numerical simulations. The epitaxial structures used for the fabrication and characterization of the devices were introduced and reviewed. Through experimental verification, we found that optimized composite channel thickness and sub-channel indium (In) composition are beneficial to the drive current and the suppression of short channel effects.
With respect to the hysteresis effect, we explored the physics origin and the bias dependences of hysteresis phenomena. A mechanism was proposed to explain the threshold voltage shift in hysteresis phenomena, and it was verified by experimental results. Various bias dependences were also studied and emphasized by using the derived equations. In addition, we also proposed a new method to extract the interface state density of the transistor without using MOS capacitor like conventional methods. The proposed method was able to evaluate the interface properties of the gate stack of MOS transistors.
iii
In addition, the physical models for the threshold voltage and gate capacitance of InAs quantum well MOSFETs were developed in order to have a understanding of the electrical behaviors of devices.
Keywords: Advanced MOSFET, InAs Quantum Well MOSFET, Bandgap Engineering, Hysteresis Effect,
iv 誌謝 韶光荏苒,匆匆又過了幾個寒暑。回顧在新竹的日子,平庸如我,無非是憑 著貴人相助和好運氣方能一步步走到這裡的。 首先感謝張翼教授提供充足的實驗設備與研究資源,讓我在半導體元件領域 中得以成長。我由衷感謝郭建億博士、涂永義博士、邱昱盛學長、Luc Quang Ho (陸廣湖)學長、徐慶議學長,特別是夥伴徐偉庭同學在研究與繁雜事務上的討論、 支持、分擔,讓我們得以度過 Panasonic MMIC 計畫和 Quinstar RF Device 計畫。 然後,感謝宋奕佐、湯雲鎮、廖仁廷、王尊民、陳昱禎同學的噓寒問暖,以及其 他百餘位 Compound Semiconductor Device Laboratory 的成員,你們令我的碩士 班生活增色不少。 我亦由衷感謝我的母校──國立交通大學,以及在人生旅途上給我幾個重要 建議的潘扶民教授和郭治群教授。交大在修課及研究上提供足夠的彈性和豐富的 資源,使我在研習主修材料科學的同時亦能有系統地發展志趣:工程物理及固態 電子元件。而兩位師長總在我迷惘時悉心解惑,引導我釐清方向,並且深植興趣。 另外,交大一群以學術作為志業的教授們──謝宗雍教授、汪大暉教授、許維德 教授、王冠生教授,亦深深地影響了我。 最後,感謝我的雙親和摯愛,希望你們能感到欣慰。
v
C
ONTENTS Chinese Abstract English Abstract Acknowledgement Tables Captions Figure Captions List of Symbols Chapter 1: Introduction 1.1 General Background 1.2 Motivations1.3 Organization of this Dissertation
Chapter 2: Literature Review
2.1 InxGa1-xAs/InAs/InxGa1-xAs Composite Channel
and Its Applications in High Electron Mobility Transistors 2.2 InAs Quantum Well MOSFET
Chapter 3: Fabrication and Characterization of Quantum Well MOSFET
3.1 Device Fabrication 3.2 Device Characterization 3.2.1 DC Measurement 3.2.2 RF Measurement
Chapter 4: Device Bandgap Engineering
4.1 Effect of Epitaxial Structure on Carrier Confinement and Mobility 4.1.1 Thickness of InAs-core and InGaAs Sub-channels
4.1.2 Indium Composition of InGaAs Sub-channels 4.2 Experimental Epitaxial Structures
4.3 Result and Discussion 4.4 Summary Page i ii iv vii viii xii 1 1 3 4 8 8 10 16 16 19 19 21 29 29 29 31 32 33 37
vi
Chapter 5: Hysteresis Effect 5.1 Hysteresis Phenomena
5.2 Physical Origin and Proposed Models 5.3 Bias Dependences of Hysteresis Effect 5.3.1 ΔID-VD Dependence
5.3.2 ΔVT-VD Dependence
5.3.3 ΔID-VG Sweep Range Dependence
5.3.4 ΔVT-VG Dependence
5.4 Summary
Chapter 6: Conclusions
References
Appendix: Physically-based Models for Quantum Well MOSFET
A.1 Threshold Voltage Calculation A.2 Gate Capacitance Calculation
A.3 Current-Voltage Characteristics and Subthreshold Behaviors
Curriculum Vitae 65 65 66 68 68 69 69 70 72 84 85 89 89 91 93 100
vii
T
ABLEC
APTIONSChapter 3 Page
Table 3.1 The fabrication process of InAs QW-MOSFET. 23
Chapter 4
Table 4.1 Experimental epitaxial structure 1: regular channel (RC). 38 Table 4.2 Experimental epitaxial structure 2: thin channel (TC). 39 Table 4.3 Experimental epitaxial structure 3: ultra-thin channel (UTC). 40 Table 4.4 Experimental epitaxial structure 4: inverted thin channel (ITC). 41
Table 4.5 Summary of the Hall measurement. 42
Table 4.6 Summary of the DC and RF performance of QW-MOSFETs and HEMT fabricated in this work.
viii
F
IGUREC
APTIONSChapter 1 Page
Fig. 1.1 The electron injection velocity at virtual source in InAs and InGaAs HEMTs/QW-FETs as a function of gate length at supply voltage VDD = 0.5 V. (Figure taken from Alamo et al.
[12])
6
Fig. 1.2 Advanced and emerging device technology. The paradigm shift of transistor technology comes from the combination of new materials and new device architectures.
7
Chapter 2
Fig. 2.1 The epitaxial structure consists of In0.53Ga0.47As/ In0.8Ga0.2As/
InAs/ In0.8Ga0.2As/ In0.53Ga0.47As configuration, yielding
electron mobility of 18,300 cm2V-1s-1. (Figure taken from Nakayama et al. [17])
12
Fig. 2.2 Schematic view of the ultra-thin-channel InAs HEMT structure, which incorporates ultra-thin In0.7Ga0.3As/InAs/In0.7Ga0.3As
composite channel. (Figure taken from Chang et al. [18])
13
Fig. 2.3 1D Poisson-Schrödinger simulations of channel electron density as a function of gate bias. (Figure taken from Kim et al. [28])
14
Fig. 2.4 Schematic view of InAs MOSFET with InAs/In0.53Ga0.47As
channel, regrown S/D, and surface recess etching. (Figure taken from Lee et al. [30])
15
Chapter 3
Fig. 3.1 Process flow of buried-channel gate-last QW-MOSFET. 24 Fig. 3.2 Cross-sectional SEM image of cap-recess EBL (a) resist profile
(b) resist thickness. The resist used in this EBL is ZEP-520A.
25
Fig. 3.3 SEM image of the gate stripe. The gate length of the fabricated QW-MOSFETs in this work is about 250 nm.
26
Fig. 3.4 Schematic device structure of the InAs QW-MOSFETs in this work.
27
Fig. 3.5 Effect of DIBL on the threshold voltage of short channel devices.
ix
Chapter 4 Page
Fig 4.1 The conduction band edge profiles of the QWs with different InAs-core thickness in the composite channels. The simulated QW structures consist of In0.52Al0.48As/In0.7Ga0.3As/InAs/
In0.7Ga0.3As/In0.52Al0.48As with InGaAs/InAs/InGaAs
thicknesses of 5/5/5 and 5/2/5 nm.
44
Fig. 4.2 The wavefunction in first sub-band of the QWs with different InAs-core thickness in the composite channels. The simulated QW structures consist of In0.52Al0.48As/In0.7Ga0.3As/InAs/
In0.7Ga0.3As /In0.52Al0.48As with InGaAs/InAs/InGaAs
thicknesses of 5/5/5 and 5/2/5 nm.
45
Fig. 4.3 The In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As/In0.52Al0.48As
QW systems with two kinds of InGaAs/InAs/InGaAs thicknesses, 3/2/3 and 1/2/1 nm.
46
Fig. 4.4 The conduction band profiles of two QW systems with different indium composition in the InGaAs sub-channels. Two kinds of indium composition, In0.7Ga0.3As and In0.3Ga0.7As, are used to
emphasize the difference in indium composition.
47
Fig. 4.5 The wavefunction in first sub-band of the QWs with different sub-channel indium composition of 70% and 30%.
48
Fig. 4.6 The band diagrams of the RC and TC structures. 49 Fig. 4.7 The band diagrams of the RC and ITC structures. 50 Fig. 4.8 (a) output characteristics and (b) transfer characteristics of RC
QW-MOSFET
51
Fig. 4.9 (a) output characteristics and (b) transfer characteristics of TC QW-MOSFET
52
Fig. 4.10 (a) output characteristics and (b) transfer characteristics of ITC QW-MOSFET
53
Fig. 4.11 (a) output characteristics and (b) transfer characteristics of RC HEMT
54
Fig. 4.12 RC QW-MOSFET vs. RC HEMT (a) ID-VD (b) ID-VG. 55
Fig. 4.12 (cont.)
RC QW-MOSFET vs. RC HEMT (c) gm-VG (d) IG-VG. 56
Fig. 4.13 TC QW-MOSFET vs. RC QW-MOSFET (a) ID-VD (b) ID-VG. 57
Fig. 4.13 (cont.)
TC QW-MOSFET vs. RC QW-MOSFET (c) gm-VG (d)
semi-log IG-VG.
58
x
Page Fig. 4.14
(cont.)
ITC QW-MOSFET vs. RC QW-MOSFET (c) gm-VG (d)
semi-log IG-VG.
60
Fig. 4.15 The equivalent circuits near the source/drain side in term of resistance for normal-type and inverted-type QW-MOSFETs.
61
Fig. 4.16 The equivalent circuits of composite channel QW-MOSFETs’ gate stack in term of capacitance, where the subscripts ox, it, ins, Q, centroid stand for the capacitance component of gate dielectric, interface states, insulator layer (i.e., InP and InAlAs), quantum capacitance, and centroid capacitance.
62
Fig. 4.17 Microwave characteristics of (a) RC QW-MOSFET (b) ITC QW-MOSFET.
63
Fig. 4.18 Benchmarking of the InAs/InGaAs MOSFETs and HEMTs. The ITC QWMOSFET is benchmarked to the similar works using InAs and high-indium InGaAs channels. The benchmarked devices are done by [29], [28], [25], [18], and [13] respectively.
64
Chapter 5
Fig. 5.1 The hysteresis phenomena in ID-VG transfer characteristics: (a)
linear scale (b) semi-log scale.
73
Fig. 5.2 The gate leakage current of the forward-/reverse-sweeps. 74 Fig. 5.3 The mechanism of how VG modulates the amount of charged
acceptor-like interface states. (a) VG > 0 (b) VG = 0 (c) VG < 0.
75
Fig. 5.4 ΔID -VD Dependence: the ΔID of various drain bias conditions
as a function of VG, where the ΔID is defined as:
ΔID = ID (forward) - ID (reverse) in the transfer characteristics.
76
Fig. 5.5 The maximum |ΔID| as a function of biased VD in the transfer
curves. The adjusted R2 of the linear fitting line is 0.98.
77
Fig. 5.6 The ΔVT as a function of the biased VD, where the VT in the
forward and reverse-sweeps is simply extracted by the linear extrapolation of ID-VG transfer curves.
78
Fig. 5.7 ΔID - VG Sweep Range Dependence: (a) the ID-VG curves with
different sweep range (b) the maximum ΔID as a function of VG
sweep range, which is defined as: VG sweep range = VG,max - VG0.
79
Fig. 5.8 The ΔVT-VG dependence, where the ΔVT is extracted by the
proposed method shown in Section 5.3.4.
xi
Page Fig. 5.9 The quantity of charged interface states of two VG biases, VG1
and VG2, as a function of energy, where the EF1 and EF2
correspond to the Fermi level at the gate bias of VG1 and VG2,
respectively. The difference in Nit between two gate biases is
denoted as δNit.
81
Fig. 5.10 The ΔVT vs. VG curves of various biased VD. 82
Fig. 5.11 The slope of the fitting line as a function of biased VD. 83
Appendix
Fig. A.1 Schematic band diagram and the charge density vs. position of normal type InAs composite channel QW-MOSFET at flat band condition.
96
Fig. A.2 Schematic band diagram and the charge density vs. position of inverted type InAs composite channel QW-MOSFET at flat band condition.
97
Fig. A.3 Equivalent circuit of the gate capacitance of (a) surface channel MOSFET (b) InAs composite channel QW-MOSFET.
98
xii
L
IST OFS
YMBOLSC capacitance/area in MOS (F/cm2) CG gate capacitance/area (F/cm2)
COX gate oxide capacitance/ area (F/cm2)
Cd depletion capacitance/ area (F/cm2)
Cins insulator capacitance/ area (F/cm2)
Cit, interface-state capacitance/ area (F/cm2)
Ccentroid centroid capacitance/ area (F/cm2)
CQ quantum capacitance/ area (F/cm2)
D electrical flux density (C/m2) Dit interface-state density (cm-2eV-1)
D, G, S drain, gate, source of an FET
Ec, Ev conduction band, valence band edge (J, eV)
EF equilibrium Fermi level (J, eV)
E0 charge neutral level (J, eV)
f(E) Fermi-Dirac distribution function gm mutual transconductance in an FET (S)
ID channel current in an FET, direction from drain to
source (A)
IG gate current in an FET (A)
k Boltzmann constant (J/K, eV/K)
k wave vector (cm-1)
Lg gate length in an FET (m)
mn*, mp* effective mass for electrons, holes (kg)
m0 rest mass of electrons (kg)
Nit effective (net) charge density/area (/cm2)
q magnitude of the electronic charge (C) Q+, Q- total positive, negative charge (C)
Qf oxide fixed charge/area (C/cm2)
Qit interface trap charge/area (C/cm2)
Qm mobile ionic charge/area (C/cm2)
R resistance (ohm)
SS subthreshold swing/slope (mV/decade)
T temperature (K)
V voltage (V)
VD, VG voltage from drain to source, gate to source in an FET
xiii VT threshold voltage (V)
Vth thermal voltage (V)
Wg gate width in an FET (m)
1
Chapter 1
Introduction
1.1 General Background
Semiconductor quantum heterostructures have drawn a great deal of attention of scientists and engineers in the fields of solid-state physics, materials science, and electronics. Engineered heterostructures not only incorporate new transport properties and device operation principles into the emerging transistor technologies, but also pave the way for future low-power and high-performance complementary metal-oxide-semiconductor (CMOS) technology through this approach: III-V MOSFET.
Driven by the Moore’s law, Si MOSFETs have dominated the CMOS technology for over three decades with the advance of lithography technology. However, scaling of deep submicron MOS transistors encountered difficulties in device engineering, including short channel effects (SCEs) [1], degraded mobility [2], random dopant fluctuation (RDF)[3], and random telegraph noise (RTN) [4]. Improved electrostatic control had been realized though device body engineering and new device architectures, such as ultra-shallow junction [5], retrograde doping [6], raised source-drain [7], FinFET [8] and ultra-thin body silicon-on insulator (UTB-SOI) [9]. Moreover, partially/fully depleted devices [10] with lightly-doped/no-dopant channel are expected to be a feasible solution to get rid of the RDF. Regarding the mobility degradation, strained Si technology has been demonstrated in industrial products. However, stress engineering approaches its limit since the injection velocity of Si is insufficient to meet the requirements of sub-10 nm MOS transistors. Advanced MOSFET technology utilizing III-Vs and/or Ge channels emerges as the promising candidates for nano-scale low-power and high-performance MOSFETs. The strength of III-V-based channel comes not only from their superior transport properties that strained-Si cannot achieve, but also from the art of device bandgap engineering.
III-V materials’ low effective mass and hence high carrier velocity enable the transistors to perform high drain current (ID), impressive transconductance (gm), and
short gate delay at low supply voltage (VDD). Scaling VDD without the expense of
device performance is essential to the present and future CMOS technology. The VDD
2
power consumption of a MOSFET is given by P = 0.5 Ci × VDD2, where Ci is the gate
capacitance. Lower VDD represents less power consumption and prevents the devices
from some reliability issues. There are two momentums that accelerate the pursuing of high-mobility channel materials. The first one is: the ballistic transport and velocity saturation phenomena in nano-scale MOSFETs make the ID and gm depend on carrier
velocity instead of gate length (Lg) as the Lg below 100 nm [1]. The second one is: the
surface-channel Si MOSFETs suffer from severe surface scattering at oxide/semiconductor interface during device scaling, due to large transverse electrical field. In the perspective of the improvement in mobility and injection velocity, InxGa1-xAs with In composition of 53% and above as well as InAs were taken into
consideration by the International Roadmap Committee [11]. Even though low effective mass leads to high carrier velocity, but its drawback — low density of state (DOS) has to be taken into considerations. Low DOS leads to the lower sheet electron concentration in channel, so the transistor requires more gate overdrive (VG - VT) to
sustain available carriers. Fig. 1.1 shows the electron injection velocity at virtual source in InAs and InGaAs quantum well field effect transistors (QW-FETs) as a function of Lg at supply voltage VDD = 0.5V [12]. It is apparent that III-V-based
materials are suitable candidates for n-channel MOSFETs.
In addition to high carrier velocity, the flexibility of bandgap engineering has been proven in various heterostructure transistors, such as high electron mobility transistor (HEMT) (i.e., QW-FET) [13], III-V FinFET [14], III-V UTB MOSFET [15] and III-V tunneling FET (TFET) [16]. The essence of bandgap engineering is, according to the specific application, one can design and adjust the materials, composition, and thickness of each layer in the heterostructure, so as to optimize the required device performance. Take HEMT as an example, composite channel [17] has been used to enhance the carrier mobility and the carrier confinement, leading to improved gm as well as current gain cut-off frequency (fT). Furthermore, the HEMT
with thin composite channel [18] have demonstrated record fT of ~710 GHz by
National Chiao Tung University, Taiwan in 2013. Another example is the vertical heterostructure TFET [19] proposed and fabricated by Intel Corporation in 2011. The inserted thin In0.7Ga0.3As layer served as a smaller tunneling barrier, which drastically
increased the drive current. These two examples illustrated the physics and technology of the bandgap engineering in III-V FETs.
3
Indeed, III-V MOSFET requires both pertinent gate dielectrics and good gate-dielectric/semiconductor interface. Unlike Si, III-Vs are lack of high-quality native oxide, which makes Si as the mainstream ULSI technology. In recent years, atomic layer deposition (ALD) realizes the deposition of high-k dielectrics on III-V materials along with the capability of ultra-thin interfacial layer to reduce interface state density (Dit) and gate leakage. Associated with the study of interfacial layer,
various surface treatments are also proposed to passivate the interface states. Even though the researches on passivation techniques are under development, ALD technology has opened up a frontier field in III-V FET researches.
Regarding the device engineering, a controversial issue lies in the device architecture of III-V MOSFET: surface channel or buried channel. Surface channel devices provide better gate modulation through the reduced gate-to-channel distance and higher gate capacitance, but III-V’s relatively higher Dit will make the device
suffer from scattering and degraded subthreshold behaviors. In contrast, buried channel ensures better high-k/semiconductor interface by using appropriate gate stack (e.g., Al2O3/InP and TaSiOx/InP), in which drastically reduced Dit preserves the high
mobility essence of III-V materials. However, the corresponding side effect is the increased gate-to-channel distance, which makes the buried channel device prone to the short channel effects. In short, the choosing of surface channel or buried channel is a trade-off between gate modulation and mobility.
To sum up, the combination of III-V nMOS and Ge pMOS on Si platform is the ultimate scenario in the foreseeable future, if the following difficulties can be overcomed: 1) optimized logic performance through device bandgap engineering, 2) good high-k dielectric/semiconductor interface with Dit in the order of 1011 cm-2eV-1,
3) low resistive, refractory, and gold-free source/drain (S/D) contact, and 4) III-Vs/Ge on Si epitaxy technology, which is the corner stone of heterogeneous integration.
1.2 Motivations
Although many works had used InxGa1-xAs/InAs/InxGa1-xAs composite channel
structure in HEMTs/QW-FETs and QW-MOSFETs, there is no complete research on the bandgap engineering of InAs composite channels. Based on the flexibility of composite channel, device performance can be optimized for different applications. In
4
this work, the logic characteristics of composite channel QW-MOSFETs are emphasized because of the emerging of III-V MOS transistors in sub-10 nm regime. Furthermore, InAs composite channel QW-MOSFETs requires appropriate physical models to describe the fundamental electrical properties, such as threshold voltage (VT) and gate capacitance (CG). The derived equations help us to look into the basic
electrical behaviors, and to have an in-depth understanding on hysteresis phenomena.
1.3 Thesis Outline
The objective of this dissertation is two-fold: 1) to deliver a comprehensive study on the bandgap engineering of composite channel for future low-power and high-performance logic application and 2) to examine the physical origin and bias dependence of the hysteresis effect based on the derived models.
In Chapter 2, the literature review starts from the InAs composite channel and its applications in HEMTs. Then the disadvantages of HEMT are discussed. Finally, the InAs FETs with insulated gate are introduced and reviewed.
In Chapter 3, the process and characterization of InAs composite channel QW-MOSFETs are introduced. The metrology methods for DC and RF characterization are also briefly described. This chapter serves as the research methodology of this work.
In Chapter 4, the investigation of bandgap engineering of InAs composite channel is conducted through both theoretical and experimental approaches. In the beginning, the influence of epitaxial structures on device performance is examined by numerical device simulations. The experimental studies were also performed. InAs QW-MOSFETs with three kinds of epitaxial structures were fabricated and characterized. It was found that the devices with inverted thin channel structure exhibit the best logic and microwave characteristics under low-power operation conditions.
In Chapter 5, the mechanism of the hysteresis phenomena and the bias dependence are explored. The trapping/de-trapping of the acceptor-like interface states at high-k/semiconductor interface has proven to be directly related to the hysteresis effect through electrical analysis. Moreover, a new extraction method is proposed to evaluate the Dit of MOS transistors.
5
In Chapter 6, the conclusions of this dissertation are drawn.
In the Appendix, analytical models developed to describe the threshold voltage (VT) and gate capacitance (CG) are presented. Based on the VT and CG models, the
current-voltage (I-V) characteristics are then derived in an analog fashion to the well-developed MOSFET equations. The derived models provide a fundamental understanding on the electrical behaviors of devices. Moreover, the VT model can also
6
Fig. 1.1 The electron injection velocity at virtual source in InAs and InGaAs
HEMTs/QW-FETs as a function of gate length at supply voltage VDD = 0.5 V.
7
Fig. 1.2 Advanced and emerging device technology. The paradigm shift of transistor
technology comes from the combination of new materials and new device architectures.
8
Chapter 2
Literature Review
2.1 InxGa1-xAs/InAs/InxGa1-xAs Composite Channel and Its Applications in High
Electron Mobility Transistors
Applying InAs channel to FETs is not a new technology. InAs FETs are often accompanied with composite channel, in which InAs channel is sandwiched by upper and lower cladding InGaAs sub-channels. The main purposes include: 1) the accommodation of lattice mismatch; 2) lowered interface free energy, which yields smoother interface and prevents the formation of defects such as misfit dislocations; 3) better carrier confinement, which is obtained through the InxGa1-xAs/InAs/InxGa1-xAs
heterostructure.
Due to the excellent transport properties and enhanced carrier confinement of InAs composite channel, Nakayama et al. [17] demonstrated extraordinary electron mobility of 18,300 cm2V-1s-1 by using 1-nm In0.53Ga0.47As/ 2-nm In0.8Ga0.2As/ 4-nm
InAs/ 4-nm In0.8Ga0.2As/ 9-nm In0.53Ga0.47As configuration, as shown in Fig. 2.1. The
inserted In0.8Ga0.2As layer between InAs and In0.53Ga0.47As reduces the interface free
energy since the surface energy for In0.53Ga0.47As/InAs is higher than
In0.8Ga0.2As/InAs. The streak RHEED pattern confirms the smoother interface.
With respect to the design of InAs composite channel, the key parameters that determine device performance can be categorized into two subjects: 1) the thickness of the InAs-core and InGaAs sub-channels; 2) the In composition of the cladding InGaAs sub-channels.
Regarding the thickness optimization of the upper sub-channel, Akazaki et al. [20] optimized the thickness of the upper cladding In0.53Ga0.47As and the InAs-core at
fixed total composite channel thickness of 30 nm. An optimized configuration was achieved by using 2.5-nm In0.53Ga0.47As/ 4-nm InAs/ 23.5-nm In0.53Ga0.47As
composite channel, which leads to the electron mobility of 12,800 cm2V-1s-1. The HEMT using this configuration with 0.6×150 μm2 gate exhibits fT of 58.1 GHz.
9
made comparisons of In0.53Ga0.47As/InAs/In0.53Ga0.47As with two kinds of sub-channel
configurations at fixed upper sub-channel thickness: tInGaAs(upper) = tInGaAs(lower) and
tInGaAs(upper) < tInGaAs(lower), where the tInGaAs(upper) and tInGaAs(lower) stand for the
upper and lower sub-channels, respectively. The electron mobility for the structure with thinner lower-clad is 14,800 cm2V-1s-1, while for the thicker one is 15,400 cm2V-1s-1. The HEMT with thicker lower-clad exhibits better DC and RF performance. However, the device with thinner lower-clad has less impact ionization phenomena and suppressed SCEs.
Regarding the optimization of the In composition of lower sub-channel, Xu et al. [22] compared the In composition of the lower cladding layer at fixed In0.53Ga0.47As/InAs/InxGa1-xAs thickness of 2/3/7 nm, in which the compared In
composition are 0.3 and 0.7. The performance of the device with In0.3Ga0.7As lower
sub-channel was better than the In0.7Ga0.3As one. The performance improvement was
attributed to the improved carrier confinement caused by the higher potential of In0.3Ga0.7As layer. Moreover, the tensile In0.3Ga0.7As layer is believed to compensate
the strong compressive strain in the InAs layer, resulting in a better epitaxial quality of InAs layer.
The optimized composite channel has demonstrated impressive microwave characteristics in HEMTs. In Kim and Alamo’s work [23], the heterostructure with 2-nm In0.53Ga0.47As/ 5-nm InAs/ 3-nm In0.53Ga0.47As has the electron mobility of
13,200 cm2V-1s-1; and their HEMT exhibits the fT of 491 GHz. On the other hand,
Fatah et al. [24] also used the same composite channel configuration to achieve the fT
of 615 GHz. Furthermore, Chang et al. [18] demonstrated the record fT of 710 GHz by
incorporating 1-nm In0.7Ga0.3As/ 2-nm InAs/ 1-nm In0.7Ga0.3As ultra-thin composite
channel and low-resistive In0.65Ga0.35As/ In0.53Ga0.47As /In0.52Al0.48As multi-cap, as
shown in Fig. 2.2.
Even though those researches on the composite channel in HEMTs demonstrated good result on the RF performance, yet they paid less attention on the logic characteristics such as subthreshold swing (SS) and drain-induced barrier lowering (DIBL). Moreover, a trade-off between device performance and gate leakage exists in the Schottky-gated InAs HEMTs: although device with thin-barrier-layer structure are able to improve both logic and RF performance, the gate leakage is relatively high. This trade-off comes from the Schottky gate, since the gate leakage
10
for Schottky-gated devices is several orders higher than the devices with insulated gate (i.e., Insulated Gate FET, IGFET). Therefore, the InAs transistors with insulated gate are preferred and had been extensively studied in recent years, in order to evaluate its performance and feasibility in ULSI applications.
2.2 InAs Quantum Well MOSFET
Above-mentioned works are HEMTs, which employ Schottky gate instead of the insulated gate. InAs FETs with high-k dielectric gate stack is essential to low-power CMOS, since it reduces the static power consumption of the transistors and the entire ICs. As a result, InAs IGFET with engineered quantum heterostructure has attracted much attention in several device-related journals and conferences such as International Electron Device Meeting (IEDM) and Symposium on VLSI Technology (VLSIT).
The primary concern on the InAs MOS transistors is the high-k/semiconductor heterointerface. Intel Corporation [25] reported two gate stacks with good interface quality: Al2O3/InP and TaSiOx/InP. Both of them represent low frequency dispersion
(7%/decade) compared to conventional Al2O3/In0.52Al0.48As (27%/decade) gate stack.
This result indicates that InP is an ideal material for the high-k/III-Vs integration. Moreover, this research may also terminate the debate among surface channel and buried channel. Although surface channel device like [26] are able to achieve high ID
and gm due to its higher CG, the poor subthreshold behaviors and frequency dispersion
due to high Dit is unacceptable for digital applications. Furthermore, the InP layer can
also be used as the etch stop layer during the selective removal of heavily-doped cap layer, giving rise to better process control and VT uniformity [27]. Therefore, using
high-k/InP as the gate stack is beneficial to ULSI applications.
Finally, three impressive researches on InAs MOS transistors will be reviewed in the following paragraphs.
11 SEMATECH VLSIT 2012
Kim et al. [28] demonstrated the InAs QW-MOSFET with thin InP layer, low Dit
Al2O3/InP gate stack, and optimized modulation doping concentration. The device
exhibited peak gm of 1730 μS/μm, fT of 245 GHz, and SS of 105 mV/decade at VD =
0.5 V. The optimized δ-doping concentration of 1×1012 cm-2 leads to high gm and good
SS since higher concentration limits the charge modulation (Fig. 2.3). The immunity to SCEs is also attributed to the gate stack with minimum Dit of 4×1012 cm-2eV-1.
MIT IEDM 2012
The InAs QW-MOSFETs with Lg = 30 nm and Lg = 22 nm [29] were realized
through the CMOS-compatible and self-aligned process, which gives rise to the scaled gate-to-contact distance of 20-30 nm. The device employed the 3-nm In0.7Ga0.3As/
2-nm InAs/ 5-nm In0.7Ga0.3As composite channel, low-resistive Mo contact, and the
2-nm HfO2 gate dielectric with the EOT less than 1nm. The 30-nm and 22-nm devices
exhibit peak gm of 1420 μS/μm and 1050μS/μm, respectively. The SS of 30-nm device
is 114 mV/decade at VD = 0.5 V.
UCSB VLSIT 2013
Lee et al. [30] reported the InAs QW-MOSFET with record extrinsic peak gm of
2450 μS/μm and excellent ID of 1950 μA/μm at VD = 0.5 V. The device consists of
regrown S/D, digital etching process, inverted-modulation-doped 5-nm InAs/ 3-nm In0.53Ga0.47As composite channel, and substitution gate process. The device
architecture is shown in Fig. 2.4. We can see that the 0.5-nm interfacial layer/ 3.6-nm HfO2/Ni/Au gate scheme is directly stacked on the InAs composite channel instead of
InP layer. As a result, the SS for the 40-nm device is about 400 mV/decade. The epitaxial S/D gives rise to the reduction of parasitic resistance, achieving low on-resistance Ron of 214 Ω-μm. The digital etching was conducted to remove the
damaged semiconductor surface, which is introduced in the process of epitaxial S/D. As a whole, although this device architecture provided very high ID and gm, the poor
subthreshold behaviors and low ION/IOFF still prevents this architecture from CMOS
12
Fig. 2.1 The epitaxial structure consists of In0.53Ga0.47As/ In0.8Ga0.2As/ InAs/
In0.8Ga0.2As/ In0.53Ga0.47As configuration, yielding electron mobility of 18,300
13
Fig. 2.2 Schematic view of the ultra-thin-channel InAs HEMT structure, which
incorporates ultra-thin In0.7Ga0.3As/InAs/In0.7Ga0.3As composite channel. (Figure
14
Fig. 2.3 1D Poisson-Schrödinger simulations of channel electron density as a
15
Fig. 2.4 Schematic view of InAs MOSFET with InAs/In0.53Ga0.47As channel,
16
Chapter 3
Fabrication and Characterization of Quantum Well MOSFET
3.1 Device Fabrication
The process flow for the InAs QW-MOSFETs of this work is shown in Fig. 3.1, and the details of the fabrication steps are summarized in Table 3.1. There are 9 major steps:
1) Device isolation,
2) Formation of the alignment marks for e-beam lithography (EBL), 3) Definition of cap-recess region by EBL,
4) Removal of the cap layer in the EBL defined area, 5) Deposition of high-k gate dielectrics by ALD, 6) Definition of contacts and the removal of dielectrics, 7) Metallization of S/D contacts and pads,
8) Gate definition by EBL, and 9) Gate metallization.
The details and purpose of each step are elaborated individually as the follows. The last paragraph evaluates the pros and cons of this gate-last process, and summarizes the critical steps and their effect on device performance.
Device isolation was performed using phosphoric-based mixture and hydrochloric-based solution; the former selectively etches InGaAs and InAlAs layers, and the latter selectively removes InP etch stop layer. The area outside the defined region was etched down to the buffer layer in order to achieve good electrical isolation. Finally, the etch depth was measured by surface profiler after the removal of photo resist (PR). Through mesa formation, the electrically conductive slice, called “active” region, is isolated from the contact pads. Isolation not only restricts the current flows within the active region, but also reduces parasitic resistance and capacitance. The parasitic resistance comes from the current flow between source and drain that does not pass under the gate, degrading device RF performance. Minimum parasitic capacitance was achieved by placing gate stripe on the semi-insulating
17
substrate, since the capacitance is associated with the doping concentration in depletion region underneath the gate stripe.
The e-beam alignment mark was formed by lift-off process, in which the image reversal technique realized the reverse-tapered PR (i.e., AZ 5214-E) profile that enabled the lift-off process. This metallization step only served the purpose of EBL alignment and the process control monitoring (PCM) pattern for the digital etching in the cap-recess process. The design consideration of separating e-beam alignment marks and contact pads in two different steps is that: high post-deposition-annealing (PDA) temperature (400~500℃) after high-k deposition degrades ohmic contacts if S/D contacts are formed before the dielectric deposition. Therefore the thermally stable metal scheme, Ti/Au, is employed to prevent metallurgical reaction that might deform the alignment mark and hence degrade the accuracy of EBL.
The EBL of cap-recess region was performed by using typical e-beam resist (ZEP-520A) and the EBL system (JEOL JBX-6000FS). The cross-section of cap recess EBL was shown in Fig. 3.2. Length of the opened area is about 150 nm with resist thickness about 280 nm. Thinner resist profile is advantageous to the scaling of cap-recessed region, which is critical to improve the device performance, since shorter cap-recessed length reduces the parasitic resistance.
Cap-recess was conducted by the selective etching of the InGaAs cap layer over the InP etch stop layer. Citric-based and succinic-based mixtures were used for the selective etching of the native oxide on the surface and the InGaAs cap layer, respectively. We monitored the current of PCM pattern during wet etching, not only to make sure the cap layer within the opened area was removed clearly, but also to optimize the lateral etching, which determines the parasitic resistance and capacitance. The optimized digital recess condition led to a clear removal of cap layer without long lateral etching.
High-k gate dielectric was deposited by ALD (Cambridge NanoTech Fiji-202 DCS). In this work, 5-nm Al2O3 were used as gate dielectric. Before Al2O3 deposition,
the sample was passivated by in-situ trimethylaluminum (TMA) pre-treatment, which has been proven to be able to reduce Dit [31]. In fact, other thinner high-k materials
with higher dielectric constant such as HfO2 and La2O3 can also be employed in order
to decrease effective oxide thickness (EOT), which is helpful to boost device performance including ID, gm, on-off current ratio (ION/IOFF), and SS. However,
18
because this research focuses on device bandgap engineering, other high-k stacks and the surface treatments were not used for convenience.
After the photolithography for contacts and pads, the dielectric within the opened area was removed by dilute hydrogen fluoride (DHF) solution, and a treatment using dilute hydrochloric acid was performed before ohmic metallization. The contacts and pads were formed by alloyed Au/Ge/Ni/Au stack. The purposes of this conventional ohmic metal scheme are two-fold: 1) Au/Ge alloy improves adhesion between semiconductor and metal; 2) Ge diffuses into the InGaAs cap layer during the annealing after metallization, and drastically increase the doping concentration few nm underneath the metal. After the lift-off process, excellent specific contact resistance of 1.27×10-7 Ω-cm2 was extracted by transmission line measurement (TLM). Although the extracted value is below the measurement limit of TLM, the result still suggested a good ohmic contact.
Finally, gate EBL and the corresponding metallization were performed. The gate width (Wg) and Lg of the InAs QW-MOSFETs are 40 μm and 250 nm, respectively.
The cross-sectional SEM image of the gate stripe is shown in Fig. 3.3. The gate metal scheme used in this work was Ti/Au. After e-beam evaporation, typical e-beam resist stripper, ZDMAC, was used in this lift-off process. The device structure is shown in Fig 3.4.
Finally, the device was passivated by the SiNx grown by plasma enhanced
chemical vapor deposition (PECVD). The via was formed after device passivation. The key process steps can be divided into several categories according to their effects on device: 1) cap recess EBL, cap etching, and source-drain spacing; 2) surface treatment and PDA condition; 3) gate dielectric materials and thickness; 4) gate EBL; 5) gate stack (which includes the materials for gate metal and gate oxide). They determine parasitic resistance, Dit, EOT, Lg, and VT respectively.
In a nutshell, the devices employed a “gate-last” process. However, as we know, the devices undergone “gate-first” process have better metal-gate/high-k and high-k/semiconductor interfaces. This is attributed to the fact that the interfaces in gate-first process are kept way from the chemicals and deleterious processing environments that introduce interface states during device fabrication steps. However, because we only have contact aligner to define the S/D contacts and pads, if the gate is formed before contacts, the gate might break during the photolithography using
19
contact aligner. Therefore, we have to choose gate-last process, even though its relatively higher Dit may degrade the subthreshold behaviors.
3.2 Device Characterization [1] 3.2.1 DC Measurement
The I-V behaviors of the transistors were characterized in terms of the output and the transfer characteristics. The figures of merit (FOMs) representing device logic performance can be extracted and evaluated by DC measurement. The principles and operational definitions of the extracted FOMs are briefly described in the following paragraphs.
Threshold Voltage (VT)
The VT is a fundamental parameter for MOSFET modeling and characterization.
This parameter, which stands for the onset of significant drain current flow, has been given several operational definitions. Most of the proposed procedures are based on the measurement of the drain current versus gate voltage (ID-VG) characteristics of the
transistor. Typical extraction methods bias the transistor at low drain voltage, so that the device operates in the linear region.
There are three commonly used methods that bias device in the linear region: 1) constant current (CC) method, which defines VT as the gate voltage corresponding to
the constant drain current, ID of 1mA/mm; 2) transconductance linear extrapolation
(TLE) method, which defines VT as the gate voltage axis intercept of the linear
extrapolation of the gm-VG curve at its maximum first derivative point; 3)
extrapolation in the linear region (ELR) method, which defines VT as the gate voltage
axis intercept of the linear extrapolation of the ID–VG curves at its maximum
transconductance point.
It is obvious that CC method determines VT in a simple manner, but the CC
method has the severe disadvantage of being totally dependent of the arbitrarily chosen value of the ID level. On the other hand, the assumptions behind TLE method
are that: 1) in weak inversion region, gm increases exponentially with VG; 2) in the
transition region between weak and strong inversion, gm increases linearly with VG; 3)
20
mobility. In this work, we choose the most popular one - ELR method to extract device VT.
Subthreshold Swing (SS)
The SS is the FOM reflects the electrostatic control of the transistor. The SS is defined as: ) 1 . 3 ( log 1 G D V d I d SS
The SS of surface channel MOSFETs can be expressed as:
) 2 . 3 ( 1 ) 10 (ln OX d it C C C q kT SS
The theoretical limitation of SS is about 60 mV/decade, which is also called the thermionic limit of MOSFETs. However, for nowadays nano-scale logic MOSFETs, the SS increases with the scaled gate length due to SCEs. Moreover, the SS degradation is also attributed to the interface states between gate oxide and semiconductor. The introduction of high-k gate stack makes the SS degradation more significant, since the interface is poorer than Si/SiO2 system. This issue is even worse
for III-V MOSFETs with high-k gate stack, because of the large amount of interface states on the III-V surface. Note that the SS of QW-MOSFETs is different from surface channel MOSFETs. The equation and the details of derivation are presented in the Appendix (A.3).
Drain-induced Barrier Lowering (DIBL)
The DIBL is also a parameter monitoring the short channel effects. The DIBL is defined as: ) 3 . 3 ( D T V d V d DIBL
The DIBL leads to a source-drain leakage and the loss of gate control. The phenomenon can be understood from Fig. 3.5, in which the surface potential of long channel and short channel MOSFETs are plotted. As the VD increases, the conduction
band edge near the drain side is pulled down. For long channel devices, this phenomenon does not have strong influence on the leakage, since the pulled-down
21
region does not reach the source side. However, for short channel devices, the surface potential near the source side is pulled down by the VD, resulting in a significant drain
leakage and a lowering in device VT.
In practice, we prefer to use two drain biases, 0.5 V and 50 mV, to extract the value of DIBL, since the devices studied in this work is for low-power logic application, the VD is expected to be lower than 1 V.
3.2.2 RF Measurement
The microwave characteristics are usually characterized by using vector network analyzer (VNA) to obtain the scattering parameters. Typical FOMs, such as fT and
maximum oscillation frequency (fmax), can be extracted by interpreting the scattering
parameters. The principles and operational definitions of scattering parameters and the extracted FOMs are introduced as the follows.
Two-port Scattering Parameters
The scattering parameters, or called S-parameters, are the fundamental to microwave characteristics of a linear network. It is difficult to measure Z-, Y-, or H-parameters since the device are unstable at open/short conditions. S-parameters measurement uses the matched load (50Ω) instead of open/short circuit conditions, so it is easier to be obtained at high operation frequency. Therefore, the FOMs of device RF characteristics can be extracted by S-parameters, such as gain, return loss, voltage standing wave ratio (VSWR), and reflection coefficient and amplifier stability.
The relationship between the reflected, incident power waves and the S-parameter matrix is expressed as:
) 4 . 3 ( 2 1 22 21 12 11 2 1 a a s s s s b b
The electrical field of the signal going into and leaving the ports are denoted as a and b, respectively. And the subscripts, 1 and 2, represents the input port and the output port respectively.
Therefore, s11 is the input voltage reflection coefficient, defined as b1/a1 at a2 = 0;
s12 is the reverse voltage gain, defined as b1/a2 at a1 = 0; s21 is the forward voltage
22
defined as b2/a2 at a1 = 0.Therefore, the properties of two-port network are then given
by:
scalar logarithmic gain, g = 20log10|s21| dB
input return loss, RLin = |20log10|s11|| dB
output return loss, RLout= |20log10|s22|| dB
input VSWR = (1+|s11|)/(1-|s11|)
output VSWR = (1+|s22|)/(1-|s22|)
Current gain cut-off frequency (fT)
The fT is a more appropriate FOM for digital circuits, in which speed is the
primary concern. The operational definition of fT is the frequency corresponding to
the current gain (h21) becomes unity (0 dB), where h21 is given by:
For surface channel MOSFET, the fT can be approximated as:
) 6 . 3 ( ) ' ' ( 2 G par m T C C g f
where C’par is the total input parasitic capacitance.
Maximum oscillation frequency (fmax)
The fmax is more relevant for analog applications, since it is defined as the
frequency corresponding to the power gain/ unilateral gain becomes unity (0 dB). The unilateral gain, U, is given by
(3.7) ) | | 1 )( | | 1 ( | | 2 22 2 11 2 21 s s s U
For surface channel MOSFET, the fmax can be approximated as:
) 8 . 3 ( ' 8 max GD G T C R f f (3.5) ) 1 )( 1 ( 2 21 12 22 11 21 21 s s s s s h
23
Table 3.1 The fabrication process of InAs QW-MOSFET.
Modules Steps Remarks
1. Device isolation Photolithography
Mesa isolation InGaAs/InAlAs etching H3PO4: H2O2: H2O =1:1:80
InP etching
HCl: H3PO4: H2O = 1:1:1
PR strip
AEI Etch depth: 220 nm (to buffer layer) 2. EBL alignment
mark formation
Photolithography
Metallization Native oxide etching HCl: H2O =1:10
Ti/Au = 50/150 nm
250℃ annealing for 30 sec 3. Cap-recess E-beam
lithography
Resist: ZEP-520A
Cap etching Critic acid-based solution Succinic acid-based solution
PR strip ZDMAC
4. ALD high-k gate dielectric Pre-deposition TMA treatment ALD gate dielectric 5nm Al2O3 5. S/D contact formation Photolithography Dielectric etching HF: H2O =1:100 Metallization Au/Ge/Ni/Au=20/40/140/250 nm Lift-off process
6. Gate formation E-beam lithography Resist: PMGI/ZEP-520A Metallization Ti/Au = 50/250 nm Lift-off process 7. Passivation Device passivation PECVD 100-nm Si3N4 Photolithography Via etching PR strip
24
25
Fig. 3.2 Cross-sectional SEM image of cap-recess EBL (a) resist profile (b) resist
thickness. The resist used in this EBL is ZEP-520A.
(a)
26
Fig. 3.3 SEM image of the gate stripe. The gate length of the fabricated
27
28
29
Chapter 4
Device Bandgap Engineering
In order to investigate the bandgap engineering of composite channel, we used both theoretical and experimental approaches. For the theoretical analysis, a technology computer aided design (TCAD) tool, nextnano, was used to capture and visualize the theoretical analysis. For the experimental study, three kinds of QW-MOSFETs with different epitaxial structures were fabricated and characterized. Through DC and RF measurements, the experimental analysis was also conducted in order to examine the effect of epitaxial structure on the performance of InAs QW-MOSFETs.
4.1 Effect of Epitaxial Structure on Carrier Confinement and Mobility 4.1.1 Thickness of InAs-core and InGaAs Sub-channels
In order to study the influence of InAs-core thickness on the carrier confinement in the InAs-core and the apparent mobility of the entire epitaxial structure, two In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As/In0.52Al0.48As structures with different
composite channel thickness (i.e., InGaAs/InAs/InGaAs of 5/5/5 and 5/2/5 nm) were simulated. The band diagrams, the eigenvalues of sub-bands, and the wavefunction (i.e., |φ|2
) in each sub-band of these two quantum well (QW) systems were solved by Poisson-Schrödinger solver. The numerical results are shown in Fig. 4.1 and Fig. 4.2. In Fig. 4.1, we can see that the first sub-band “height”, which is defined as the difference between first sub-band and the condition band of InAs, of thin-core structure is higher than the thick one (i.e., 112 mV vs. 74 mV). Obviously, this result is due to the thickness of center InAs layer. The InAlAs/InGaAs/InAs/InGaAs/InAlAs structure is essentially a QW system, in which the thickness of composite channel determines the “width” of this QW. The thinner InAs-core corresponds to higher and more discrete eigenvalues (i.e., larger energy separation between sub-bands).
In Fig. 4.2, the electron distribution of the structures with thin-core (blue) and thick-core (black) are shown. We can see that the thin-core structure has higher peak
30
in the center. However, it does not lead to more electrons dwell in the InAs layer, since the total number of the electrons in the core is the area under the probability curve within the InAs layer. In this case, the thin-core structure has fewer electrons in the high-mobility InAs layer due to the scaled InAs thickness. Therefore, the apparent mobility of the simulated thin-InAs structure is lower than the thick one in this case. This result suggests that the scaling of the InGaAs/InAs/InGaAs structure should employ the scaling of both InAs and InGaAs layer; otherwise the reduced area in the InAs region will slightly degrade the apparent mobility of the entire structure.
This suggestion can be verified by the experimental result. Three epitaxial structures (shown in Tables 4.1, 4.2, and 4.3) with InGaAs/InAs/InGaAs of 4/5/4, 3/2/3, and 1/2/1 nm are grown by molecular beam epitaxy (MBE), and their Hall mobility are characterized to examine the effect of the composite channel thickness on the apparent mobility. It is shown that the measured Hall mobility of 4/5/4-structure is 13,500 cm2V-1s-1, which is higher than 3/2/3-strucuture (11,500 cm2V-1s-1) and 1/2/1-structure (11,100 cm2V-1s-1). We can see that although the 3/2/3-structure and 1/2/1-sturcture has the same InAs-core thickness, thinner InGaAs sub-channel leads to lower Hall mobility since more carriers dwells outside the high-mobility InGaAs/InAs/InGaAs composite channel. The previous deduction can also be verified by simulations. The In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As/ In0.52Al0.48As QW
systems with two kinds of InGaAs/InAs/InGaAs thicknesses, 3/2/3 and 1/2/1 nm, are shown in Fig. 4.3. Even though the peak population of in InAs region for 1/2/1-structure is higher than 3/2/3-structure, the 1/2/1-strcucture has more electrons outside the composite channel, leading to the small mobility degradation. The result of Hall measurements also manifested the fact that the thickness ratio (TR) of InGaAs sub-channel to InAs-core, TR = tInGaAs/tInAs, should be scaled during the optimization
31
4.1.2 Indium Composition of InGaAs Sub-channels
In order to study the influence of InGaAs sub-channel In composition on the carrier confinement in the InAs-core and the apparent mobility of the entire epitaxial structure, two In0.52Al0.48As/InxGa1-xAs/InAs/InxGa1-xAs/In0.52Al0.48As structures with
different InxGa1-xAs sub-channel In composition (70% vs. 30%) were simulated. The
purpose of choosing the large difference in In composition in the simulation is to easily visualize and address the effect of sub-channel In composition. The band diagrams, the eigenvalues of sub-bands, and the wavefunctions of these two QW systems are shown in Fig. 4.4.
In Fig. 4.4, the black line denotes the conduction band edge of the QW system with higher In composition (high-In%), and the blue line is for lower In composition (low-In%); the wavefunction in the first sub-band for low-In% and high-In% are in pink and red, respectively. We can see that there is no significant difference in the first sub-band “height” (i.e., 0.19 V for low-In% and 0.18 V for high-In%), since the thickness of every layers are the same.
In Fig. 4.5, the electron distribution of the structures with low-In% (blue) and thick-core (black) are shown. We can see that the low-In% structure has higher peak in the center. Because the InAs-thickness of low-In% and high-In% is the same, the higher peak probability corresponds to the higher apparent mobility. This result suggests that we are able to improve the carrier confinement in the InAs-core and the apparent mobility by using the sub-channel with slightly lower In composition. However, the In composition cannot be too low; otherwise it will degrade the apparent mobility since some portion of electrons travel through the lower-mobility InGaAs sub-channel.
To sum up, not only the thickness of InAs and InGaAs layers but also the In composition of InGaAs sub-channels should be optimized to achieve good electrostatic control and carrier mobility. Although the buried channel QW-MOSFET prevents the electrons from surface scattering and preserves the high-mobility-essence of InAs channel, buried channel MOSFETs usually has poor subthreshold behaviors due to the increased gate-to-channel distance. Hence the immunity to SCEs is also an important issue to QW-MOSFET.
The improvements in controlling SCEs can be obtained by the scaling of gate-to-channel distance (i.e., gate-to-2DEG distance, more precisely for the case of
32
QW-MOSFETs). This goal can be realized by reducing the thickness of InP etch stop layer, InAlAs barrier layer, and InGaAs/InAs/InGaAs composite channel. The epitaxial structures used for the fabrication of QW-MOSFETs with different optimization strategies will be presented in the next section.
4.2 Experimental Epitaxial Structures
Three kinds of structures for the experimental study of the impact of epitaxial structures on the performance of QW-MOSFETs will be shown and disused in this section. According to the thickness of composite channel and the modulation doping type, they are named regular channel (RC), thin channel (TC), and inverted thin channel (ITC), as shown in Tables 4.1, 4.2, and 4.4, respectively. The Hall mobility and sheet carrier density of all the experimental structures are summarized in Table 4.5.
The thickness of each layer of InGaAs/InAs/InGaAs composite channel structure are (unit: nm), 4/5/4 for RC, 3/2/3 for TC, and 2/3/4 for ITC. Note that the total thickness of RC is 13 nm, which is comparable to the “thin channel” works done by Kim et al [28]. In ITC structure, the In composition of two InGaAs sub-channels is slightly lower than RC and TC (65% vs. 70%). The purpose of this design is the formation of deeper QW that confines more carriers in the high-mobility InAs core.
Compared to RC, TC structure features scaled gate-to-channel distance, reduced composite channel thickness, and smaller potential drop in the barrier layer. The band diagram of the RC and TC structures is shown in Fig. 4.6. The scaled gate-to-channel distance was obtained by reducing the thickness of barrier layer and composite channel. This factor is expected to have better electrostatic control. However, the un-optimized scaling of composite channel resulted in a small degradation in the carrier mobility as mentioned in Section 4.1.1.
Compared to RC, ITC structure features ultra-scaled gate-to-channel distance, lower-In-composition sub-channel, and inverted-type modulation doping. The band diagram of RC and ITC structures is shown in Fig.4.7. The ultra-scaled gate-to-channel distance is also attributed to the inverted δ-doping. The elimination of upper InAlAs barrier layer not only reduced the gate-to-channel distance, but also reduced the S/D resistance RSD, since the intrinsic InAlAs layer is resistive. Moreover,
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the inverted modulation doping slightly makes the 2DEG away from the gate. On the other hand, the InGaAs sub-channel with lower In composition is expected to have better carrier confinement compared to the structure with higher In composition (i.e., if the thickness of each layer in the structures are the same) as discussed in Section 4.1.2. An observable difference near the InP layer is also shown in Fig. 4.7. This difference is due to the different band alignment of heterojunctions. For RC structure, the InP/InAlAs heterojunciton belongs to type II, the staggered gap. For ITC structure, the InP/InGaAs heterojunctions belongs to type I, the straddling gap. This difference affects the VT of QW-MOSFETs. The comprehensive VT calculation will be discussed
in the Appendix.
4.3 Result and Discussion
The QW-MOSFETs with RC, TC, and ITC epitaxial structures were fabricated and characterized in terms of DC and RF performance. The Lg and Wg of the
QW-MOSFETs are 0.25 μm and 40 μm, respectively, and the EOT of all devices is about 2 nm. The output and transfer characteristics for RC/TC/ITC QW-MOSFETs and RC HEMT are shown in Figures 4.8, 4.9, 4.10, and 4.11. Summary of all device performances is presented in Table 4.6, in which the DC performance of Schottky-gated RC HEMT with gate length of 60 nm is also shown for the comparison of insulated-gate and Schottky-gate InAs FETs. Favorable current saturations at low VD of 0.5 V with good pinch-off behaviors are observed in all
typical devices.
RC QW-MOSFETs represents comparable ID to 60-nm-gate RC HEMT (257
μA/μm vs. 208 μA/μm, respectively) with suppressed gate leakage current, as shown in Fig. 4.12. The gate current of QW-MOSFET is about 2.5 orders lower than HEMT, since the wide-bandgap of gate dielectric prevents gate leakage. The reason why we compare HEMT with QW-MOSFET instead of MOS capacitor is due to the difference in the high-k/semiconductor interface. The high-k/semiconductor interface of transistors is worse than MOS capacitor, since the process of transistors is more complicated than the capacitor. So the comparison among HEMT and QW-MOSFET reflects the “real” difference in gate leakage. On the other hand, the gm of RC
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length. Regarding the subthreshold behavior, the SS of QW-MOSFET is 684 mV/decade, while the SS of HEMT is only 110 mV/decade. The SS degradation is due to the poor III-V/high-k interface. Those interface states not only affect the subthreshold behavior, but also give rise to severe hysteresis phenomena, so the surface treatment before gate dielectric deposition should be optimized.
Compared to RC device, TC QW-MOSFET exhibits 6% lower ID and 11% lower
peak gm at the same bias condition, as shown in Fig. 4.13. This slight degradation can
be explained by the difference in mobility. The Hall mobility of RC structure is slightly higher than TC structure since the RC structure has better carrier confinement in InAs channel as mentioned in Section 4.1.1. However, the TC device has much better electrostatic control (SS of 187 mV/decade) due to the scaling of barrier layer and composite channel. The experimental results indicate that, even though thinner composite channel is beneficial to suppress SCEs, interface states still play an important role in the SS degradation. Furthermore, the TC device has higher VT. The
reason should be examined by the derived VT models in the Appendix. For
normal-type QW-MOSFETs (i.e, not inverted modulation doping), the VT is given
by1:
where, ΔEC,HK/InP: the conduction band discontinuity of high-k/InP interface;
ΔEC,InP/InAlAs: the conduction band discontinuity of InP/InAlAs interface;
ΔEC,InAlAs/InGaAs: the conduction band discontinuity of InAlAs/InGaAs
interface;
ΔEg: ΔEg = Eg (InxGa1-xAs)-Eg(InAs);
𝜙P: the potential change in the barrier layer,
for delta-doping, 𝜙p = q nsh tbarrier/ 𝜀barrier;
Nit : the effective charge density (/cm2) of the high-k /InP interface traps;
Nox,bulk : the fixed oxide charge density (/cm2).
1 The full derivation of V
T is shown in the Appendix. (A.1)
) 1 . 4 ( ) ( ) ( ) 2 ( ~ , 1 / , / , / , ox F it ox bulk ox ch sb P g InGaAs InAlAs C InAlAs InP C InP HK C B T C E qN C qN q E E E E V