Device Fabrication

The process flow for the InAs QW-MOSFETs of this work is shown in Fig. 3.1, and the details of the fabrication steps are summarized in Table 3.1. There are 9 major steps:

1) Device isolation,

2) Formation of the alignment marks for e-beam lithography (EBL), 3) Definition of cap-recess region by EBL,

4) Removal of the cap layer in the EBL defined area, 5) Deposition of high-k gate dielectrics by ALD, 6) Definition of contacts and the removal of dielectrics, 7) Metallization of S/D contacts and pads,

8) Gate definition by EBL, and 9) Gate metallization.

The details and purpose of each step are elaborated individually as the follows.

The last paragraph evaluates the pros and cons of this gate-last process, and summarizes the critical steps and their effect on device performance.

Device isolation was performed using phosphoric-based mixture and hydrochloric-based solution; the former selectively etches InGaAs and InAlAs layers, and the latter selectively removes InP etch stop layer. The area outside the defined region was etched down to the buffer layer in order to achieve good electrical isolation. Finally, the etch depth was measured by surface profiler after the removal of photo resist (PR). Through mesa formation, the electrically conductive slice, called

“active” region, is isolated from the contact pads. Isolation not only restricts the current flows within the active region, but also reduces parasitic resistance and capacitance. The parasitic resistance comes from the current flow between source and drain that does not pass under the gate, degrading device RF performance. Minimum parasitic capacitance was achieved by placing gate stripe on the semi-insulating

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substrate, since the capacitance is associated with the doping concentration in depletion region underneath the gate stripe.

The e-beam alignment mark was formed by lift-off process, in which the image reversal technique realized the reverse-tapered PR (i.e., AZ 5214-E) profile that enabled the lift-off process. This metallization step only served the purpose of EBL alignment and the process control monitoring (PCM) pattern for the digital etching in the cap-recess process. The design consideration of separating e-beam alignment marks and contact pads in two different steps is that: high post-deposition-annealing (PDA) temperature (400~500℃) after high-k deposition degrades ohmic contacts if S/D contacts are formed before the dielectric deposition. Therefore the thermally stable metal scheme, Ti/Au, is employed to prevent metallurgical reaction that might deform the alignment mark and hence degrade the accuracy of EBL.

The EBL of cap-recess region was performed by using typical e-beam resist (ZEP-520A) and the EBL system (JEOL JBX-6000FS). The cross-section of cap recess EBL was shown in Fig. 3.2. Length of the opened area is about 150 nm with resist thickness about 280 nm. Thinner resist profile is advantageous to the scaling of cap-recessed region, which is critical to improve the device performance, since shorter cap-recessed length reduces the parasitic resistance.

Cap-recess was conducted by the selective etching of the InGaAs cap layer over the InP etch stop layer. Citric-based and succinic-based mixtures were used for the selective etching of the native oxide on the surface and the InGaAs cap layer, respectively. We monitored the current of PCM pattern during wet etching, not only to make sure the cap layer within the opened area was removed clearly, but also to optimize the lateral etching, which determines the parasitic resistance and capacitance.

The optimized digital recess condition led to a clear removal of cap layer without long lateral etching.

High-k gate dielectric was deposited by ALD (Cambridge NanoTech Fiji-202 DCS). In this work, 5-nm Al2O3 were used as gate dielectric. Before Al2O3 deposition, the sample was passivated by in-situ trimethylaluminum (TMA) pre-treatment, which has been proven to be able to reduce Dit [31]. In fact, other thinner high-k materials with higher dielectric constant such as HfO₂ and La₂O₃ can also be employed in order to decrease effective oxide thickness (EOT), which is helpful to boost device performance including I_D, g_m, on-off current ratio (I_ON/I_OFF), and SS. However,

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because this research focuses on device bandgap engineering, other high-k stacks and the surface treatments were not used for convenience.

After the photolithography for contacts and pads, the dielectric within the opened area was removed by dilute hydrogen fluoride (DHF) solution, and a treatment using dilute hydrochloric acid was performed before ohmic metallization. The contacts and pads were formed by alloyed Au/Ge/Ni/Au stack. The purposes of this conventional ohmic metal scheme are two-fold: 1) Au/Ge alloy improves adhesion between semiconductor and metal; 2) Ge diffuses into the InGaAs cap layer during the annealing after metallization, and drastically increase the doping concentration few nm underneath the metal. After the lift-off process, excellent specific contact resistance of 1.27×10^-7 Ω-cm² was extracted by transmission line measurement (TLM). Although the extracted value is below the measurement limit of TLM, the result still suggested a good ohmic contact.

Finally, gate EBL and the corresponding metallization were performed. The gate width (W_g) and L_g of the InAs QW-MOSFETs are 40 μm and 250 nm, respectively.

The cross-sectional SEM image of the gate stripe is shown in Fig. 3.3. The gate metal scheme used in this work was Ti/Au. After e-beam evaporation, typical e-beam resist stripper, ZDMAC, was used in this lift-off process. The device structure is shown in Fig 3.4.

Finally, the device was passivated by the SiN_x grown by plasma enhanced chemical vapor deposition (PECVD). The via was formed after device passivation.

The key process steps can be divided into several categories according to their effects on device: 1) cap recess EBL, cap etching, and source-drain spacing; 2) surface treatment and PDA condition; 3) gate dielectric materials and thickness; 4) gate EBL; 5) gate stack (which includes the materials for gate metal and gate oxide).

They determine parasitic resistance, Dit, EOT, Lg, and VT respectively.

In a nutshell, the devices employed a “gate-last” process. However, as we know, the devices undergone “gate-first” process have better metal-gate/high-k and high-k/semiconductor interfaces. This is attributed to the fact that the interfaces in gate-first process are kept way from the chemicals and deleterious processing environments that introduce interface states during device fabrication steps. However, because we only have contact aligner to define the S/D contacts and pads, if the gate is formed before contacts, the gate might break during the photolithography using

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contact aligner. Therefore, we have to choose gate-last process, even though its relatively higher D_it may degrade the subthreshold behaviors.