Result and Discussion - Fabrication and Characterization of Quantum Well MOSFET

Fabrication and Characterization of Quantum Well MOSFET

4.3 Result and Discussion

The QW-MOSFETs with RC, TC, and ITC epitaxial structures were fabricated and characterized in terms of DC and RF performance. The L_g and W_g of the QW-MOSFETs are 0.25 μm and 40 μm, respectively, and the EOT of all devices is about 2 nm. The output and transfer characteristics for RC/TC/ITC QW-MOSFETs and RC HEMT are shown in Figures 4.8, 4.9, 4.10, and 4.11. Summary of all device performances is presented in Table 4.6, in which the DC performance of Schottky-gated RC HEMT with gate length of 60 nm is also shown for the comparison of insulated-gate and Schottky-gate InAs FETs. Favorable current saturations at low VD of 0.5 V with good pinch-off behaviors are observed in all typical devices.

RC QW-MOSFETs represents comparable ID to 60-nm-gate RC HEMT (257 μA/μm vs. 208 μA/μm, respectively) with suppressed gate leakage current, as shown in Fig. 4.12. The gate current of QW-MOSFET is about 2.5 orders lower than HEMT, since the wide-bandgap of gate dielectric prevents gate leakage. The reason why we compare HEMT with QW-MOSFET instead of MOS capacitor is due to the difference in the high-k/semiconductor interface. The high-k/semiconductor interface of transistors is worse than MOS capacitor, since the process of transistors is more complicated than the capacitor. So the comparison among HEMT and QW-MOSFET reflects the “real” difference in gate leakage. On the other hand, the gm of RC QW-MOSFET is much smaller than that of RC HEMT due to the difference in gate

length. Regarding the subthreshold behavior, the SS of QW-MOSFET is 684 mV/decade, while the SS of HEMT is only 110 mV/decade. The SS degradation is due to the poor III-V/high-k interface. Those interface states not only affect the subthreshold behavior, but also give rise to severe hysteresis phenomena, so the surface treatment before gate dielectric deposition should be optimized.

Compared to RC device, TC QW-MOSFET exhibits 6% lower ID and 11% lower peak gm at the same bias condition, as shown in Fig. 4.13. This slight degradation can be explained by the difference in mobility. The Hall mobility of RC structure is slightly higher than TC structure since the RC structure has better carrier confinement in InAs channel as mentioned in Section 4.1.1. However, the TC device has much better electrostatic control (SS of 187 mV/decade) due to the scaling of barrier layer and composite channel. The experimental results indicate that, even though thinner composite channel is beneficial to suppress SCEs, interface states still play an important role in the SS degradation. Furthermore, the TC device has higher V_T. The reason should be examined by the derived V_T models in the Appendix. For normal-type QW-MOSFETs (i.e, not inverted modulation doping), the V_T is given by¹:

where, ΔEC,HK/InP: the conduction band discontinuity of high-k/InP interface;

ΔEC,InP/InAlAs: the conduction band discontinuity of InP/InAlAs interface;

ΔEC,InAlAs/InGaAs: the conduction band discontinuity of InAlAs/InGaAs interface;

ΔEg: ΔEg = Eg (InxGa1-xAs)-Eg(InAs);

𝜙P: the potential change in the barrier layer, for delta-doping, 𝜙_p= q n_sht_barrier/ 𝜀_barrier;

Nit : the effective charge density (/cm²) of the high-k /InP interface traps;

N_ox,bulk : the fixed oxide charge density (/cm²).

Because the other materials-related parameters for TC and RC structures are the same and the 𝜙p for TC is smaller than RC due to thinner barrier layer (i.e., smaller tbarrier), the VT of TC device is expected to be higher than RC device. The experimental result also verifies our deduction: the VT of TC QW-MOSFET is -0.09 V, and the VT of RC device is -1.12 V.

ITC QW-MOSFET demonstrates the best output and transfer characteristics (Fig.

4.14) among the three device structures: ID of 505 μA/μm, peak gm of 412 μS/μm. The ID is about twice larger than RC device and the peak gm also has over 50%

improvement. The great improvement over RC and TC devices is based on the reduced parasitic resistance and increased gate capacitance. The equivalent circuits near the S/D side in term of resistance for normal-type and inverted-type QW-MOSFETs are shown in Fig. 4.15. The total parasitic source (or drain) resistance of normal-type device is given by: R_S(norm.) = r_c+r_cap+r_{etch stop}+r_barrier ; and the parasitic resistance of inverted-type device is expressed as: R_S (inv.) = r_c+r_cap+r_{etch stop} , where r_C is the contact resistance, and the other subscripts stands for the resistance component in that layer. Clearly, the inverted-type device possesses smaller parasitic resistance by the elimination of upper InAlAs layer, which is known to be the largest resistance component. One the other hand, the equivalent circuits of composite channel QW-MOSFETs’ gate stack in term of capacitance is shown in Fig. 4.16. The gate capacitance, C_G, can be expressed as²:

where the subscripts ox, it, ins, Q, centroid stand for the capacitance component of gate dielectric, interface states, insulator layer (i.e., InP and InAlAs), quantum capacitance, and centroid capacitance. The insulator capacitance (Cins) of normal-type device is the series combination of two capacitance components (i.e., device. This improvement in SS is attributed to the ultra-scaled gate-to-channel

distance achieved by inverted modulation doping. However, the SS of TC device is still better than ITC. Moreover, the I_ON/I_OFF of ITC devices is in the order of 10², which is far below the requirement for logic application (~10⁵). This poor ratio is caused by higher modulation doping concentration, as mentioned in Section 2.2 (cf.

Fig. 2.3). The improvement in ION/IOFF can be realized by lowering the concentration of δ-doping or replacing the ohmic metal stack with Schottky metal scheme to suppress off-state leakage (IOFF). But the latter method is not preferred, since Schottky S/D not only reduces IOFF, but also reduces ION. However, the overall evaluation in terms of ID and gm still indicates that ITC structure is a more suitable design for future low-power and high-performance logic applications.

The on-wafer RF measurement of RC QW-MOSFET and ITC QW-MOSFET are also conducted to evaluate their potential in high frequency applications. The microwave characteristics of RC and ITC devices without de-embedding are shown in Fig. 4.17. The extrinsic f_T and f_max are extracted by extrapolation with theoretical -20 dB/decade slope and the devices are biased at low V_D of 0.5 V. For RC device, the extrinsic f_T and f_max are 32 GHz and 53 GHz. The extrinsic f_T and f_max of ITC device are 70 GHz and 82 GHz. It is shown that ITC device exhibits better microwave performance and the ITC structure is also a preferable design for the RF and microwave applications.

Finally, the ITC device is also benchmarked with the similar works done by other research groups. The current drive at VD of 0.5 V as a function of gate length of the benchmarked devices is presented in Fig. 4.18. The ITC QW-MOSFET in this work has good current drive and RF performance without using sub-100-nm-gate like other works.

4.4 Summary

A thoroughgoing investigation into the bandgap engineering of InAs composite channel is obtained. The conclusions of this chapter are drawn and listed as follows:

 The structure with lower-In-composition sub-channel improves carrier confinement in the InAs-core. The better carrier confinement results in the improved transport properties. However, the In composition of sub-channel cannot be too low; otherwise the decreased mobility in sub-channel will degrade the apparent mobility of the entire structure.

 The device with thinner composite channel structure effectively suppresses SCEs by reducing gate-to-channel distance. The TR should be optimized during the scaling of entire composite channel. Moreover, the interface states still play an important role in SS degradation, which is hard to be compensated by simply using thin composite channel structure.

 The device with ITC structure exhibits good I_D and g_m, but mediate SS. The improvement in I_D and g_m is due to the reduced parasitic resistance and higher gate capacitance caused by the elimination of upper InAlAs layer.

The improved immunity to SCEs is attributed to the thinner composite channel and ultra-thin InP layer.

 The experimental results shows that ITC InAs QW-MOSFET is a promising candidate for future low-power high-performance logic and microwave applications if the optimized surface treatment, scaled Lg, and reduced EOT are realized.

Table 4.1 Experimental epitaxial structure 1: regular channel (RC).

Materials In % Thickness (A)

Dopant &

Concentration Cap n⁺-InGaAs 53 450 Si, 5×10¹⁹ cm^-3

Etch Stop i-InP 100 50

Barrier i-InAlAs 52 80

δ-doping Si - - Si, 4×10¹² cm^-2

Spacer i-InAlAs 52 50

Channel

i-InGaAs 70 40

i-InAs 100 50

i-InGaAs 70 40

Buffer i-InAlAs 52 5000

3” semi-insulating InP substrate

Table 4.2 Experimental epitaxial structure 2: thin channel (TC).

Materials In % Thickness (A)

Dopant &

Concentration Cap n⁺-InGaAs 53 450 Si, 5×10¹⁹ cm^-3

Etch Stop i-InP 100 50

Barrier i-InAlAs 52 50

δ-doping Si - - Si, 4×10¹² cm^-2

Spacer i-InAlAs 52 30

Channel

i-InGaAs 70 30

i-InAs 100 20

i-InGaAs 70 30

Buffer i-InAlAs 52 5000

3” semi-insulating InP substrate

Table 4.3 Experimental epitaxial structure 3: ultra-thin channel (UTC).

Materials In % Thickness (A)

Dopant &

Concentration

Cap

n⁺-InGaAs 65 40 Si, 2×10¹⁹ cm^-3 n⁺-InGaAs 53 150 Si, 2×10¹⁹ cm^-3 n⁺-InAlAs 52 150 Si, 2×10¹⁹ cm^-3 Etch

Stop i-InP 100 30

Barrier i-InAlAs 52 20

δ-doping Si - - Si, 4×10¹² cm^-2

Spacer i-InAlAs 52 30

Channel

i-InGaAs 70 10

i-InAs 100 20

i-InGaAs 70 10

Buffer i-InAlAs 52 6000

3” semi-insulating InP substrate

Table 4.4 Experimental epitaxial structure 4: inverted thin channel (ITC).

Materials In % Thickness (A)

Dopant &

Concentration Cap n⁺-InGaAs 53 250 Si, 2×10¹⁹ cm^-3

Etch Stop i-InP 100 30

Channel

i-InGaAs 65 20

i-InAs 100 30

i-InGaAs 65 40

Spacer i-InAlAs 52 30

δ-doping Si - - Si, 3×10¹² cm^-2

Buffer i-InAlAs 52 5000

3” semi-insulating InP substrate

Table 4.5 Summary of the Hall measurement.

Epitaxial Structure RC TC UTC ITC

Composite Channel Structure InXGa1-XAs/InAs/InXGa1-XAs

(unit: nm)

4/5/4 3/2/3 1/2/1 2/3/4

Sub-channel In % 70 70 70 65

Hall Mobility (cm²V^-1s^-1)

13,400 11,500 11,100 12,400 Sheet Carrier Concentration

(×10¹² cm^-2)

2.95 3.24 3.02 2.81

Table 4.6 Summary of the DC and RF performance of QW-MOSFETs and HEMT fabricated in this work.

QW-MOSFET HEMT

channel type RC TC ITC RC

gate length 250 250 250 60

ID (μA/μm)

@ VD = 0.5V 257 242 505 208

peak g_m(μS/μm)

@ V_D = 0.5V 270 241 412 584

SS (mV/decade) 684 187 312 110

DIBL (mV/V) 198 170 183 137

VT (V) -1.12 -0.09 -0.85 -0.35

I_ON/I_OFF 1.27×10² 9.6×10³ 5.73×10² 8.53×10³

f_T (GHz) 32 N/A 70 N/A

fmax (GHz) 53 N/A 82 N/A

Fig. 4.1 The conduction band edge profiles of the QWs with different InAs-core thickness in the composite channels. The simulated QW structures consist of In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As /In0.52Al0.48As with InGaAs/InAs/InGaAs thicknesses of 5/5/5 and 5/2/5 nm.

Fig. 4.2 The wavefunction in first sub-band of the QWs with different InAs-core thickness in the composite channels. The simulated QW structures consist of In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As /In0.52Al0.48As with InGaAs/InAs/InGaAs thicknesses of 5/5/5 and 5/2/5 nm.

Fig. 4.3 The In0.52Al0.48As/In0.7Ga0.3As/InAs/In0.7Ga0.3As/In0.52Al0.48As QW systems with two kinds of InGaAs/InAs/InGaAs thicknesses, 3/2/3 and 1/2/1 nm.

Fig. 4.4 The conduction band profiles of two QW systems with different In composition in the InGaAs sub-channels. Two kinds of In composition, In0.7Ga0.3As and In0.3Ga0.7As, are used to emphasize the difference in In composition.

Fig. 4.5 The wavefunction in first sub-band of the QWs with different sub-channel In composition of 70% and 30%.

Fig. 4.6 The band diagrams of the RC and TC structures.

InP InAlAs InGaAs/InAs/InGaAs InAlAs

Fig. 4.7 The band diagrams of the RC and ITC structures.

InP InAlAs InGaAs/InAs/InGaAs InAlAs InAlAs

InP InGaAs/InAs/InGaAs InAlAs

Fig. 4.8 (a) output characteristics and (b) transfer characteristics of RC QW-MOSFET.

Fig. 4.9 (a) output characteristics and (b) transfer characteristics of TC QW-MOSFET.

Fig. 4.10 (a) output characteristics and (b) transfer characteristics of ITC QW-MOSFET.

Fig. 4.11 (a) output characteristics and (b) transfer characteristics of RC HEMT.

Fig. 4.12 RC QW-MOSFET vs. RC HEMT (a) ID-VD (b) ID-VG.

Fig. 4.12 (cont.) RC QW-MOSFET vs. RC HEMT (c) gm-VG (d) IG-VG.

Fig. 4.13 TC QW-MOSFET vs. RC QW-MOSFET (a) ID-VD (b) ID-VG.

Fig. 4.13 (cont.) TC QW-MOSFET vs. RC QW-MOSFET (c) gm-VG (d) semi-log IG-VG.

Fig. 4.14 ITC QW-MOSFET vs. RC QW-MOSFET (a) ID-VD (b) ID-VG.

Fig. 4.14 (cont.) ITC QW-MOSFET vs. RC QW-MOSFET (c) gm-VG (d) semi-log IG-VG.

Fig. 4.15 The equivalent circuits near the S/D side in term of resistance for normal-type and inverted-type QW-MOSFETs.

Fig. 4.16 The equivalent circuits of composite channel QW-MOSFETs’ gate stack in term of capacitance, where the subscripts ox, it, ins, Q, centroid stand for the capacitance component of gate dielectric, interface states, insulator layer (i.e., InP and InAlAs), quantum capacitance, and centroid capacitance.

Fig. 4.17 Microwave characteristics of (a) RC QW-MOSFET (b) ITC QW-MOSFET.

Fig. 4.18 Benchmarking of the InAs/InGaAs MOSFETs and HEMTs. The ITC QWMOSFET is benchmarked to the similar works using InAs and high-In InGaAs channels. The benchmarked devices are made by [29], [28], [25], [18], and [13], respectively.

Chapter 5

Hysteresis Effect

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