Device Measurement System

After completing the experimental process and before measuring the samples, all of our samples were conserved in the vacuum environment to avoid exposure to moisture and oxygen.

The current−voltage characteristics of this study were measured at room temperature under the atmosphere by a probe station connected with the Keithley 4200−SCS semiconductor parameter analyzer in a dark room. In the ID-VD measurement, the drain bias was swept from 0 to -45 Volts and the gate voltage step were 0, −15, −30,

−45, and −60 Volts, respectively. In the ID-VG measurement, the gate bias ranged from +10 to −60 Volts, and the drain voltage step were 0, −15, −30, −45, and −60 Volts. To investigate into the effective contact resistance, the ID−VD curve was measured by small drain bias sweeping from 0 to −1 Volts and the step at each volt of gate voltage ranging from 0 to −90 Volts.

Chapter 4 THEOREM & ANALYSIS METHOD

4.1 Morphology of Pentacene Thin Films

In our study, the crystal structure and morphology properties of pentacene thin film were investigated by using atomic force microscopy (AFM) and X-ray diffraction (XRD). In this chapter, the analysis methods of AFM images and the theorems of XRD-spectra analysis were investigated.

The characterization of the surface morphology of pentacene thin film was examined by AFM (Digital Instruments NanoScope Dimension D3100 probe microscope system). Each of our images was recorded in tapping mode in air with 1 Hz of scan rate and 256×256 dpi. To examine the post-annealing effect on pentacene grain in channel, in bulk, and in contact area, we prepared pentacene thin-film samples with different thickness: 5, 10, 20, 30, and 60 nm. The value of root-mean-square roughness (Rrms) of film was obtained by analyzing over 3×3 μm² area using the built-in software of the AFM instrument. Figure 4.1 displays one of the surface morphology from our samples, and a Rrms of 7.599 nm is obtained. Moreover, a program of MATLAB was used to calculate the density of grain boundary. The grain boundaries defined by the

(μm)^-1.

(a)

(b) Figure 4.1 (a) The R_rms of this AFM image is 7.599 nm , which was obtained by analyzing

over 3×3 μm² area using the built-in software of the AFM. (b) The grain boundaries defined by a program of MATLAB. The detail of the program is shown in APPENDIX.

4.2 Pentacene Crystal Structure [5]

The characterization of our pentacene thin film structure was investigated by XRD, which is the direct evidence for the periodic atomic structure of crystals. The specification of XRD is M18 XHF, MacScience. The XRD measurements were performed to 60-nm thick pentacene thin films, and it was operated with Cu-Kα (λ = 1.5406 Å) radiation in a symmetric reflection, coupled θ−2θ mode. Phase identification using XRD relies mainly on the positions of the peaks in a diffraction profile and to some extent on the relative intensities of these peaks. The shapes of the peaks, however, contain additional and valuable information. The shape, particularly the width, of the peak is a measurement of the amplitude of thermal oscillations of the atoms at their regular lattice sites. It can also be a measurement of vacancy and impurity element concentrations and even plastic deformation, any factor which results in a distribution of d-spacings. In the following sections, we will discuss about how we analyze our XRD data.

4.2.1 Pentacene Phase - From Bragg’s Law

The principle of diffraction is described by Bragg’s law, which refers to the simple equation:

hkl hklsin 2d

nλ= θ (4.1) Intensity-peaks represent multiple lattice spacings (d), which can be labeled as (hkl) peaks. Each d corresponds to a specific angle (θ ). λ is the wavelength of the

incident X-ray beam, and n is an integer. A XRD-spectrum consists of the position (2θ) and the intensity of (hkl) peaks. The former implies some information about crystal structures such as size and sharp, and the latter reveals what kind of atoms are included in a film and how these atoms arrange.

One of our pentacene X-ray diffraction (λ = 1.5406 Å) spectra is shown in Figure 4.2. Five intensity-peaks represent multiple dhkl. According to the Bragg’s law, (001) peak at 5.7^o corresponds to d001 with value of 15.49 Å.

5 10 15 20 25 30

(005) (004)

(001)

(002)

(003)

2 θ ( deg. )

Intensity (a. u.)

Figure 4.2 The XRD spectrum for 60-nm thick of pentacene thin films. There are five intensity-peaks, (00l), l = 1, 2, …, 5.

Similar result has been reported by C.D. Dimitrakopoulos et al. The value of d001

was found to be 15.4 Å. [4] However, the expected [32-33] single-crystal structure of pentacene in triclinic with a = 7.90 Å, b = 6.06 Å, c= 16.01 Å, α = 101.9 Å, β = 112.6

Å, and γ = 85.8 Å. In such a structure, the (001) plane spacing d001 is ∼14.5 Å.

Obviously, the result of d001 = 15.49 Å is attributed to a phase different with single crystalline phase, called “thin film phase.” The other pentacene phase with (001) peak at 6.1^ο is called “bulk phase,” which is closer to the (001) peak of single crystal phase at 6.25^ο. Only (00l) peaks are found in pentacene XRD-spectrum with the absence of any other (hkl) peaks, which indicates that all the pentacene crystals in the film are oriented along their (00l) planes parallel to the substrate.

4.2.2 Pentacene Crystal Size - From Scherrer Equation

[34-35]

There are two ways to calculate pentacene grain size along c-axis, the Scherrer Equation and Paracrystal Theory. The crystallite size measured by the Scherrer method is given by

cosθhkl

δθ λ

hkl hkl

L = K (4.2)

Here L^hkl is the volume-weighted size, θhkl is the Bragg angle, λ is the wavelength of the X-ray, and K is unit cell geometry dependent constant whose value is typically between 0.85 and 0.99. δθ _hkl is the full width of the peak at half maximum of Bragg’s peak intensity (FWHM) in radians.

4.2.3 Pentacene Crystalline - From Paracrystal Theory [36-39]

Paracrystal theory is another way used to calculate pentacene crystal size along c-axis. To use both methods to verify our results becomes reliable. From the formula of paracrystal theory,

we can obtain two important parameters, L and _hkl g_II, from the intercept on the ordinate axis and the slope of the straight line determined by the least-squares fitting.

Here L specifies the mean crystal size vertical to the plane (hkl), and _hkl g_II represents the distance fluctuation between successive planes of the family (hkl) or second kind of distortion of crystal structure.

Besides,(δs)_c is the broadening associated with the size of the crystal domain, s)II

(δ stands for the broadening due to lattice distortions of the second kind, m is the order of the diffraction, and d is the mean spacing between (hkl) planes. _hkl² (δs)₀ is the overall broadening excluding instrumental broadening and is further described by:

λ full width of the peak at half maximum of Bragg’s peak intensity (FWHM) in radians.

Chapter 5 RESULTS & DISCUSSION

5.1 The Effect on Pentacene Crystal

5.1.1 The Analysis of Film Morphology

Figure 5.1 (a) and 5.1 (b) show AFM images of pentacene thin films near the channel [40] for the as-prepared sample and the thermally annealed sample, respectively.

From the AFM images, we can find that the layer-by-layer of pentacene growth and the grain boundary in channel became less apparent, especially after post-annealing.

Pentacene grains seem to make better convection with each other and the grain size is slightly larger after thermal annealing. Further, the density of grain boundary reduces from 1.35 (μm)^-1 to 1.16 (μm)^-1 after thermal annealing, that is 14 % decrease. Since it has been reported that grain boundaries limit the charge transport in thin organic films, we can presume that the annealed device with less grain boundaries exhibits better electrical properties than the un-annealed one. [19]

(a) (b) Figure 5.1 5-nm pentacene thin films for (a) as-prepared and (b) thermally annealed

samples.

Figure 5.2 (a)-(f) are the images of pentacene thin films with different thicknesses and annealing condition. From the AFM images, it seems reasonable that the grain size only grows slightly, because the grain size of pentacene is dominated by the nucleation sites on substrate [41] and interaction/aggregation forces between pentacene/substrate molecules. [42] Thermal annealing treatment will not influence the number of nucleation sites.

From Figure 5.2 (e) and (f), the Rrms values calculated by the built-in software of AFM instrument showed that the film morphology are decreased after the thermal annealing treatment. It is well known that the rougher the surface is, the larger contact area becomes. Therefore, the contact area of pentacene/gold interface should be reduced after the thermal annealing treatment.

(a) (b)

(c) (d)

(e) (f)

Figure 5.2 20-nm Pentacene thin films (a) as-prepared, (b) after thermal annealing.

30-nm thick samples (c) as-prepared, (d) after thermal annealing. 60-nm thick samples (e) as-prepared, and (f) after thermal annealing.

5.1.2 The Analysis of XRD spectra

XRD was carried out to study the crystal structure of the pentacene thin films, as shown in Figure 5.3. As discussed in Chapter 4, there are five intensity peaks and only (00l, l = 1,2,…5) peaks are found, indicating that all the pentacene crystals in the film are oriented along their (00l) planes parallel to the substrate. Whether the thermal annealing treatment was performed or not, only thin-film phase was observed in the spectra. This result reveals that the change of device performance is independent of the pentacene phase transition. After thermal annealing, the Bragg’s peak intensity was significantly boosted, which implies the fact that thermal annealing treatment indeed improves the pentacene molecular ordering. The similar results have been proposed in reference [12].

Table 5.1 specifies the XRD parameters deduced from Equations (4.2), (4.3), and (4.4). Combined Equation (4.3) and (4.4), the following equation is obtained:

4

By Substituting θhkl and FWHM of each Bragg’s peak in Figure 5.3 into Equation (5.1), a plot of (δs)02 versus the fourth power of the diffraction order m⁴ (Figure 5.4) can be obtained. By linear fitting, L and g_hkl II can be obtained from the intercept and slope of Equation (5.1), respectively. Both Scherrer Equation and Paracrystal Theory showed that the mean crystal size vertical to substrate is decreased after thermal annealing. The values of gII below 2 % indicate that the structural perfection of pentacene crystalline is high [5]. After the thermal annealing treatment, the second kind of lattice distortion became more serious (increasing from 1.3 to 1.7 %).

5 10 15 20 25 30

Figure 5.3 The XRD spectra obtained from 60 nm-thick pentacene films. The inset shows the XPS spectrum near (002) intensity peak.

200 400 600 intercept and slope of this plot, we can obtain the mean crystal size vertical to substrate and second kind of distortion of crystal structure.

Table 5.1 The analysis of XRD spectra.*

Condition Intensity FWHM (deg.)

L

hkl

(nm)

Lhkl

(nm)

g

II

(

^%

)

As prepared 575 0.136 58.0 33.0 1.3

With treatment 4333 0.229 34.5 20.5 1.7

* L_hkl is calculated from Scherrer Equation. L_hkl and g_II are evaluated from Paracrystal Theory.

5.2 The Effect on Device Property

5.2.1 Electrical Characteristics

In the beginning, we tried the annealing condition for different annealing temperature at 60, 90, and 120 ^οC for 80 min. The key results were listed in Table 5.2.

We found that annealing at 90 ^οC gave to better device performance.

Table 5.2 The device performance*

Annealing Condition

μ_sat

(cm

²

/Vs)

V

T

(V)

I

on/

I

off

As prepared 0.42 -17.4 3×10⁶

Annealing at 60 ^oC 0.54 -17.9 7×10⁶

Annealing at 90 ^oC 0.80 -19.1 2×10⁷

Annealing at 120 ^oC 0.49 -21.2 6×10⁶

* The device performance of pentacene-based TFT at different annealing temperature: room temperature (without annealing), 60, 90, and 120 ^oC, respectively.

However, while the temperature is higher than 120 ^oC, the device performance degrades. Since, the best device performance was achieved at 90 ^oC in our experiment, so that the condition of annealing treatment was set to be at 90 ^oC for 80 min in the following discussions.

First, we focused on the post-annealing effect on the device performance. The resulting characteristics were presented in Figures 5.5, which exhibits the common TFT behavior as described in Chapter 2. The influence of the post-annealing treatment can be seen clearly. The drain current (ID) was dramatically increased after the post-annealing treatment. The log|ID|−VGS characteristics provide some information about the post-annealing effect. First, the Ion/Ioff was increased by almost one order after post-annealing. The S.S. also decreased from 2.5 V/decade to 1.4 V/decade, and the VT

shifted from −17.4 to −19.1 V. From the (ID)^1/2-VGS characteristic, it was found that the device mobility increased from 0.42 to 0.80 cm²V^-1sec^-1 in the saturation regime for VDS

= −60 V. Obviously, the device performance has been improved by the thermal annealing treatment.

0 -10 -20 -30 -40 -50 Figure 5.5 The current-voltage characteristics of pentacene-based TFT with anneal/

un-annealed condition. (a) The drain current ID versus the drain-source voltage VDS at VGS

= −60 V and (b) the absolute value of the drain current and the logarithmic drain current versus the gate-source voltage VGS at VDS = −60 V. The post-annealing treatment was carried out at 90 ^oC for 80 min in a N₂-filled glove box.

5.2.2 Resistance Analysis

The device performance can be significantly improved, as mentioned above. In order to clarify the underlying mechanism, the device resistance was further investigated. Figure 5.6 shows a simplified equivalent OTFT circuit where the conducting path is divided into three parts of resistance, rch, rC, and rbulk.

As shown in Figure 5.7 (a), it is obviously observed that the channel resistance was significantly reduced after post-annealing.Accordingly, we can presume that a number of defects in the pentacene grain boundary in the channel were removed after the thermal annealing treatment. This improvement probably can be explained by the reduced number of defects existing in the grain boundary in the channel regime. The rbulk and rC were estimated by the method published by M. Shur in 1990. The concepts of M. Shur’s theorem have been discussed in Chapter 2. According to this method, rC

and rbulk can be discussed individually, and the equivalent circuit is shown in Figure 5.7(b).

Figure 5.6 The simplified equivalent OTFT circuit, where the conducting path is divided into three parts of resistance, rch, rC, and rbulk.

-20 -40 -60 -80 10M

20M

30M as-prepared

with annealing treatment

Channel resistance

(

Ω/μm

)

Gate Voltage (V)

(a)

-20 -40 -60 -80

0 3 6

9 as-prepared

with annealing treatment

Eff ect series r esistance (

Ω

cm

2

)

Gate Voltage (V)

(b) Figure 5.7 Resistance characteristics of pentacene-based TFT with/without the annealing

treatment. (a) the channel resistance versus gate voltage V_GS and (b) the effective series resistance versus V_GS. In our assumption, effective contact resistance r_C is V_GS independent and effective bulk resistance rbulk is variable with VGS. The effective series resistance is equal to the sum of rC and rbulk.

To simplify our problem, rC was assumed to be independent of VGS, and therefore rbulk is a function of VGS. Taking this assumption into consideration, rbulk can be negligible as compared to rC at high VGS. The values of rC for the untreated and the thermally annealed devices are 0.003 and 0.235 Ω-cm², respectively. In addition, the influence of rbulk is extremely large than rC at low VGS. After post-annealing, both rC

and rbulk increase, which are harmful to device performance. Combining the change of pentacene crystals and that of device performance, it is believed that the increased rC is attributed to the reduced pentacene surface roughness. Since the contact area of pentacene/gold interface is reduced after post-annealing. Further, the increased rbulk is due to the more serious lattice distortion which does not facilitate the carrier transport in pentacene.

As shown in Table 5.3, although both of rC and rbulk increased, rch decreased. For our devices, the channel lengths range form 75 to 160 μm. The decreased amount of rch

is much more than the increased sum of rC and rbulk. Therefore, the total resistance of pentacene-based TFTs is decreased after post-annealing treatment. However, it must be noticed that the reduced degree of rch is much smaller than the increased degree of μsat.

Accordingly, some other factors are expected to influence the device performance. The DC stress degradation on the OTFT devices was subsequently performed.

Table 5.3 The key parameters of devices*

Annealing Condition

μ_sat

(cm

²

/Vs)

r

C

(

^Ω

-cm

²

)

r

bulk

(

^Ω

-cm

²

)

r

ch

(M

^Ω

/

^μ

m)

As prepared 0.42 0.003 0.007 11.9

Annealing at 90 ^oC 0.80 0.235 0.432 10.1

* The resistance of device with different annealing condition obtained under V_GS = −60 V.

5.2.3 DC Stress Degradation

The ID of the TFTs was measured under a continuous DC voltage biases of VGS =

−30 V. As shown in Figure 5.8, the post-annealing treatment is effective in the reduction of DC stress degradation from more than 50 % to less than 40 %. It is believed that the change of DC bias stress is associated with the traps induced by molecular defects, disorder, and/or impurities. Deep trapping of carriers lead to a decrease of ID. [26] As a result, the reduction of defects can relieve the phenomenon of charge trapping, thus improving the device stability under DC stress and device performance.

500 1000 1500 2000 0.5

0.6 0.7 0.8 0.9 1.0

Time (s)

N orm alized D rain cur rent

as-prepared

with annealing treatment

Figure 5.8 The DC stress of the pentacene-based TFTs. The continuous DC voltage bias was VGS = −30 V lasting for 2500 sec.

5.3 Trap Calculation

In the previous sections, the changes of electrical properties, AFM images, and XRD patterns after the post-annealing treatment were systematically studied. In the following parts, experimental results were further discussed by the trap calculation.

5.3.1 Grain Boundaries

The grain boundary trap density (NGB) can easily be estimated from the fitting of the Levinson plot of ln(ID /VGS) versus 1/ VGS. [43-44] Here ID can be approximated by

The Levinson plot for our devices is shown in Figure 5.9. According to Equation (5.2) and the slopes of Figure 5.9, NGB of un-annealed and annealed devices are calculated to be 2.6×10¹² cm^-2 and 2.3×10¹² cm^-2, respectively. The 11.5 % reduction of NGB proves that traps in grain boundaries are decreased after post-annealing. This result explains why the device performance and channel resistance are improved. From AFM images and XRD spectra, the reduced trap density must be attributed to the decreased GB density of AFM images.

0.000 0.025 0.050 0.075 0.100 the trap density at the grain boundary can be estimated by the slope of this diagram.

5.3.2 Interface

For further investigating, we focus on the interface quality of pentacene and PαMS-modified SiO2. The maximum interface trap density (Nit(max)) could be estimated by the approximation [45]: where Ci is the capacitance per unit area, k is Boltzmann’s constant, T is the absolute temperature, and S.S is the minimum sub-threshold swing deduced from the transfer curve of devices. From our calculation, the approximate Nit(max) of PαMS-modified devices was decreased from 3.60×10¹² cm^-2eV^-1 to 1.97×10¹² cm^-2eV^-1 after

post-annealing treatment. The decrease of Nit(max) might be due to the surface modification of PαMS at the pentacene/SiO2 interface. The glass transition temperature (Tg) of PαMS at atmosphere is 85 ^οC. Above Tg, PαMS becomes soft and behaves as rubbery state. During the thermal annealing treatment, the soft PαMS could make the interfacial adhesion better. Defects and voids near the interface are extensively removed and filled, respectively, after the post-annealing treatment, which leads to the decrease of the rC and Nit(max). Further, we made a comparison of devices with and without surface treatment in Table 5.4.

Table 5.4 The parameters of devices with/without surface treatment*

Annealing Condition Surface

* The device properties were obtained under VGS = −60 V.

The surface treatment is indeed helpful to the decrease of interface traps. The Nit(max) of devices without surface treatment was only 17 % decreased after post-annealing. On the contrary, Nit(max) of devices with surface treatment was

extremely decreased by 45 % after post-annealing. By combining surface treatment with post-annealing treatment, the Nit(max) was significantly decreased by 70

%. Obviously, surface treatment not only improved the device performance but also enhanced the degree of the improvement induced by the post-annealing effect.

5.3.3 Summary

The surface roughness of pentacene at the pentacene/gold interface was decreased after the annealing treatment, leading to a decrease of contact area. This explained the increase of contact resistance. Through the XRD analysis, the lattice distortion became seriously after thermal annealing. The serious lattice distortion gave rise to the increase of bulk resistance.

After thermal annealing, the AFM images showed that the GB density was decreased, and the NGB was proved to be decreased from Equation (5.2) In addition, the Nit(max) at pentacene/insulator interface was also decreased. The reduction of traps must lead to a decrease of the channel resistance. Furthermore, the reduction of DC stress degradation also explained the reduction of defects and traps. The decrease of Nit(max)

was more distinct than that of NGB, showing that the post-annealing effect on pentacene/insulator interface was the most critical to the device performance.

Chapter 6 CONCLUSIONS

In this study, we controlled the morphology of pentacene through the post-annealing treatment, followed by studying the correlation between the thin-film morphology of pentacene and TFT device performance. The aims of our research are to find out the effect of post-annealing treatment on the device performance, pentacene crystal structures, and their correlations.

After the post-annealing treatment, the device mobility increased from 0.42 to 0.80 cm²V^-1sec^-1 and the device became more stable. After investigating the mechanism, the

After the post-annealing treatment, the device mobility increased from 0.42 to 0.80 cm²V^-1sec^-1 and the device became more stable. After investigating the mechanism, the

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