Chapter 2 LITERATURE REVIEW
2.3 The Thermal Annealing Treatment
Thermal annealing is a heat treatment of material, usually changing its orderings or properties. The annealing process contains heating and maintaining at a suitable temperature, and then cooling. It is hoped to improve the molecular structure and the properties of devices. Therefore, the thermal annealing effect on film orderings and the relationship between molecular structure and device properties are concerned. The thermal annealing treatment has been widely used in the fabrication of poly-Si TFTs [23-24]. Since 2002, several researches about thermal annealing effect on OTFTs and organic films have been proposed. The related literatures are summarized in Table 2.1, including device structures, annealing conditions, and device mobility.
Researches on pentacene thin film and its device performance have been concerned. In Figure 2.8, the plot of ln(μ) versus 1000/T can be fitted by the Arrhenius formula:
⎟⎠
⎜ ⎞
⎝⎛−
∝ kT
Ea
0exp μ
μ (2.16) indicating that the charge transport in devices can be described by the hole-hopping model. [27, 30]
Table 2.1 The related researches about thermal annealing treatment.
Authors Device Structure
G\insulator\semiconductor\S.D
Best Annealing Condition
Mobility cm
2/Vs
T. Komoda et al. [25] n+-Si\SiO2\pentacene\Gold 50 οC/1 hr (in vacuum) 0.2 S. J. Kang et al. [13] n+-Si\SiO2\pentacene\ Gold 90 οC/1 hr (in vacuum)* 0.49
T. Seckitani et al. [26-28] Au\Polyimide\pentacene\
Gold 140 οC/12 hr (in N2) 0.56 R. Ye et al. [12] n+-Si\SiO2\pentacene 40-120 οC/1 hr (in vacuum) / R. B. Chaabane et al. [29] Si\SiO2 + Si3N4\NiPc\Gold 100 οC/1 hr (in vacuum) 8.9×10-3 D. Guo et al. [30] n+-Si\SiO2\pentacene\ Gold 45 οC/2 hr (in vacuum) ≒0.22
* The annealing treatment is executed by “pre-annealing” in chamber after pentacene deposition.
Figure 2.8 Arrhenius plot of the logarithm mobility versus the reciprocal temperature. [30]
In ref. [12, 13, 25], both AFM images and XRD analysis showed that pentacene ordering were improved by thermal annealing. Nevertheless, the mechanism has not been explained in details. How the device performance was influenced by the thermal annealing treatment was still not well understood yet. Therefore, to understand the mechanism of the post-annealing effect on OTFTs is the most important target in this study.
Chapter 3 EXPERIMENTAL PROCESS
3.1 Device Fabrication
3.1.1 Substrate Cleaning
The substrate used in this study consists of heavily n-doped silicon wafer with 200 nm-thick thermal oxides. To remove organic contaminants, the substrates were rinsed in de-ionized water for 5 minutes, dipped in H2SO4 + H2O2 (H2SO4:H2O2=3:1, 80 οC) solution for 20 minutes, and then rinsed in de-ionized water for another 10 minutes.
Finally, the cleaned substrates were blew by dry N2 gas and dried in an oven at 120 οC for 1 hour.
Figure 3.1 The procedure of substrate cleaning. The SiO2 wafers were placed on the Teflon carrier during the cleaning process.
3.1.2 The Surface Treatment of Insulator Surface
Surface treatment on the gate insulator is one of the effective methods to control the condition of dielectric surface. The treatment has been proposed to have significant effects on the resulting thin film structure and electrical characteristics. [31] Therefore, surface treatment on the SiO2 is carried out prior to the deposition of the pentacene layer. Our SiO2 surface was modified with poly-α-methyl styrene (PαMS, Aldrich Co.) by spin-coating from toluene solutions, which can change the electronic state at the dielectric/channel interface, and improve the pentacene-based TFT performance. After spin-coating, the PαMS modified substrates were baked at 100 oC for 1 hour to remove residual solvent. The PαMS film was about 8-nm-thick, and the capacitance per unit area Ci of 200 nm-thick thermal oxides with PαMS-coating layer is 1.41 × 10-8 F/cm2 in our study.
Figure 3.2 The chemical formula of poly-α-methyl styrene (PαMS). Our SiO2 surface was modified with PαMS by spin-coating from toluene solutions.
3.1.3 Pentacene and Gold Electrode Deposition
The growth of pentacene thin film and deposition of gold electrodes were accomplished via vacuum sublimation by thermal evaporation. In the chamber, a quartz oscillator and a shutter were utilized to control the deposition rate avoiding deposition under unstable vapor flux. The deposition temperature was measured by an Al-Cr thermocouple. The pentacene source was placed in a BN-crucible and heated by a W-coil, and gold ingot was placed and heated in a W-boat.
The substrates were attached to shadow masks to define the deposited area. The 60 nm-thick pentacene (FLUKA Co., without further purification) thin-films were deposited under a working pressure below 1.6 × 10-6 Torr. During the thin film formation, the deposition rate was maintained at 0.05 nm/s, and the substrate temperature was kept at 17 oC.
Gold, as the source/drain electrode, was finally evaporated on top of the pentacene thin-film through a patterned shadow mask. The channel width (W) was 2 mm and the channel length (L) ranged from 75 to 160 μm. The device fabrication procedure is shown in Figure 3.3.
3.1.4 The Post-Annealing Treatment
To discuss the effect of post-annealing, a portion of our devices were treated by the thermal annealing process. The thermal annealing treatment was carried out at 90 oC for
80 min in a nitrogen-filled glove box. The concentrations of O2 and H2O in the glove box are both controlled bellow 1 ppm. After thermal annealing, the annealed samples are then cooled down naturally.
STEP 1
Surface modification on cleaned substrates with PαMS by spin-coating from toluene
solutions.
STEP 2
Pentacene thin film deposition through shadow mask.
STEP 3
Golden electrode deposition through shadow mask.
Device fabrication complete.
Figure 3.3 The flow chart of device fabrication. To discuss the effect of post-annealing, a portion of our devices were treated by thermal annealing process after device fabrication.
3.2 Device Measurement System
After completing the experimental process and before measuring the samples, all of our samples were conserved in the vacuum environment to avoid exposure to moisture and oxygen.
The current−voltage characteristics of this study were measured at room temperature under the atmosphere by a probe station connected with the Keithley 4200−SCS semiconductor parameter analyzer in a dark room. In the ID-VD measurement, the drain bias was swept from 0 to -45 Volts and the gate voltage step were 0, −15, −30,
−45, and −60 Volts, respectively. In the ID-VG measurement, the gate bias ranged from +10 to −60 Volts, and the drain voltage step were 0, −15, −30, −45, and −60 Volts. To investigate into the effective contact resistance, the ID−VD curve was measured by small drain bias sweeping from 0 to −1 Volts and the step at each volt of gate voltage ranging from 0 to −90 Volts.
Chapter 4 THEOREM & ANALYSIS METHOD
4.1 Morphology of Pentacene Thin Films
In our study, the crystal structure and morphology properties of pentacene thin film were investigated by using atomic force microscopy (AFM) and X-ray diffraction (XRD). In this chapter, the analysis methods of AFM images and the theorems of XRD-spectra analysis were investigated.
The characterization of the surface morphology of pentacene thin film was examined by AFM (Digital Instruments NanoScope Dimension D3100 probe microscope system). Each of our images was recorded in tapping mode in air with 1 Hz of scan rate and 256×256 dpi. To examine the post-annealing effect on pentacene grain in channel, in bulk, and in contact area, we prepared pentacene thin-film samples with different thickness: 5, 10, 20, 30, and 60 nm. The value of root-mean-square roughness (Rrms) of film was obtained by analyzing over 3×3 μm2 area using the built-in software of the AFM instrument. Figure 4.1 displays one of the surface morphology from our samples, and a Rrms of 7.599 nm is obtained. Moreover, a program of MATLAB was used to calculate the density of grain boundary. The grain boundaries defined by the
(μm)-1.
(a)
(b) Figure 4.1 (a) The Rrms of this AFM image is 7.599 nm , which was obtained by analyzing
over 3×3 μm2 area using the built-in software of the AFM. (b) The grain boundaries defined by a program of MATLAB. The detail of the program is shown in APPENDIX.
4.2 Pentacene Crystal Structure [5]
The characterization of our pentacene thin film structure was investigated by XRD, which is the direct evidence for the periodic atomic structure of crystals. The specification of XRD is M18 XHF, MacScience. The XRD measurements were performed to 60-nm thick pentacene thin films, and it was operated with Cu-Kα (λ = 1.5406 Å) radiation in a symmetric reflection, coupled θ−2θ mode. Phase identification using XRD relies mainly on the positions of the peaks in a diffraction profile and to some extent on the relative intensities of these peaks. The shapes of the peaks, however, contain additional and valuable information. The shape, particularly the width, of the peak is a measurement of the amplitude of thermal oscillations of the atoms at their regular lattice sites. It can also be a measurement of vacancy and impurity element concentrations and even plastic deformation, any factor which results in a distribution of d-spacings. In the following sections, we will discuss about how we analyze our XRD data.
4.2.1 Pentacene Phase - From Bragg’s Law
The principle of diffraction is described by Bragg’s law, which refers to the simple equation:
hkl hklsin 2d
nλ= θ (4.1) Intensity-peaks represent multiple lattice spacings (d), which can be labeled as (hkl) peaks. Each d corresponds to a specific angle (θ ). λ is the wavelength of the
incident X-ray beam, and n is an integer. A XRD-spectrum consists of the position (2θ) and the intensity of (hkl) peaks. The former implies some information about crystal structures such as size and sharp, and the latter reveals what kind of atoms are included in a film and how these atoms arrange.
One of our pentacene X-ray diffraction (λ = 1.5406 Å) spectra is shown in Figure 4.2. Five intensity-peaks represent multiple dhkl. According to the Bragg’s law, (001) peak at 5.7o corresponds to d001 with value of 15.49 Å.
5 10 15 20 25 30
(005) (004)
(001)
(002)
(003)
2 θ ( deg. )
Intensity (a. u.)
Figure 4.2 The XRD spectrum for 60-nm thick of pentacene thin films. There are five intensity-peaks, (00l), l = 1, 2, …, 5.
Similar result has been reported by C.D. Dimitrakopoulos et al. The value of d001
was found to be 15.4 Å. [4] However, the expected [32-33] single-crystal structure of pentacene in triclinic with a = 7.90 Å, b = 6.06 Å, c= 16.01 Å, α = 101.9 Å, β = 112.6
Å, and γ = 85.8 Å. In such a structure, the (001) plane spacing d001 is ∼14.5 Å.
Obviously, the result of d001 = 15.49 Å is attributed to a phase different with single crystalline phase, called “thin film phase.” The other pentacene phase with (001) peak at 6.1ο is called “bulk phase,” which is closer to the (001) peak of single crystal phase at 6.25ο. Only (00l) peaks are found in pentacene XRD-spectrum with the absence of any other (hkl) peaks, which indicates that all the pentacene crystals in the film are oriented along their (00l) planes parallel to the substrate.
4.2.2 Pentacene Crystal Size - From Scherrer Equation
[34-35]There are two ways to calculate pentacene grain size along c-axis, the Scherrer Equation and Paracrystal Theory. The crystallite size measured by the Scherrer method is given by
cosθhkl
δθ λ
hkl hkl
L = K (4.2)
Here Lhkl is the volume-weighted size, θhkl is the Bragg angle, λ is the wavelength of the X-ray, and K is unit cell geometry dependent constant whose value is typically between 0.85 and 0.99. δθ hkl is the full width of the peak at half maximum of Bragg’s peak intensity (FWHM) in radians.
4.2.3 Pentacene Crystalline - From Paracrystal Theory [36-39]
Paracrystal theory is another way used to calculate pentacene crystal size along c-axis. To use both methods to verify our results becomes reliable. From the formula of paracrystal theory,
we can obtain two important parameters, L and hkl gII, from the intercept on the ordinate axis and the slope of the straight line determined by the least-squares fitting.
Here L specifies the mean crystal size vertical to the plane (hkl), and hkl gII represents the distance fluctuation between successive planes of the family (hkl) or second kind of distortion of crystal structure.
Besides,(δs)c is the broadening associated with the size of the crystal domain, s)II
(δ stands for the broadening due to lattice distortions of the second kind, m is the order of the diffraction, and d is the mean spacing between (hkl) planes. hkl2 (δs)0 is the overall broadening excluding instrumental broadening and is further described by:
λ full width of the peak at half maximum of Bragg’s peak intensity (FWHM) in radians.
Chapter 5 RESULTS & DISCUSSION
5.1 The Effect on Pentacene Crystal
5.1.1 The Analysis of Film Morphology
Figure 5.1 (a) and 5.1 (b) show AFM images of pentacene thin films near the channel [40] for the as-prepared sample and the thermally annealed sample, respectively.
From the AFM images, we can find that the layer-by-layer of pentacene growth and the grain boundary in channel became less apparent, especially after post-annealing.
Pentacene grains seem to make better convection with each other and the grain size is slightly larger after thermal annealing. Further, the density of grain boundary reduces from 1.35 (μm)-1 to 1.16 (μm)-1 after thermal annealing, that is 14 % decrease. Since it has been reported that grain boundaries limit the charge transport in thin organic films, we can presume that the annealed device with less grain boundaries exhibits better electrical properties than the un-annealed one. [19]
(a) (b) Figure 5.1 5-nm pentacene thin films for (a) as-prepared and (b) thermally annealed
samples.
Figure 5.2 (a)-(f) are the images of pentacene thin films with different thicknesses and annealing condition. From the AFM images, it seems reasonable that the grain size only grows slightly, because the grain size of pentacene is dominated by the nucleation sites on substrate [41] and interaction/aggregation forces between pentacene/substrate molecules. [42] Thermal annealing treatment will not influence the number of nucleation sites.
From Figure 5.2 (e) and (f), the Rrms values calculated by the built-in software of AFM instrument showed that the film morphology are decreased after the thermal annealing treatment. It is well known that the rougher the surface is, the larger contact area becomes. Therefore, the contact area of pentacene/gold interface should be reduced after the thermal annealing treatment.
(a) (b)
(c) (d)
(e) (f)
Figure 5.2 20-nm Pentacene thin films (a) as-prepared, (b) after thermal annealing.
30-nm thick samples (c) as-prepared, (d) after thermal annealing. 60-nm thick samples (e) as-prepared, and (f) after thermal annealing.
5.1.2 The Analysis of XRD spectra
XRD was carried out to study the crystal structure of the pentacene thin films, as shown in Figure 5.3. As discussed in Chapter 4, there are five intensity peaks and only (00l, l = 1,2,…5) peaks are found, indicating that all the pentacene crystals in the film are oriented along their (00l) planes parallel to the substrate. Whether the thermal annealing treatment was performed or not, only thin-film phase was observed in the spectra. This result reveals that the change of device performance is independent of the pentacene phase transition. After thermal annealing, the Bragg’s peak intensity was significantly boosted, which implies the fact that thermal annealing treatment indeed improves the pentacene molecular ordering. The similar results have been proposed in reference [12].
Table 5.1 specifies the XRD parameters deduced from Equations (4.2), (4.3), and (4.4). Combined Equation (4.3) and (4.4), the following equation is obtained:
4
By Substituting θhkl and FWHM of each Bragg’s peak in Figure 5.3 into Equation (5.1), a plot of (δs)02 versus the fourth power of the diffraction order m4 (Figure 5.4) can be obtained. By linear fitting, L and ghkl II can be obtained from the intercept and slope of Equation (5.1), respectively. Both Scherrer Equation and Paracrystal Theory showed that the mean crystal size vertical to substrate is decreased after thermal annealing. The values of gII below 2 % indicate that the structural perfection of pentacene crystalline is high [5]. After the thermal annealing treatment, the second kind of lattice distortion became more serious (increasing from 1.3 to 1.7 %).
5 10 15 20 25 30
Figure 5.3 The XRD spectra obtained from 60 nm-thick pentacene films. The inset shows the XPS spectrum near (002) intensity peak.
200 400 600 intercept and slope of this plot, we can obtain the mean crystal size vertical to substrate and second kind of distortion of crystal structure.
Table 5.1 The analysis of XRD spectra.*
Condition Intensity FWHM (deg.)
L
hkl(nm)
Lhkl
(nm)
g
II(
%)
As prepared 575 0.136 58.0 33.0 1.3
With treatment 4333 0.229 34.5 20.5 1.7
* Lhkl is calculated from Scherrer Equation. Lhkl and gII are evaluated from Paracrystal Theory.
5.2 The Effect on Device Property
5.2.1 Electrical Characteristics
In the beginning, we tried the annealing condition for different annealing temperature at 60, 90, and 120 οC for 80 min. The key results were listed in Table 5.2.
We found that annealing at 90 οC gave to better device performance.
Table 5.2 The device performance*
Annealing Condition
μsat
(cm
2/Vs)
V
T(V)
I
on/I
offAs prepared 0.42 -17.4 3×106
Annealing at 60 oC 0.54 -17.9 7×106
Annealing at 90 oC 0.80 -19.1 2×107
Annealing at 120 oC 0.49 -21.2 6×106
* The device performance of pentacene-based TFT at different annealing temperature: room temperature (without annealing), 60, 90, and 120 oC, respectively.
However, while the temperature is higher than 120 oC, the device performance degrades. Since, the best device performance was achieved at 90 oC in our experiment, so that the condition of annealing treatment was set to be at 90 oC for 80 min in the following discussions.
First, we focused on the post-annealing effect on the device performance. The resulting characteristics were presented in Figures 5.5, which exhibits the common TFT behavior as described in Chapter 2. The influence of the post-annealing treatment can be seen clearly. The drain current (ID) was dramatically increased after the post-annealing treatment. The log|ID|−VGS characteristics provide some information about the post-annealing effect. First, the Ion/Ioff was increased by almost one order after post-annealing. The S.S. also decreased from 2.5 V/decade to 1.4 V/decade, and the VT
shifted from −17.4 to −19.1 V. From the (ID)1/2-VGS characteristic, it was found that the device mobility increased from 0.42 to 0.80 cm2V-1sec-1 in the saturation regime for VDS
= −60 V. Obviously, the device performance has been improved by the thermal annealing treatment.
0 -10 -20 -30 -40 -50 Figure 5.5 The current-voltage characteristics of pentacene-based TFT with anneal/
un-annealed condition. (a) The drain current ID versus the drain-source voltage VDS at VGS
= −60 V and (b) the absolute value of the drain current and the logarithmic drain current versus the gate-source voltage VGS at VDS = −60 V. The post-annealing treatment was carried out at 90 oC for 80 min in a N2-filled glove box.
5.2.2 Resistance Analysis
The device performance can be significantly improved, as mentioned above. In order to clarify the underlying mechanism, the device resistance was further investigated. Figure 5.6 shows a simplified equivalent OTFT circuit where the conducting path is divided into three parts of resistance, rch, rC, and rbulk.
As shown in Figure 5.7 (a), it is obviously observed that the channel resistance was significantly reduced after post-annealing.Accordingly, we can presume that a number of defects in the pentacene grain boundary in the channel were removed after the thermal annealing treatment. This improvement probably can be explained by the reduced number of defects existing in the grain boundary in the channel regime. The rbulk and rC were estimated by the method published by M. Shur in 1990. The concepts of M. Shur’s theorem have been discussed in Chapter 2. According to this method, rC
and rbulk can be discussed individually, and the equivalent circuit is shown in Figure 5.7(b).
Figure 5.6 The simplified equivalent OTFT circuit, where the conducting path is divided into three parts of resistance, rch, rC, and rbulk.
-20 -40 -60 -80 10M
20M
30M as-prepared
with annealing treatment
Channel resistance
(
Ω/μm)
Gate Voltage (V)
(a)
-20 -40 -60 -80
0 3 6
9 as-prepared
with annealing treatment
Eff ect series r esistance (
Ωcm
2)
Gate Voltage (V)
(b) Figure 5.7 Resistance characteristics of pentacene-based TFT with/without the annealing
treatment. (a) the channel resistance versus gate voltage VGS and (b) the effective series resistance versus VGS. In our assumption, effective contact resistance rC is VGS independent and effective bulk resistance rbulk is variable with VGS. The effective series resistance is equal to the sum of rC and rbulk.
To simplify our problem, rC was assumed to be independent of VGS, and therefore rbulk is a function of VGS. Taking this assumption into consideration, rbulk can be negligible as compared to rC at high VGS. The values of rC for the untreated and the thermally annealed devices are 0.003 and 0.235 Ω-cm2, respectively. In addition, the influence of rbulk is extremely large than rC at low VGS. After post-annealing, both rC
and rbulk increase, which are harmful to device performance. Combining the change of pentacene crystals and that of device performance, it is believed that the increased rC is attributed to the reduced pentacene surface roughness. Since the contact area of pentacene/gold interface is reduced after post-annealing. Further, the increased rbulk is due to the more serious lattice distortion which does not facilitate the carrier transport in pentacene.
As shown in Table 5.3, although both of rC and rbulk increased, rch decreased. For our devices, the channel lengths range form 75 to 160 μm. The decreased amount of rch
is much more than the increased sum of rC and rbulk. Therefore, the total resistance of pentacene-based TFTs is decreased after post-annealing treatment. However, it must be noticed that the reduced degree of rch is much smaller than the increased degree of μsat.
Accordingly, some other factors are expected to influence the device performance. The DC stress degradation on the OTFT devices was subsequently performed.