Device Selection and Output Stage Design

In order to achieve the overall target Psat of 15 dBm and have reasonable gain at the output stage, four-way transformer-based power combining is adopted at the output stage. As discussed in section 4.1, current-combining configuration is chosen since symmetric characteristic of the combiner is especially critical for PA designs with multi-way combining at such high frequencies.

Fig. 4.5 shows the schematic of the output stage with the four-way transformer-based power combiner [48]. The output stage consists of four differential pairs, each of which consists of two common-source (CS) amplifier cells and cross-coupled neutralization capacitors. The Psat of a single CS amplifier cell can be estimated using the load-line theory as

max min max combiner. Thus, a Psat ≥ 8 dBm from each of the eight CS amplifier cells is required to achieve the overall target Psat of 15 dBm. Fig. 4.6 shows the DC-IV curves of the device with gate-periphery of 32f x 1μm. From (4.11), Psat of around 8.5 dBm can be estimated at VDS = 1.2 V, which provides enough margin for the 8 dBm target. Fig. 4.7 shows the gm and IDS of the 32f x 1 μm device versus VGS at VDS = 1.2 V . The device reaches peak gm at VGS = 0.8V, and therefore the bias condition is set to [VGS, VDS] = [0.8 V, 1.2 V].

Different configurations of a total 32-μm gate-periphery is then compared at the selected bias condition of [VGS, VDS] = [0.8V, 1.2V]. As can be seen in Fig. 4.8, the simulated MSG/MAG of two parallel-combined 16f x 1 μm devices is higher than a single 32f x 1 μm device. The parasitic capacitance is effectively reduced by splitting a single into two parallel-combined devices with half of the gate-peripheries, which leads to a higher MSG/MAG. Despite the benefit of a higher gain, further splitting of the devices leads to larger and more complicated physical layout. Therefore, the two parallel-combined 16f x 1 μm devices is used as the configuration for the eight CS amplifier

cells of the output stage.

Fig. 4.6. Simulated DC-IV curves of the device with gate-periphery of 32f x 1 μm.

Fig. 4.7. Simulated g_m and I_DS of the 32f x 1 μm device versus V_GS at V_DS = 1.2 V.

Fig. 4.9 shows the circuit schematic of the differential pair used at the output stage. Two cross-coupled capacitances CN are adopted for the neutralization technique. Fig. 4.10 shows the simulated MSG/MAG and stability factor of the differential pair at 110 GHz versus different values of CN. The differential pair reaches maximum gain increase at CN = 13.5 fF, and is most stable at CN

= 10 fF. Considering a potential  20% variation of capacitance during fabrication, CN of 12 fF is Fig. 4.8. Simulated MSG/MAG and stability factor of a single 32f x 1 μm device compared with two parallel-combined 16f x 1 μm devices.

Fig. 4.9. Schematic of the output stage differential pair with four 16f x 1 μm devices.

chosen for added stability and 2 dB of gain improvement at 110 GHz. Multi-digit capacitors consisting of metal-7, 8, and 9 layers are used for the requirements of both a small 12 fF capacitance and a compact layout footprint. Since the physical layout of the differential pair around the devices is rather compact and complicated, results from the pre- and post-EM simulations may differ significantly. To avoid the time-consuming process of redesigning, EM simulations of the differential pair are performed before starting the design of matching networks. Fig. 4.11 shows the post-EM simulated MSG/MAG and stability factor of the differential pair. By adopting the neutralization technique, increase in stability and in the MSG/MAG at 110 GHz by 2 dB is achieved.

The optimum load impedance Zopt3,diff for Psat performance can be obtained through load-pull simulation. Fig. 4.12 shows the power contours of the post-EM simulated differential pair. The differential pair achieves Psat of 11.5 dBm and PAE of 26.04% with optimum load impedance Zopt3,diff = 24.23 + j39.85 Ω at 110 GHz.

Fig. 4.10. Simulated MSG/MAG and stability factor of the output differential pair at 110 GHz versus different values of CN.

As can be seen in Fig. 4.5, each differential pair is followed by a differential-to-single transformer to form the four-way power combining structure. Symmetrical 50-Ω micro-strip lines are used for in-phase power combining of the four transformers before connecting to the output

Fig. 4.11. Post-EM simulated MSG/MAG and stability factor of the output differential pair.

Fig. 4.12. Post-EM simulated power contours of the output differential pair.

through another 50-Ω micro-strip line. As previously reported in [48], the radial-symmetric configuration minimize the length and therefore the insertion loss of the micro-strip lines used for power combining during physical layout. This also result in the transfer of load impedance at the output, i.e., ZL = 50 Ω, to 4 x 50 Ω seen by the transformers looking towards the output. To transfer 200 Ω to Zopt3,diff with the lower impedance transformation ratio of the current-combining configuration, transformers with 1:2 turn ratio and high coupling coefficients are required.

Fig. 4.14. Post-EM simulated parameters of the output transformer TFout.

Fig. 4.13. 3-D rendering of the output transformer TFout used for EM simulation.

Fig. 4.13 shows the 3-D rendering of the output transformer TFout used for EM simulation. The transformer is realized using the metal-9 layer (top layer, 3.4-μm thick) for the primary coil, and metal-8 layer (0.9-μm thick) for the secondary coil in order to minimize the insertion loss. The ground plane (metal-1) underneath the transformer is removed to prevent undesired coupling of field. Fig. 4.14 shows the post-EM simulated parameters of TFout. The 1:2 turn ratio enable an inductance ratio r = Ls/Lp greater than 3 at 110 GHz. Together with a coupling coefficient of 0.66 at 110 GHz, the transformer design mitigates the low impedance ratio of the current-combining configuration. Since the center of the transformer primary coil is a virtual ground in differential mode, it also serves as bias-feeding point for drain voltage of the output stage devices (VD,output).

Center-tap shunt capacitors are adopted at the bias-feeding point to enforce the AC ground. This mitigates the phase and amplitude imbalances of the transformer, and suppresses any undesired common-mode signal. The adoption of center-tap capacitors are especially beneficial in inherently asymmetric transformer configurations such as differential-to-single or single-to-differential.

Fig. 4.15. Post-EM simulated S-parameters of the four-way transformer-based power combiner.

Fig. 4.15 shows the post-EM simulated S-parameters of the four-way transformer-based power combiner. The combiner has insertion loss within 1.7 to 2 dB across 100 to 120-GHz, with the minimum loss of 1.7 dB at 110 GHz. In/output return loss larger than 10 dB indicates decent impedance matching across 100 to 120 GHz. Post-EM simulations of the output stage complete with the transformer-based power combiner are performed with ideal input conjugate termination.

Fig. 4.16 and 4.17 shows the simulated S-parameters and large-signal performances at 110 GHz, respectively. The output stage has over 5 dB of gain across 90 to 120 GHz, with gain of 7.7 dB at 110 GHz and peak gain of 8 dB at 106 GHz. With Psat of 15.4 dBm, PAEpeak of 14.8%, and OP1dB of 12.8 dBm at 110 GHz, the output stage meets the target large-signal performance. Fig. 4.18 shows the simulated large-signal performances versus frequency. The output stage has Psat above 14.9 dBm, PAEpeak above 13.2%, and OP1dB above 12.8 dBm from 96 to 114 GHz. This indicates a wideband matching to the device optimal impedance provided by the transformer-based power combiner.

Fig. 4.16. Simulated S-parameters of the output stage complete with the four-way transformer-based power combiner.

Fig. 4.17. Simulated large-signal performance at 110 GHz of the output stage complete with the four-way transformer-based power combiner.

Fig. 4.18. Simulated large-signal performances versus frequency of the output stage complete with the four-way transformer-based power combiner.