Modulation Measurements

For modulation measurements, all RF in/output and baseband data inputs were performed using on-wafer probing. Dice were mounted on PCB boards with bond-wiring for DC applications (VG1 and VDD). RF (carrier) input was generated using an Agilent E8257D analog signal generator.

Baseband data input in the form of pseudo-random binary sequence (PRBS) data at various data rates was generated using an Anritsu MP1800A signal quality analyzer. The Vp-p of the baseband data signal was set to 0 to VG2,on, i.e., 0 to 1.8 V.

Fig. 3.59 shows the setup for modulation measurements in frequency-domain. The output spectrum was monitored using an Agilent E4448A spectrum analyzer with an Agilent 11974V mixer (50 to 75 GHz). Fig. 3.60 to 3.63 shows the measured output spectrum at various data rates.

As can be seen, the first nulls appear at [data rate]-GHz from the 60 GHz carrier frequency, which indicates a successful modulation of the carrier signal.

Fig. 3.64 shows the setup for modulation measurements in time-domain. The output time-domain waveform was monitored using a Keysight DSAZ334A oscilloscope (with 50-GHz update). Note that due to the frequency limitation of the oscilloscope, carrier frequency of 50 GHz was used instead of 60 GHz for measurements in time-domain. Fig. 3.65 to 3.68 show the output waveform in the form of PRBS data at various data rates.

Fig. 3.59. Setup for modulation measurements in frequency-domain.

Fig. 3.60. Measured output spectrum of the modulated signal at data rate of 4.5 Gb/s.

Fig. 3.61. Measured output spectrum of the modulated signal at data rate of 6 Gb/s.

Fig. 3.62. Measured output spectrum of the modulated signal at data rate of 8 Gb/s.

Fig. 3.63. Measured output spectrum of the modulated signal at data rate of 10 Gb/s.

Fig. 3.64. Setup for modulation measurements in time-domain.

Fig. 3.65. Measured output waveform of the modulated signal at data rate of 4.5 Gb/s.

Fig. 3.66. Measured output waveform of the modulated signal at data rate of 6 Gb/s.

Fig. 3.67. Measured output waveform of the modulated signal at data rate of 8 Gb/s.

Fig. 3.68. Measured output waveform of the modulated signal at data rate of 10 Gb/s.

3.5 Summary

In this chapter, a 60-GHz OOK modulator of the switching-amplifier configuration is proposed.

By combining the functions of modulation and output amplification in a single circuit, a transmitter of lower complexity and higher efficiency can be achieved. The proposed modulator is based on a cascode circuit, in which modulation is performed by switching the common-gate device on/off. A cascode-based transformer-feedback technique is proposed for improvements in output power, gain performances at on-state, and isolation performance at off-state.

The proposed transformer feedback consists of a shunt inductor between the devices, and a series inductor at the gate of the common-gate device. At on-state, the effective inductances of the transformer eliminates the undesired effects caused by the parasitic capacitance of the devices. At off-state, coupling of the transformer enables the cancelation of the leakage signal by introducing a signal of similar magnitude and 180 ° phase difference. This results in improvements in performances at both on- and off-states. The transformer feedback technique has further benefits besides improvements in circuit performances. Compact physical layout of the proposed modulator can be achieved due to the small footprint of the transformer. A small core area of 261 x 469 μm² without RF and DC pads is possible for future applications in OOK transmitter designs.

Furthermore, the transformer feedback brings the improvements at on- and off-states while requiring only a single baseband data input. This results in a lower requirement in baseband circuit components, and in turn a transmitter of lower complexity and power consumption.

While the modulator design is based on a high gate-bias of VG2,on = 1.8 V for optimum on-state performances, the proposed modulator maintains decent gain and on-off isolation performances with lower output power and efficiency under lower VG2,on. Therefore, applications requiring lower Vp-p of the baseband data signal or lower power consumptions can also be supported, with the tradeoff of a shorter transmission distance.

For modulation, an inductor with a shunt capacitor is adopted for the baseband data input to provide isolation to the RF (carrier) frequencies instead of a large resistor. This effectively lowers the time-constant (τ) seen by the baseband data signal, and enables the modulator to achieve a maximum 10 Gb/s data rate.

As mentioned in section 2.1, the ratio Eb/N0 between the average bit energy and the noise power spectral density directly translates to the SNR under binary modulations such as OOK, and is crucial to the bit-error-rate at the receiver end. Higher SNR at the receiver end can be achieved by increasing either the output power, or on-off isolation of the transmitter. Table 3.4 compares the proposed modulator with previous reported 60-GHz OOK modulators in CMOS processes. The propose modulator achieves the highest OP1dB among the reported works, and has significant advantage in on-off performance compared to the works with OP1dB greater than 0 dBm. On the other hand, the proposed modulator also has significant advantage in OP1dB level over reported works with on-off isolation greater than 30 dB. Therefore, the proposed modulator proves to have state-of-the-art performance in terms of SNR, and greatly reduce the burden on the receiver to achieve a high bit-error rate. With a strong performance of maximum 10-Gb/s data rate, the proposed modulator achieves a state-of-the-art performance all-round.

Table 3.4. Previously Reported OOK Modulator Designs in CMOS processes.

^ chip area with RF, DC pads, and the embedded VCO included

Chapter 4 A Study on Common-mode stability of Millimeter-wave Power Amplifiers using a W-band Design in 65-nm CMOS Process

In this chapter, a W-band power amplifier (PA) with transformer-based impedance matching and power combining designed and realized in 65-nm CMOS process is presented. A transformer-based radial-symmetric power combining structure is adopted at the output for low insertion loss and matching imbalances, which are critical in PA designs at such high frequencies.

Common-mode instabilities were observed and analyzed after the first tape-out. Modifications to the transformers are proposed to eliminate the common-mode instabilities, without altering the matching conditions in differential mode. The modifications proved successful in the second tape-out. Modeling issue of high frequency transformer designs is also discussed.

4.1 Introduction

Wireless communications in millimeter-wave frequencies gain many interests in recent years due to the large available bandwidth and therefore higher data rates [39]-[47], [50]. At the high frequencies of W-band, the short wavelength also provides potentials for imaging applications in area such as bio-medical research. Furthermore, wireless systems designed at W-band benefit from having smaller circuit footprints and antenna sizes. However, the low fmax/fT of CMOS technologies is often the limiting factor of gain and output power performances in W-band transceiver designs.

4.1.1 Transformer-based Power Combining

Advanced nanoscale technologies such as 28, 40, and 65-nm CMOS processes has advantages of higher gain and fmax/fT, which are especially critical in amplifier designs at millimeter-wave frequencies. However, shorter gate-lengths lead to lower breakdown voltages, which in turn limit the supply voltage. This poses challenges to PA designs in achieving high levels of output power.

Power combining is widely used for increasing the output power under low supply voltages [47]-[50]. Due to the short wavelength at millimeter-wave frequencies, the phase difference

between combining paths becomes highly sensitive to any physical asymmetry of the power combining structure. Phase difference between combining paths degrades the combined power, and therefore the amplifier efficiency. Fig. 4.1 shows two commonly used structure for in-phase power combining in millimeter-wave PA designs. In Fig. 4.1(a), binary power combining uses transmission lines for the purposes of both in-phase power combining and impedance matching. A wideband performance can often be achieved with careful design of the transmission lines [44]-[46], [50]. However, a large transformation ratio between the optimal impedance of the devices and the load impedance leads to longer transmission lines, and therefore higher insertion losses.

Furthermore, transmission lines often take up large layout footprint, even at millimeter-wave frequencies. In Fig. 4.1(b), transformer-based power combining has stood out in millimeter-wave PA designs recently [39], [48]-[49]. Transformers also serves the purposes of both in-phase power combining and impedance matching, but in a much more compact layout footprint than transmission lines. Since a large impedance transformation ratio does not necessarily translate to a large insertion loss of the transformer, the technique is especially suited for multi-way, high output power PA designs.

Fig. 4.1. Commonly used power combining structures: (a) binary power combining (b) transformer-based power combining.

(a) (b)

Fig. 4.2 shows two different configurations of transformer-based power combining, in which power is combined through voltage- and current-combining, respectively. In Fig. 4.2(a), the voltage is combined by cascading the secondary coils of the transformers. The output voltage and current are given by

out 1 2 N

V    V V V  N rV , (4.1)

and

out

I 1I

r , (4.2)

in which N denotes the number of combining, V denotes the voltage across each of the primary coils, I denotes the current through each of the primary coils, and r denotes the inductance ratio between

Fig. 4.2. Schematics of (a) voltage-combining configuration, and (b) current-combining configuration of transformer-based power combining.

(a) (b)

the secondary and primary coils. From (4.1) and (4.2), in order to transform the load impedance RL output voltage and current are given by

Vout rV , (4.5) impedance Ropt of the device, the required impedance transformation ratio is given by

2 impedance transformation ratio for multi-way, i.e., N ≥ 2, power combining. Transformers with turn ratios of 1:1 often meets the requirement of impedance transformation. On the other hand,

transformers with r > 1 and often turn ratios of 2:1 are required if the current-combing configuration is to be used for multi-way power combining. This leads to more complexity and potentially more insertion loss in the transformer design.

Fig. 4.3 shows the two configurations of transformer-based power combining with the shunt parasitic capacitances from the transformers considered. In the case of single-ended output, cascading of the transformer secondary coils in the voltage-combining configuration leads to a single current path at the output. With the shunt parasitic capacitances from the transformers, this leads to different impact from the leakage currents on each of the combining paths,

1 1 2 2 1 1

out C C C N CN C

I  I I  I I I I I  I . (4.9) On the other hand, current is distributed evenly among the combining paths in the Fig. 4.3. Schematics of (a) voltage-combining configuration, and (b) current-combining configuration of transformer-based power combining, with the parasitic capacitances considered.

(a) (b)

current-combining configuration. Therefore, while the leakage currents from the parasitic capacitances are still present, the symmetric nature of the configuration means the impacts on each of the combining paths are the same,

Therefore, the impedance seen by each of the differential PA cells suffer greater imbalances in the voltage-combining configuration. The imbalance leads to different impedances seen by each differential PA cells and degrades the efficiency of power combining, which in turn degrades the output power and power-added-efficiency (PAE) performances of the overall PA. As the frequency and the number of combining paths increases, the effect of imbalance becomes more prominent.

Thus, the current-combining configuration is more suited for multi-way PA designs at millimeter-wave frequencies. However, the low impedance transformation ratio is a tradeoff to be considered when adopting the current-combining configuration.

4.2 Circuit Design

The proposed W-band PA is targeted at saturated output power (Psat) of 15 dBm at 110 GHz.

To reach the target output power at W-band, multi-way power combining is required at the output.

4.2.1 Neutralization Technique

In PA designs, devices with relatively large gate-periphery are often used to achieve higher output power levels. However, the intrinsic gate-to-drain capacitance Cgd also increases with the device gate-periphery. A larger Cgd leads to worse reverse isolation of the device, which in turn degrades both gain and stability. Furthermore, the PAE of PA designs will suffer from poor gain performance of the output stage. As PA designs enter millimeter-wave frequencies, the effect of Cgd

becomes more prominent.

Neutralization technique cancels the effect of intrinsic Cgd by introducing an equivalent negative capacitance –CN [51]. As shown in Fig. 4.4, the technique can be implemented using

cross-coupled capacitors between the gate and drain of two devices in differential mode to eliminate the effect of Cgd. In addition to increased gain and stability, another benefit of adopting neutralization is that it makes little difference on the impedances for optimal large-signal performance of the devices. Therefore, the design of impedance matching networks will not be more complicated because of adopting the neutralization technique.

Fig. 4.4. Schematic of neutralization technique implementation in differential mode with cross-coupled capacitors between device gate and drain.

Fig. 4.5. Schematic of the output stage complete with the four-way transformer-based power combiner.

4.2.2 Device Selection and Output Stage Design

In order to achieve the overall target Psat of 15 dBm and have reasonable gain at the output stage, four-way transformer-based power combining is adopted at the output stage. As discussed in section 4.1, current-combining configuration is chosen since symmetric characteristic of the combiner is especially critical for PA designs with multi-way combining at such high frequencies.

Fig. 4.5 shows the schematic of the output stage with the four-way transformer-based power combiner [48]. The output stage consists of four differential pairs, each of which consists of two common-source (CS) amplifier cells and cross-coupled neutralization capacitors. The Psat of a single CS amplifier cell can be estimated using the load-line theory as

max min max combiner. Thus, a Psat ≥ 8 dBm from each of the eight CS amplifier cells is required to achieve the overall target Psat of 15 dBm. Fig. 4.6 shows the DC-IV curves of the device with gate-periphery of 32f x 1μm. From (4.11), Psat of around 8.5 dBm can be estimated at VDS = 1.2 V, which provides enough margin for the 8 dBm target. Fig. 4.7 shows the gm and IDS of the 32f x 1 μm device versus VGS at VDS = 1.2 V . The device reaches peak gm at VGS = 0.8V, and therefore the bias condition is set to [VGS, VDS] = [0.8 V, 1.2 V].

Different configurations of a total 32-μm gate-periphery is then compared at the selected bias condition of [VGS, VDS] = [0.8V, 1.2V]. As can be seen in Fig. 4.8, the simulated MSG/MAG of two parallel-combined 16f x 1 μm devices is higher than a single 32f x 1 μm device. The parasitic capacitance is effectively reduced by splitting a single into two parallel-combined devices with half of the gate-peripheries, which leads to a higher MSG/MAG. Despite the benefit of a higher gain, further splitting of the devices leads to larger and more complicated physical layout. Therefore, the two parallel-combined 16f x 1 μm devices is used as the configuration for the eight CS amplifier

cells of the output stage.

Fig. 4.6. Simulated DC-IV curves of the device with gate-periphery of 32f x 1 μm.

Fig. 4.7. Simulated g_m and I_DS of the 32f x 1 μm device versus V_GS at V_DS = 1.2 V.

Fig. 4.9 shows the circuit schematic of the differential pair used at the output stage. Two cross-coupled capacitances CN are adopted for the neutralization technique. Fig. 4.10 shows the simulated MSG/MAG and stability factor of the differential pair at 110 GHz versus different values of CN. The differential pair reaches maximum gain increase at CN = 13.5 fF, and is most stable at CN

= 10 fF. Considering a potential  20% variation of capacitance during fabrication, CN of 12 fF is Fig. 4.8. Simulated MSG/MAG and stability factor of a single 32f x 1 μm device compared with two parallel-combined 16f x 1 μm devices.

Fig. 4.9. Schematic of the output stage differential pair with four 16f x 1 μm devices.

chosen for added stability and 2 dB of gain improvement at 110 GHz. Multi-digit capacitors consisting of metal-7, 8, and 9 layers are used for the requirements of both a small 12 fF capacitance and a compact layout footprint. Since the physical layout of the differential pair around the devices is rather compact and complicated, results from the pre- and post-EM simulations may differ significantly. To avoid the time-consuming process of redesigning, EM simulations of the differential pair are performed before starting the design of matching networks. Fig. 4.11 shows the post-EM simulated MSG/MAG and stability factor of the differential pair. By adopting the neutralization technique, increase in stability and in the MSG/MAG at 110 GHz by 2 dB is achieved.

The optimum load impedance Zopt3,diff for Psat performance can be obtained through load-pull simulation. Fig. 4.12 shows the power contours of the post-EM simulated differential pair. The differential pair achieves Psat of 11.5 dBm and PAE of 26.04% with optimum load impedance Zopt3,diff = 24.23 + j39.85 Ω at 110 GHz.

Fig. 4.10. Simulated MSG/MAG and stability factor of the output differential pair at 110 GHz versus different values of CN.

As can be seen in Fig. 4.5, each differential pair is followed by a differential-to-single transformer to form the four-way power combining structure. Symmetrical 50-Ω micro-strip lines are used for in-phase power combining of the four transformers before connecting to the output

Fig. 4.11. Post-EM simulated MSG/MAG and stability factor of the output differential pair.

Fig. 4.12. Post-EM simulated power contours of the output differential pair.

through another 50-Ω micro-strip line. As previously reported in [48], the radial-symmetric configuration minimize the length and therefore the insertion loss of the micro-strip lines used for power combining during physical layout. This also result in the transfer of load impedance at the output, i.e., ZL = 50 Ω, to 4 x 50 Ω seen by the transformers looking towards the output. To transfer 200 Ω to Zopt3,diff with the lower impedance transformation ratio of the current-combining configuration, transformers with 1:2 turn ratio and high coupling coefficients are required.

Fig. 4.14. Post-EM simulated parameters of the output transformer TFout.

Fig. 4.13. 3-D rendering of the output transformer TFout used for EM simulation.

Fig. 4.13 shows the 3-D rendering of the output transformer TFout used for EM simulation. The transformer is realized using the metal-9 layer (top layer, 3.4-μm thick) for the primary coil, and metal-8 layer (0.9-μm thick) for the secondary coil in order to minimize the insertion loss. The ground plane (metal-1) underneath the transformer is removed to prevent undesired coupling of field. Fig. 4.14 shows the post-EM simulated parameters of TFout. The 1:2 turn ratio enable an inductance ratio r = Ls/Lp greater than 3 at 110 GHz. Together with a coupling coefficient of 0.66 at 110 GHz, the transformer design mitigates the low impedance ratio of the current-combining configuration. Since the center of the transformer primary coil is a virtual ground in differential mode, it also serves as bias-feeding point for drain voltage of the output stage devices (VD,output).

Center-tap shunt capacitors are adopted at the bias-feeding point to enforce the AC ground. This mitigates the phase and amplitude imbalances of the transformer, and suppresses any undesired common-mode signal. The adoption of center-tap capacitors are especially beneficial in inherently asymmetric transformer configurations such as differential-to-single or single-to-differential.

Fig. 4.15. Post-EM simulated S-parameters of the four-way transformer-based power combiner.

Fig. 4.15 shows the post-EM simulated S-parameters of the four-way transformer-based power combiner. The combiner has insertion loss within 1.7 to 2 dB across 100 to 120-GHz, with the minimum loss of 1.7 dB at 110 GHz. In/output return loss larger than 10 dB indicates decent impedance matching across 100 to 120 GHz. Post-EM simulations of the output stage complete

Fig. 4.15 shows the post-EM simulated S-parameters of the four-way transformer-based power combiner. The combiner has insertion loss within 1.7 to 2 dB across 100 to 120-GHz, with the minimum loss of 1.7 dB at 110 GHz. In/output return loss larger than 10 dB indicates decent impedance matching across 100 to 120 GHz. Post-EM simulations of the output stage complete