EM Simulation

The physical layout around the devices of a cascode circuit often limits the possibility of including all the passive elements into a single run of EM simulation. However, since the proposed modulator requires relatively complicated physical layout around the devices including the feedback

transformer, we manage to consider as much elements in a single run of EM simulation for accurate modeling of the passive elements. Fig. 3.23 shows the 3-D rendering of the area around the devices used for EM simulation, as indicated by the grey area in the schematic.

3.3.5 Simulation Results

Fig. 3.24 and Fig. 3.25 shows the post-EM simulated S-parameters of the proposed 60-GHz modulator at on- and off-states, respectively. At on-state, the modulator shows a 14 GHz 3-dB bandwidth from 52 to 66 GHz, and gain of 8.8 dB at 60 GHz. Both in- and output return losses are above 10dB from 57 to 63 GHz. Input return loss performance is slightly better than output, which is to be expected in PA designs. At off-state, the modulator shows isolation above 35 dB across 40 to 80 GHz, and isolation of 36 dB at 60 GHz. Both in- and output return losses are similar to that at on-state, with output return loss decreased slightly below 10 dB at 60 GHz. Similar behavior in in/output return loss between on- and off-states ensures the stability within the transmitter at either state of data transmission. From the on- and off-state performances, the modulator shows an on-off isolation of 44.8 dB at 60 GHz.

Fig. 3.23. 3-D rendering of the area around the devices used for EM simulation.

Feedback TF

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Fig. 3.24. Simulated S-parameters of the proposed modulator at on-state.

Fig. 3.25. Simulated S-parameters of the proposed modulator at off-state.

Fig. 3.26 shows the post-EM simulated large-signal performances at on-state at 60 GHz. The modulator shows an OP1dB of 6.2 dBm, Psat of 8.4 dBm, and peak power-added-efficiency (PAE) of 14.2% at 60 GHz. Fig. 3.27 shows the post-EM simulated large-signal performances at on-state versus frequency. Across 56 to 64 GHz, the modulator shows OP1dB above 5.8 dBm, Psat above 7.8 dBm, and peak PAE above 12.2%. Furthermore, OP1dB performance is above 5.5 dBm across 52 to 66 GHz.

Fig. 3.28 shows the post-EM simulated large-signal performances at off-state at 60 GHz. As can be seen, the isolation performance only degrades slightly at higher Pin levels. The modulator shows isolation > 35dB for Pin < 0 dBm, and isolation > 30 dB for Pin < 5 dBm. Compared with the on-state performances shown in Fig. 3.26, this means that the modulator can be driven at high Pin

levels for output power performances at on-state, with little compromise in isolation performance at off-state.

Fig. 3.29 shows the post-EM simulated stability factor of the modulator. Stability factor above 1 across the frequencies indicates a stable design. Fig. 3.30 shows the post-EM simulated drain current (IDD) and power consumption (PDC) at on-state versus Pin, in which PDC = VDD x IDD = 2V x IDD. The drain current and power consumption is around 17 mA and 34 mW across different Pin

levels, respectively.

For modulation simulations, the Pin level at 60 GHz is set to -1 dBm, around the IP1dB point at on-state. Fig. 3.31(a) to 3.34(a) shows the post-EM simulated output spectrum of the modulated signal. As mention in the introduction, the power spectral density of OOK modulation is a sinc function centered at the carrier frequency with main lobe width of 2Tb, in which Tb denotes the bit period. As shown in the figures, the first nulls appear at [data rate]-GHz away from the 60 GHz carrier frequency at different data rates, indicating a successful modulation. Fig. 3.31(b) to 3.34(b) shows the post-EM simulated output waveform of the modulated signal. Data sequence of “1010” is used during simulation for demonstration purposes. We also include the output waveform of the

modulator at on- and off-states in the figures. As can be seen, the modulated signal of a single bit, i.e., the shortest response time for data transition, can reach the output magnitude at on/off-state before falling/rising again at up to data rate of 10 Gb/s. This ensures that the modulator maintains the on/off-state performance of our design during modulation at the particular data rate. Fig. 3.35 to 3.38 show the simulated eye patterns of the OOK modulation. The baseband data input is of pseudo-random binary sequence (PRBS) data frame (2³¹ - 1) at data rates of 4.5 to 10 Gb/s. Vp-p of the baseband data signal is set to 0 to VG2,on, i.e., 0 to 1.8 V. For a better match of the conditions during measurement and future applications, the rise and fall times are set to 10% of Tb during simulation of the eye patterns. An ideal AM receiver is used for envelope detection at the output of the modulator. As can be seen, the rise and fall times of the eye patterns increase with higher data rates as expected. For the proposed modulator, , the simulated eye pattern up to the data rate of 10 Gb/s shows good opening, indicating a modulation index close to 1.

Fig. 3.26. Simulated large-signal performances of the proposed modulator at 60 GHz at on-state.

Fig. 3.28. Simulated large-signal performances of the proposed modulator at 60 GHz at off-state.

Fig. 3.27. Simulated large-signal performances of the proposed modulator at on-state versus frequency.

Fig. 3.30. Simulated drain current (IDD) and power consumption (PDC) at on-state versus P_in. Fig. 3.29. Simulated stability factor of the proposed modulator at on-state.

Fig. 3.31. Simulated output (a) spectrum and (b) waveform of the modulated signal at data rate of 4.5 Gb/s.

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Fig. 3.32. Simulated output (a) spectrum and (b) waveform of the modulated signal at data rate of 6 Gb/s.

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Fig. 3.33. Simulated output (a) spectrum and (b) waveform of the modulated signal at data rate of 8 Gb/s.

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Fig. 3.34. Simulated output (a) spectrum and (b) waveform of the modulated signal at data rate of 10 Gb/s.

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Fig. 3.35. Simulated eye pattern of the OOK modulation at data rate of 4.5 Gb/s.

Fig. 3.36. Simulated eye pattern of the OOK modulation at data rate of 6 Gb/s.

Fig. 3.37. Simulated eye pattern of the OOK modulation at data rate of 8 Gb/s.

Fig. 3.38. Simulated eye pattern of the OOK modulation at data rate of 10 Gb/s.

3.4 Experimental Results

The proposed design was fabricated in 90-nm CMOS process by TSMC. As shown in Fig. 3.39, the die size measures at 471 x 519 μm² with RF and DC pads included. Three GSG-configuration RF pads are used. Two on the left and right are used for RF (carrier) in and output, respectively.

One on the top is used for baseband data input. Note that due to physical limitations of on-wafer probing, the chip size has to be increased with elongated 50-Ω transmission lines on both horizontal and vertical directions. An even smaller footprint of 261 x 469 μm² without RF and DC pads is possible for future applications in OOK transmitter designs. All measurements were performed via on-wafer probing.