Implementation of Proposed Sigma Delta Modulator
4.2 Transistors Level Design
4.2.1 Differential OPAMP
Figure 4.2 A timing diagram illustrating clock signals
4.2 Transistors Level Design
This section described the elaboration of sub-circuits that will be used to realize an actual integrated circuit, which covers an operational amplifier (OPAMP), a comparator, switches and capacitors, and feedback path. The simulation results and device ratios are given at each section.
4.2.1 Differential OPAMP
Utilizing switched-capacitor technology and an operational amplifier (OPAMP) to realize a loop filter in a SDM is a common circuitry for high speed and low power
applications. It is clearly that, however, the performance of this loop filter dominates dynamic specifications of a SDM. Designing a high performance OPAMP is the main purpose in this section. In addition to a main circuit, a bias circuit and a common mode feedback circuit (CMFB) will be discussed.
M1 M2
Figure 4.3 Fully differential OPAMP
Figure 4.3 shows the fully differential OPAMP including its bias circuit and CMFB. The OPAMP, which is a folded cascade amplifier, was chosen for its large dc gain and ability to drive capacitive loads [12]. The bias circuit supplies several internal bias voltages except Vcm. The CMFB determine the output common mode voltage and control it to be a specified voltage [15].
The OPAMP circuit consists of eleven transistors, from M1 to M10 and M16.
The first stage including M1, M2, and M16; the remainders are second stage. It must be noted that the drain current of M16 determines the slew rate of this amplifier.
Added to this, the drain current of M3 (or M4) should be more than M16 to avoid operating failed during slewing. By Naming the drain current of M3 and M16 is “Iss”
and “Ir” respectively, the drain currents of M7 to M10, which are active loads, can be represented as Ir minus Iss. This shows that the device ratios of active loads don’t affect the quantity of current, but affect the voltage gain sufficiently. Briefly speaking, high output resistance is the critical issue to design these four transistors. And then
higher output resistance, higher DC gain. From above discussions, we obtain the following results:
(4.1) (4.2) (4.3) The device ratio of M1 and M2 are another critical issue for high DC gain. By the way, the unit-gain frequency (Fu) is also dependent on their sizes. It can be found that:
(4.4) The overall gain of this amplifier can be derived from Figure 4.4, and the detail procedure is given:
(4.5)
Vid/2
Vb1
Vb2
Vb3
Vcmc -Vo/2 i1
RA RB
R
i Rout
Figure 4.4 Small signal equivalent circuit of OPAMP
The bias circuit contains eight transistors, from M17 to M24. Its outputs are four independent voltage sources to drive OPAMP operating at active mode. Strictly speaking, M22 and M3 is a current mirror pair. Compared with the drain current of M3, the quantity of Vb1 is not the key point in design. In other words, the amount of current and minimum output voltage should be considered prior to Vb1 when design the size of M22 in order to ensure it could be a current mirror source. A similar result could be found in M21.On the other hand, using two skills for higher output swing [28]. First is minimizing the size of M18, second is connecting the gates of M23 and the source of M20. Figure 4.5 shows the results diagrammatically.
Vb1
Vb2=VDD-kVov-Vt
Vb3= Vgs24
Vb4 Vb1
Vb2=VDD-2Vgs
Vb3=Vss+2Vgs
Vb4
Traditional Modified
S
S/k2
Figure 4.5 Two types of the bias circuit
Thus if VDD is 3.3V, Vov is 0.2V, and k is 3, the Vb1, Vb2, Vb3, and Vb4 is 2.4V, 2.0V, 1.0V, and 0.8V respectively. Equations for these device rations can easily be written as:
(4.6) (4.7) (4.8) From M11 to M15, there are five transistors comprise the CMFB. In order to simplify the description of operating, we recall that Voc= (Vo1+Vo2)/2, Vg15= Vf, Vg13=Vcm, and Vg10=Vcmc, as illustrated in Figure 4.3.If Voc raises (drops) slightly greater (less) than specified quantity, the drain currents flow through M11 and M12 will raise (drop) at the same time and then Vcmc will increase. After that Voc will drop (raise) cause of output resistance. This implies that there is a negative feedback loop to “latch” Voc at an immobile position if Vcmc is fixed. Figure 4.6 seeks to capture the fact.
Figure 4.6 Latch Voc by negative feedback
On the other hands, the source follower, which is made up of M13 and M15, senses the Vcm and adjusts Vf to drive Vcmc at a designated voltage. Precisely speaking, Vcmc is a shift form Vcm and output voltage characteristics are controlled
2 2
by it, such as common mode (4.9), maximum (4.10).
(4.9) (4.10) The relationship between Vcm and Voc can be proved by CAD simulation. The results can be schematized as follows:
Vcm Vg15 Vo_peak
Vcm Vg15 Voc
Figure 4.7 Relationship between Vcm and Voc
Capitalizing the foregoing equations, the aspect ratio of this OPAMP can be estimated except CMFB. These constrain represent sufficient information for first-order hand analysis before CAD simulation, however, the results of CAD simulation exhibits a large difference form desired specifications. This is because of the model for CAD is more complex than level 2 model used hand analysis. In order to solve this problem, several methods are proposed here:
(1)Tune the value of S3 and S4 until the drain current is equal to Ir.
(2)Tune the value of S16 until the drain current is equal to Iss.
(3)Tune the value of S7~S10 to improve DC gain.
(4)Tune the value of S1 and S2 to improve DC gain and Fu.
(5)Tune the value of S11~S15 to meet output characteristics.
(6)Using multiple fingers instead of inadequately wide device
14 ( 15 )
2 11
14 ( )
_ 15
11 S
Voc Vcmc S Vg Vth
S
Vo peak Vcmc S Vg Vth
= + × −
×
= + × −
Finally, the transistors sizes and the simulated results, when ambient temperature is 25oC, CL is 1.4 pF, are summarized in Table 4.3 and Table 4.4, respectively. The frequency response of this fully differential OPAMP is revealed in Figure 4.8.
Table 4.3 OPAMP device ratios summary
Transistors Ratio Transistors Ratio
M1,2,7,8,9,10 40 M13,16 25
M3,4,5,6 128.57 M11,12,18 5
M14,15 15.71 M17,19,20,22,23 20
M24 1 M21 2.86
Table 4.4 OPAMP simulated specifications summary
DC Gain 74.867dB Fu 152MHz
PSRR+ 98dB Phase Margin 53.78o
PSRR- 109dB Slew rate 158V/us
CMRR 96dB ICMR 2.1V
Output swing 2.17V Power 2.53mW
1000 100000 11000000 152000000 1000000000
−150
−100
−50 0 50 75
Frequency
Parameters
Gain(dB) Phase(degree)
Figure 4.8 Frequency response of this fully differential OPAMP
4.2.2 Comparator
Generally speaking, the comparator is a circuit that compares an analog signal with another analog signal or reference and outputs a binary signal based on comparison. Binary signal means one of two given point exhibits anytime, but this concept is too ideal fore real world situation, where there is a transition region between the two binary states [20]. Therefore, the cores of designing a comparator are speed, dynamic rang, accuracy, and so on.
From the circuitry point of view, comparators can be divided into open-loop and regenerative comparators. The open-loop comparators are based on OPAMP and the regenerative comparators are based on positive feedback. From operation point of view, they can be classified into continuous-time and discrete-time comparators. The continuous-time means comparators generate digital level outputs all the time and the discrete-time means comparators only functions over a portion of a time period [20].In this thesis, we decide to adopt the discrete time comparators founded on regenerative structure for high speed and low power dissipation.
(a) (b) M1 M2
Vlow Vhigh
Figure 4.9 (a) A NMOS latch (b) An analogy
Before tuning to realize a whole comparator, the principle of regenerative comparators must be clarified. A simple model is shown in Figure 4.9(a) and it is also called a NMOS latch. If their drain voltage is different from each other, one of them will be push up to a high position (VDD) and the other will be pull down to a low position (ground), Figure 4.9(b) is an analogy. In other words, the latch output binary signal caused by practically dissimilar drain voltage or unavoidable noise.
We can analyze a latch more detail by plotting I-V curves illustrated in Figure 4.10. Suppose the drain voltage of M1 raises a little voltage, vds, and approaches to Vgs+vds, the gate voltage of M2 immediately raises to this identical level. The drain voltage of M2 drops vds’ on account of fixed current as shown in Figure 4.10(a), this lead to the gate voltage of M1 drops to Vgs-vds’ at the same time. Then the drain voltage of M1 raises vds’’ because of fixed current as shown in Figure 4.10(b).
Obviously vds’’ is bigger than vds, and this implies that there is a positive feedback loop. The result of this effect is binary outputs we read on the front page.
Figure 4.10 DC analysis of a NMOS latch
The first important parameter of a latch is its equivalent output resistance. If adding a testing voltage, like Figure 4.11(a), the output resistance can be derived below. The second is the time it takes for a latch goes from its initial value to the final value [20] developed the equations (4.12) by Figure 4.11(b).
(4.11)
Figure 4.11 Equivalent models for (a) output resistance (b) time constant
Let us now return to realization of an entire comparator. Figure 4.12 is a discrete-time comparator bases on regenerative structure which is used a clock input to alter its operation modes. Assume clock is high, M7~M10 becomes two pair of active loads for M5 and M6, this make input signal can be amplified and called
“preamplifier” or “track mode”. Assume clock is low, one active load becomes invalid and the latch built up by M7 and M8 push or pull the output signal, this is called
“latch mode”.
Figure 4.12 A regenerative comparator
The gain of this preamplifier can be confirmed by equation (4.11), and the result is equation (4.13). We should notice that the denominator have to be positive to ensure correct output polarity, in addition to this, the denominator must as small as possible to amplify input signal tremendously. In order to, precisely speaking, remove outputs from the highest or lowest state to the common mode voltage and track inputs, gm9 a little more than gm6 is the best choice.
(4.13) The dc analysis of this preamplifier is shown in Figure 4.13, it reveals the gain is approximately fifteen decibel and output range is 1.5 volt. Although performance of this preamplifier is worse than an amplifier like an OPAMP, but it is enough to trigger the latch and compare input signal by quite low power. Table 4.5 summarizes device rations of the entire comparator.
Voltages (lin)
Voltage X (lin) (VOLTS)
-2 0 2
** comparator **
Figure 4.13 DC analysis of the preamplifier Table 4.5 Comparator device ratios summary
Transistors Ratio Transistors Ratio
M1,2 5 M3,4 18
M5,6 18 M7,8 5
M9,10 10 M11 20
M12 20 Power dissipation is 238 μW
1 6
The outcomes of the transient analysis are illustrated in Figure 4.14.From high to low, the input frequency is 0.2MHz, 2.5MHz, and 5MHz respectively; the clock rate is 2MHz, 25MHz, and 50MHz respectively. It is evident that higher input has longer settling time. Finally, another thing we need to note is that, a comparator can be considered as a one bit ADC, so the inputs must lower than half of clock rate to meet the Nyquist rate theory.
Voltages (lin) -2
0 2
Time (lin) (TIME)
0 1u 2u 3u 4u
5u
** comparator **
Voltages (lin) -2
0 2
Time (lin) (TIME)
0 200n
400n 25m
Voltages (lin) -2
0 2
Time (lin) (TIME)
0 50n 100n 150n
200n 50m
Figure 4.14 Transient analysis of the preamplifier