System Level Design Considerations
3.2 Higher Temperature Issues
Current commercial CMOS technologies can be used without any process modifications to design circuits useful up to 250oC [24]. However, thermal effects on small signal parameters of CMOS are studied necessarily to figure out the design tradeoffs and considerations limitation for analog circuits.
Table 3.1 lists some parameters with level 2 model [25], it is evident that the drain current have strong dependency on temperature, furthermore all of small signal models as transconductance and output resistance, are based on the amount of drain current. We may, therefore, reasonably conclude that the relationship between these parameters and temperature is quite close. Direct deriving correlations, however, bring about complex results and inefficiency on circuit design. Fortunately, some effectives equations proposed in [24] are present along with the temperature dependencies of key design parameters and represent sufficient information for first-order hand analysis prior to CAD design.
Table 3.1 Some parameters of NMOS with level 2 model
Parameter Equation
Drain current ( )2 (1 ) Intrinsic carrier concentration 7.785 1015 32 2EgkT
ni T e
The effects of temperature on large signal parameters of the MOSFET are discussed first. Recalling the drain current, wherein threshold voltage and effective mobility are critical points. Whether both of them are analytical quantity, two good approximations can describe the temperature dependency, thus:
(3.20) (3.21) Where T is absolute temperature, (α, β, γ) are parameters depend on processing. Then we can estimate the Zero-Temperature-Coefficient (ZTC) bias points for saturation region, at which the drain current exhibits minimum temperature sensitivity, it is possible to write:
(3.22) Another ZTC bias point over the range [T1, T2] is addressed in [24], that is:
(3.23) In 0.25μm CMOS technology, (α, β, γ) = (-0.9m, 800m, -1.5) and (+0.88m, -1124m, -1.5) for NMOS and PMOS respectively. Using equation (3.20), (3.22) and (3.23), the ZTC bias point for a NMOS during temperature [300k, 500k] is about 920mv. If we use HSPICE to fide out this ZTC bias point, shown in Figure 3.8, its value is 897mv.
( )
A similar result is exhibits in triode region can be expressed as:
Voltage X (lin) (VOLTS)
400m 600m 800m 1 1.2 1.4 1.6 1.8
ZTC bias points
** ztc **
Figure 3.8 ZTC bias points for NMOS (14μm/0.7μm) in 0.25μm process
By the way, retuning to equations (3.20) and (3.21), the threshold voltage decreases with down scaling, the mobility have no effect with down scaling, and the ration of n to p inversion layer mobility μn(T)/μp(T) remains approximately constant between 25oC and 250oC [26].
Let us consider small signal models right now. Most important two parameters are transconductance and output resistance, which determine the gain and bandwidth of many circuits. It is easy to write that:
Previous equations imply that the minimum variation of transconductance and output resistance occur at ZTC bias point. So, in order to maintain the same characteristic during temperature rise, bias at ZTC is the best choice, below are simulation results:
Figure 3.9 Id, gm, gds characteristics for ZTC, ZTC+0.2v, ZTC+0.6v
If the temperature is higher than 250oC, sharp increases in the output conductance and body effect transconductance have consistently been observed [27], it has been determined that diffusion leakage current. The various leakage currents comprise the following:
1. The drain and source to body junctions’ bottom wall component, Ib(T), which is proportion to W and D, shown in Figure 3.10.
2. The drain and source to body junctions’ sidewall wall component, Isw(T), which is proportion to W and X, shown in Figure 3.10.
3. The inversion layer to body junctions component, Ich(T), which is proportion to the W and L, shown in Figure 3.10.
Gate
Figure 3.10 Leakage current components
Leakage current, in particular, can be a significant source of impairment and is worthy of a more detail review. The ideal P-N diode current is described by:
A is the area of leaky diodes. If this diode is operated under strong reverse, it can be reduced as:
In addition to this, there is reverse bias current due to generation-recombination events within the depleted region, which is:
So, the total leakage current in the reverse bias as shown [12]:
(3.27) Figure 3.11 indicates that, the leaky diodes are sinks and sours at the drain or source node of NMOS and PMOS respectively. Although, we can use equation (3.27) to calculate leakage current, but the exactly amount is difficult to predict and hard to avoid. Design a compensation circuit is more effective to restrain thermal problems.
IL IL IL IL
IL IL
Figure 3.11 The leaky junction diodes are explicitly shown in CMOS
2 D( 1)
The principle of compensation circuits is algebraic sum of all leakage current be zero at any given node. If one was not this case, net leakage current would flow into or out of this node, thus forcing an increase or decrease in drain current of adjacent transistors, which result in voltage shift from bias points and performance degrade. To this point, adding diodes or complementary structure are approaches to reduce leakage current, as sketches below.
Compensation Diode Voltage dividing string
Transmission gates
Figure 3.12 Compensation circuits for leakage current
We should note that transmission gates, show in Figure 3.12, this structure is popular in the switches-capacitor system to be a switch. The leakage current is not matched all the time and keeps almost constant for any given node, thereby charging or discharging loading capacitors, so that setting or holding error as a result.
Increasing clock rate, which can decrease the charging or discharging time, is one way to solve this problem.
From previous study, we can make a conclusion below to minimize leakage current in high temperature environment:
z Small diffusion area z Low leakage switches
z Compensation devices, like diodes z Matching leakage area
z Bias at ZTC points
z External capacitors to increase the time constant z High clock rate