Switches and Capacitors

The switches and capacitors are frequently used in integrated circuit design, for example, sample and hold circuits. No mater each of them can be built up by transistors. Special process of capacitors, however, is good for implementation of larger size and lower variation. Different fabricator provides different capacitor for designers to use, but this is irrelevant to the main subject here, we will only discussed some key points about them. On the contrary, switches are only made up by transistors without special process and need to be discussed more detail.

A MOS transistor can serve as a switch because (a) it can be on while carrying zero current and (b) its source and drain voltage need not follow that variation [29].

Figure 4.15(a) show three structures of CMOS switches. The first point to note is how to turn on them? As we know, for NMOS, Vgs must bigger than Vthn, for PMOS, Vsg must bigger than |Vthp|. Suppose the gate voltage of NMOS and PMOS is VDD and ground respectively, and then the output ranges of different switches can be estimated, the results are shown in Figure 4.15(b). It is important that transmission gates which are made up by a PMOS and a NMOS can pass full voltage level. The second point to note is the speed consideration. Simply speaking, a switch circuits can be seen as a R-C circuit because of turn on resistance. Smaller turn on resistance has smaller time constant and can approach to input level sooner. So, we focus on the evaluation of turn on resistances.

PMOS

NMOS VDD

VSS VDD-Vthn

VSS+Vthp

(a) (b)

Transmission gate

Figure 4.15 (a) MOS switches (b) Output level for different switches

As illustrated in front of page, if NMOS switches on, the output is approximately equal to input and the transistor is operated at triode region. Thus we can obtain the current flowing the switch is:

So we can express turn on resistance of a NMOS switch as:

(4.14) Similarly, turn on resistance of a PMOS switch and a transmission gate is:

(4.15)

(4.16) It is clearly that:

(a) Bigger device ratios have smaller turn on resistance, but larger area is needed.

(b) Turn on resistance is a function of input level.

(c) For a transmission gate, NMOS dominates the turn on resistance when input is low.

PMOS dominates the turn on resistance when input is high.

Despite equations written above, accuracy is not enough for high speed applications. The CAD simulation is necessary and results are indicated in Figure 4.16.

The first curve is turn on resistance of NMOS, the second is turn on resistance of PMOS, and the last is turn on resistance of transmission gates. These curves are based on that, device ration of NMOS and PMOS is 20/0.36 (or 4/0.36) and 20/0.36 respectively. All of them are agreed with principles we proposed before. There is another important thing we need to know, transmission gates allow full swing and constant resistance all the time, but requires complementary clocks and larger area. If input level is confined in some region, NMOS or PMOS is satisfied for adoption.

This work is implemented in single-poly five-metal 0.25um CMOS process provides metal-insulator-metal (MIM) process to implement capacitors. The structure and equivalent circuit is shown in Figure 4.17 next page. By the way, the parasitic capacitor of the bottom plate is always larger than top plate, so we should avoid the input nodes of OPAMP connecting to the bottom plate s of capacitors.

( )

R on transmission W W

Cox L Vin V ss V Cox L VD D V V

µ µ

= − − − −

0 0.5 1 1.5 2 2.5 3

Figure 4.16 Turn on resistance of NMOS, PMOS, and a transmission gate

M5

Figure 4.17 MIM capacitor structure and its equivalent circuit

4.2.4 Integrator

An integrator is a main building block of SDM. It plays a loop filter to eliminate quantization error of the ADC, so the overall performance of the modulator is determined by it. We shall now confine our attention to realize an integrator by OPAMP, comparator, switches and capacitors which we have discussed in detail at early sections.

Figure 4.18 A pair of complementary SC integrators

Our objective is a discrete-time integrator based on switched-capacitor (SC) technology. Toward that we show a pair of complementary SC integrator in Figure 4.18, one is called inverting and another is called non-inverting. Both of them are completely insensitive to stray capacitances between any node and ground [15]. For infinite amplifier gain and bandwidth, Figure 4.18 has the ideal transform functions below:

(4.17) (4.18) Assume there is an offset voltage at the OPAMP input node, these equations are:

(4.19)

Inverting H z C

C z

Figure 4.19 shows several structures to complete differential input, all operational procedures of them are similar to the complementary SC integrators.

C1

Figure 4.19 Differential SC integrators

Owing to limitations of OPAMP, however, the deviation of ideal ones and SC integrators can not be ignored. However, SC filters are much tolerant of OPAMP limitations when encountered in active-RC filters. Fuller discussion has been present in section 3.1, we only plot the gain and phase versus frequency at Figure 4.20 for SCI with OPAMP described in section 4.2.1 and switches described in section 4.2.3.

From the equations (4.19) and (4.20), the offset voltage affects output signal seriously, in order to attenuate this effect, a popular schematic called correlated double sampling (CDS) is employed [30], Figure 4.21 at next page is a simple diagram of it. An offset capacitor is the key feature of CDS, and then the offset voltage is double sampled, as its name, by this capacitor. During φ1, the input signal and offset voltage is stored at C1 and Cos respectively, during φ2, the charges on the C1 are transferred to C2 and offset voltage is still sampled on Cos, then output level is unaffected by it.

According to previous discussions, we adopt a differential SC integrator, like Figure 4.19 class one, and add CDS technology to complete the loop filter in SDM, fully Figure is shown in 4.1-1. Table 4.1 summarizes sizes of the SC integrator and operational period. We don’t repeat these data again, readers can refer to section 4.1

10² 10³ 10⁴ 10⁵

Figure 4.20 The Bode plot of SCI with present OPAMP, C1/C2=0.8, and 2Mhz clock

C1 Cos

Figure 4.21 A CDS SC integrator