Digital circuit realization

The digital circuits include non-overlapping four-phase clock generator, feedback loop control circuit with a 20% mismatch signal externally, digital delay circuit and other circuit for new proposed MASH only.

3.2.1 Switched-capacitor implementation and C-ratio mismatch control The basic switching capacitor circuit in integrator has been described in section 3.1.2.

Now, the digital control parts of switching capacitor implementation will be discussed in this

section. First, we talk about the four-phase non-overlapping clock generation circuit. Fig. 22(b) is the output waveform of four-phase clock. This circuit is based on two phase non-overlapping clock generation circuit. At least one pair of non-overlapping clock is essential in switched-capacitor circuits. These clocks determine when charge transfers occurs and they must be non-overlapping in order to guarantee charge is not inadvertently lost. As seen in Fig. 29(a), the term non-overlapping clocks refers to two logic signals running at the same frequency and arranged in such a way that at no time are both signal high. Note that the time axis in Fig. 29(a) has been normalized with respect to the clock period, T. Such normalization illustrates the location of the sample numbers of the discrete-time signals that occur in switched-capacitor filters. As a convention, we denote the sampling numbers to be integer values just before the end of clock phase φ1, while the end of clock φ2 is deemed to be 1/2 sample off the integer values as shown. However, it should be noted that it is not important that the falling clock edge of φ2 occur precisely one-half a clock period earlier than falling edge of φ1. In general, the locations of the clock edges of φ1 and φ2 need only be moderately controlled to allow for complete charge settling. So in four-phase clock, a new stage of “de-load” is applied to discharge the sampling capacitor Cs which has been described in previous section 3.1.2.

One simple method for generating non-overlapping clocks is shown in Fig. 29(b).

Here, delay blocks are used to ensure that the clock remain non-overlapping. These delays could be implemented as a cascade of an even number of inverters.

Fig. 29 Non-overlapping clocks (a) clock signal, φ1 and φ2. (b) A possible circuit

The final four-phase non-overlapping clock generation circuit is shown in Fig. 30. The delay unit is composed by two long channel (3µm) inverters which are shown in Fig. 29(b).

Note that every output has its buffer to drive the MOS switches.

Fig. 30 The schematic of four-phase non-overlapping clock generation

Fig. 31 The simulation result of four-phase non-overlapping clock generation

The control circuit as shown in Fig. 32 is another key block to maintain the function of Sigma-delta modulator. The node of “In” is the output of quantizer, it is a digital signal. The output of quantizer is connected to the input of DAC in feedback loop. In order to feed the control signal to DAC, this control circuit must be able to fit the function of non-inverting integrator or inverting integrator which have explained in section 3.1.2.

Fig. 32 The schematic of control circuit The brief function is list below:

CTL1=CLK1; CTL2=CLK2 when IN=H (27)

CTL1=CLK2; CTL2=CLK1 when IN=L (28)

We can easily know that the φ1 and φ2 will change the polarity when IN is switched.

Review the Fig. 24, the DAC function is applied by non-inverting and inverting integrator, and the value of reference voltage can adjust the feedback volume of DAC. Finally sum the input signal and feedback value of DAC by superposition which is shown in Fig. 24.

The major issue of this thesis is reducing the effect with mismatch errors. The non-linear of OPAMP is not easy to establish by external signal, but capacitor ratio mismatch is much easier to construct with an external signal-“MIS”. A C-ratio mismatch is forced when

“MIS” pin is connected to “H”. The design value of capacitor in feedback DAC is 1p in normal (match) condition. This 1p capacitor is divided into two parts, 0.8p and 0.2p. The control signals CTL1, ZCTL1, CTL2 & ZCTL2 in Fig. 32 are connected to 0.8p capacitors;

and CTL1_M, ZCTL1_M, CTL2_M & ZCTL2_M in Fig. 32 are connected to 0.2p capacitors.

0.8p+0.2p capacitors are used in normal (match) condition, but only 0.8p capacitor is used in mismatch condition, so a 20% mismatch happen. The SNR can be measured by switching the

“MIS” pin, and compare the value between match and mismatch. The expectative result is that the SNR of conventional MASH will descend with “MIS” is “H”. And only a little SNR will drop in new proposed MASH whether “MIS” is “H” or “L”. Here the “MIS” control must be added in this control circuit, and the simulation result is shown in Fig. 33.

Fig. 33 The simulation result of control circuit

Finally, the conclusion of control circuit with mismatch function is list below:

CTL1=CLK1; CTL2=CLK2 when IN=H (29)

CTL1=CLK2; CTL2=CLK1 when IN=L (30)

CTL1=”L”; CTL2=”L” when MIS=H (31)

CTL1=CTL1_M; CTL2=CTL2_M when MIS=L (32)

3.2.2 Logic circuit and digital cancellation

In this section, I would like to introduce the extra circuits which are used in new proposed MASH. They include the integrator capacitors which share sampling capacitors and op-amps, digital delay circuits and new clock generator. The first part has been mentioned in

chapter 2.3. In order to keep the sampling frequency, the clock frequency of new proposed MASH is the double of conventional MASH. So each sampling is formed with two clocks.

Both Sigma-delta modulators are first-order ones which are connected to input signal in first clock period, in other word the input signal is sent to both Sigma-delta modulators at the same time, and then be second-order Sigma-delta modulators which are connected to other side Sigma-delta modulator in second clock period. The first and second period data must be keep in integrator capacitor. This is why we need two capacitors for new proposed MASH. Only one more capacitor is added as conventional MASH, the sampling capacitors and op-amps can be shared.

The clock generation circuit is the other block which is added in new proposed MASH.

In order to divide the clock for time- and capacitor- multiplexing, all kinds of clocks must be generated to re-locate the data path. Fig. 34 shows a non-overlapping clock divide one sampling frequency into two stages: timing phase-1 and timing phase-2. The brief principle of this circuit is introduced in chapter 3.2. Here the outputs of the two stage clocks, clk1 and clk2, will be produced other control clocks in Fig. 35 which is like a counter by 2 circuit.

These control clocks are the key signals to re-locate the data path to be a new proposed MASH.

Fig. 34 divide one sampling period into two phases

Fig. 35 Clock generation circuit for new proposed MASH

The digital delay circuit of z^-1 and z^-1/2 are approached by a simply flip-flop cell which is shown in Fig. 36(a) and (b). The z^-1 mean that the digital data is delayed one sampling clock (equal to two input clocks), and the z^-1/2 mean that the data is delayed half sampling clock (equal to one input clock). This is because the time has z^-1/2 difference between first-order Sigma-delta modulator and second-order Sigma-delta modulator. So both z^-1 and z^-1/2 are necessary.

Fig. 36 digital delay circuit (a) z^-1 (b) z^-1/2

3.2.3 System design

In this section we give a design discussion of a cascaded Sigma-delta modulator (MASH). The 1-1 modulator architecture with coefficients is repeated in Fig. 37 for convenience. We start by choosing the coefficients in the modulator. The transfer function of the modulator is given by [23]

-2 -1 2

1c

(1-z ) e2(z) Y(z)=z X(z)+

H (33)

where e2(z) is the quantization noise in the second stage. To make the quantization noise small, H1c should be as close as 1. This coefficient also determines the gain factors in the digital cancellation logic. All other gain factors in the modulator are in a SC implementation determined by capacitor ratios. The capacitor ratios should be chosen such that the circuit is easy to layout using unit-capacitors.

Fig. 37 2nd-order 1-1 cascaded Sigma-delta modulator with system coefficient.

To make the modulator less sensitive to circuit noise the voltage swings in all the nodes of the circuit should be approximately the same. The maximum signal swing at the input of last stage can be determined by [24]

2 1c 1 1

Where ∆ is the step size in the D/A converters and x1 is the maximum swing at the input of the first stage. To maximum H1c, H1 should be 1. The integrator gains are chosen to give signal swings at the OPAMP’s outputs that equal to or slightly less than the swing of the feedback signals of the DAC.

After calculating, the capacitor sizes can now be determined as shown in Table I and Fig. 38. And the final SC-implementation of conventional 1-1 Sigma-delta modulator is shown in Fig. 39 and new proposed 1-1 Sigma-delta modulator is shown in Fig. 40. All capacitor values of both modulators are listed in table II.

Table I Gain factors in the modulator.

Coeff. Value

Fig. 38 Gain factors in the modulator.

Fig. 39 SC-implementation of conventional 1-1 modulator.

Fig. 40 SC-implementation of new proposed 1-1 modulator.

Table II Capacitor values in the modulator.

Capacitor Value(pF) Cs1 1 Ci1 4

Cβ1 1

Cs2 4 Ci2 4

Cβ2 1

Cβ3 1