Gain boosting CMFB OPAMP

Most Sigma-delta modulator implementations have switched-capacitor integrators often using folded-csacode OTA, because of their fast settling. The dc gain of op-amps in a MOS technology intended for switched-capacitor circuits is typically on the order of 40 to 80 dB. Low dc gains affect the coefficient accuracy of the discrete-time transfer function of a switched-capacitor. The unity-gain frequency and phase margin of an OPAMP gives an indication of the small signal settling behavior of an OPAMP. A general rule is that the clock frequency should be at least five times lower in frequency than the unity-gain frequency of the OPAMP assuming little slew-rate behavior occurs and the phase margin is greater than 60 degrees.[8] Since the loads of these OPAMPs are purely capacitive (never resistive), fully differential OTA structure with gain boosting CMFB is preferred since this structure has a good high frequency power supply and common mode rejection that is essential to attenuate disturbances generated by digital parts. For this structure, the dominant pole is generated by the capacitive loaded output stage, whereas the other poles are located at relatively high frequencies [12]. The SC OPAMP is shown in Fig. 14.

Fig. 14 Fully differential gain boosting CMFB OPAMP

The use of a PMOS differential pair eliminates need of chopper stabilization, since the 1/f noise is 30 times lower than NMOS in this process. In addition, dynamic threshold variation due to charge trapping in the MOS channel is ten times less severe for PMOS [13].

Insufficient dc gain will cause integrator gain and pole error and will increase quantization noise leakage. Fully differential gain enhancement [14] is employed to increase output impedance of the cascade loads, which enhances both dc gain and power supply rejection ratio [6].

For high gain designs, two-stage configuration might be the appropriate choice;

however, the speed of this configuration is the bottleneck. In this design, a fully differential folded csacode that has two fully differential folded cascade boosting amplifiers has been chosen. It has a switched capacitor CMFB circuit that will enable the OPAMP to have a common mode output voltage. The boosting amplifiers have a continuous time CMFB circuits.

The boosting amplifiers are of two types [15]: the BN has a NMOS differential input stage, while the BP has a PMOS differential input stage. As shown in Fig. 14, the inputs of the BN boosting amplifier comes from the drains of M18 and M19 transistors, which are supposed to

be biased in the saturation region and have a drain-to-source voltage, Vds<0.5V. This means that the inputs to the differential pair of BN are going to be around 2.5v, hence an NMOS differential input stage is required. The bottom boosting amplifier, BP, has its inputs coming from the drains of M8 and M9 which are supposed to be biased at Vds<-0.5V, hence a PMOS differential input stage is required. The main OPAMP has a switched capacitor CMFB circuit in order to maximize the output range of the main OPAMP. Next, the design of the boosting amplifier is described first.

The design of the Boosting Amplifier. [14]

The NMOS type boosting amplifier, BN, which is continuous time common mode feedback circuit is shown in Fig. 15. Cascading the two transistors will decrease the excess bias voltage of those transistors in order to guarantee that they are in the saturation region of operation when they have the common mode voltage input to their gates set by the drains of M18 and M19. The CMFB circuit consists of all transistors MC1~MC9.

Fig. 15 NMOS-input fully differential gain boosting amplifier with continuous time CMFB The BP boosting amplifier is the same as the NMOS type with the exception that a PMOS differential input stage is used in addition to a NMOS CMFB circuit instead of the PMOS one used above. The BP boosting amplifier is shown as Fig. 16.

Fig. 16 PMOS-input fully differential gain boosting amplifier with continuous time CMFB CMFB circuit design of the boosting amplifier.

Designing the CMFB circuit of the boosting amplifiers is a straightforward process.

The output of each boosting amplifier does not need high swing, thus, a continuous time CMFB circuit is used [16]. The first step is to design the boosting amplifier without the CMFB circuit such that the common mode output of the OPAMP is around BPC. Once this is finished, part of the output is generated by the CMFB circuit using transistors MC8 and MC9.

For example, suppose that after designing the OPAMP without the CMFB circuit, the channel width of M4 and M5 is 10µm for 5µA current mirror. If we assume that half output current will be provided by the CMFB circuit, then channel width of M4 and M5 will be reduced to 5µm. If Vref equals the common mode voltage of Von and Vop, then MC2-MC7 are designed such that the current in MC4 is the same as the current through both of MC2 and MC3. This means that the current through MC4 is half of the current MC1. Since the current in the path of M9 and M7 will is 1/2 of M11, then the current of MC4 is 1/2 of that in M9 or M7. So, 1/2 of the current of M9 or M7 will be provided by the CMFB circuit, and the rest is provided by M5 which will be 1/2 of the current. This is why channel width of M5 was reduced from

10µm to 5µm. Fig. 17 shows the AC frequency response of BN boosting amplifier. The gain is about 82dB (typical case) and phase margin is about 55 degree.

Fig. 17 Gain and phase margin with AC response of the boosting amplifier The design of the gain boosting CMFB amplifier.

Consider the simple cascade in Fig. 18(a), whose output impedance is given by

2 2 1

out m O O

R =g r r . As far as Rout is concerned, M1 operates as a degeneration resistor in Fig.

18(b), sensing the output current and converting it to a voltage. Illustrated in Fig. 18(c), the idea is to drive the gate of M2 by an amplifier that forces Vx to be equal to Vb. Thus, voltage variations at the drain of M2 now affect Vx to a lesser extent because A1 “regulates” this voltage. With smaller variations at X, the current through rO1 and hence the output current remain more constant than those in Fig. 18(b), yield a higher output impedance.[17]

1 2 2

out m O O1

R ≈ A g r r (24)

concluding that Rout can be “boosted” substantially without stacking more cascode devices on top of M2. So the Rout in Fig. 14 can be written as

BN 13 13 19// BP 11 11 9

out m O O m O O

R ≈ A g r r A g r r (25)

The gain of boosting amplifier is about 80dB in Fig. 17, this is said that the gain boosting structure improve the output impedance about 10000 times. The output impedance is up to

472.7MΩ by Hspice simulation.

Fig. 18 Increasing the output impedance by feedback.[17]

The most important part of the gain boosting CMFB OPAMP is its common-mode feedback circuit. It is a compound by switched capacitor circuit and a continuous time CMFB circuit as shown in Fig. 14. The switched capacitor CMFB circuit is utilized in order to keep the common mode output voltage at the required level while maximizing the output swing of the operational amplifier. The sizes of the switches should also be chosen carefully so that they will not have charge injection effect on the capacitors. Fig. 19 shows the AC frequency response of main amplifier. The gain is about 100dB (typical case) and phase margin is about 60 degree. Most important thing is that the unity gain frequency is up to almost about 100MHz.

Fig. 19 Gain and phase margin with AC response of the main OPAMP

3.1.2 Integrator

In order to show the new proposed MASH that can improve SNR with mismatch effect, both conventional and new proposed MASH is placed in this chip. All the circuits are based on first-order Sigma-delta modulator which is shown in Fig. 20.

Fig. 20 Basic first-order Sigma-delta modulator

While the circuit seen so far have all been shown with single-ended signals, in most analog applications it is desirable to keep the signal fully differential. Fully differential signals imply that the difference between two lines represents the signal component, and thus any noise which appears as a common-mode signal on those two lines does not affect the signal.

Fully differential circuits should also be balanced, implying that the differential signals operate symmetrically around a dc common-mode voltage (the common-mode voltage is set to vdd/2). Fully differential circuits have the additional benefit that if each single-ended signal is distorted symmetrically around the common-mode voltage, the differential signal will have only odd-order distortion terms (which are often much smaller).[8] A fully differential realization of the first-order Sigma-delta modulator is shown in Fig. 21. Note here that the fully differential version is essentially two copies of the single-ended version, which might lead one to believe that it would consume twice the amount of integrated area. Fortunately, the increased area penalty is not that high. First, we see that only one OPAMP is needed although it does require extra common-mode feedback circuit. Second, note that the input and output signal swings have now been doubled size. Thus, to maintain the same dynamic range due to (kT)/C noise, the capacitors in fully differential version can be half the size of those in

the single-ended case. Since smaller capacitors can be used, the switch size widths may also be reduced to meet the same settling-time requirement. However, the fully differential circuit has more switches and wiring so this circuit will be somewhat larger than its single-ended counterpart. However, recall that the fully differential circuit has the advantages of rejecting much more common-mode noise signals as well as having better distortion performance.

Fig. 21 Fully differential first-order integrator

The basic first-order Sigma-delta modulator is composed by two components:

Integrator and quantizer. The integrator is the most important part of the modulator. To get better performance, the high performance folded-cascode CMOS OPAMP is adopted in the design. [18]

Fig. 20 shows the first integrator of the first stage with the 1-b digital-to-analog converter (DAC), and Fig. 22 shows the clock timing. A parasitic-insensitive integrator (Stray-insensitive integrator) is considered to be used for high-accuracy integrated circuits.

[8][19]

Fig. 22 (a) switched-capacitor unit (b) four-phase non-overlapping clock

Even with single-ended sampling, the reference will still see data-dependent loading during the sample phase (φ1 and φ1D high). Since data dependency across CR1 remains after the integrate phase, the reference will see a data-dependent load when recharging CR1 during the sample phase. To avoid this mechanism, four-phase non-overlapping clock scheme was developed [6]. The difference from the conventional four-phase clock [20] is the clock sequence after the integrate phase, i.e., φ1 rising prior to φ2dD falling. This gives a short period where both terminals of CR1 are connected to VCM. This period will discharge (“de-load”) any data dependency across CR1 before charging the reference voltage at the next sample phase.

Another important circuit element in switched-capacitor circuits is the MOS switch.

The simplest realization of an on-off switch Fig. 23(a) in MOS technology is a single MOSFET Fig. 23(b). When the gate has a sufficiently high voltage of the appropriate polarity (positive for NMOS, negative for PMOS), the switch will be “on”, and a current iD will flow between node 1 and node 2 in response to a potential difference vDS between these node.

Since the on-value of the gate voltage vφ, derived from a clock Fig. 23(c), is usually large, it can be assumed that the FET switch is in its linear region. A “clock feedthrough” noise will be generated.

Fig. 23 MOS switch (a) symbol; (b) single-MOSFET realization; (c) equivalent circuit

In most applications, noise voltages of such magnitude are not tolerable. To compensate for the clock feedthrough effect using both NMOS and PMOS transistors are available. The circuit of Fig. 23(a), which compensates feedthroughs to both nodes 1 and 2, can be used. This circuit also reduces the voltage drop across the switch, and thus increases the dynamic range since smaller signals may be used [19]. The on-resistance Ron performance of NMOS, PMOS, and CMOS switches is discussed now. For a n-channel device with the processing parameters given in the figure and a gate voltage of VDD=5v, the switch will cut off when the signal voltage exceeds 2V. Similarly, the PMOS switch cuts off when Vin<0.

The first-order Sigma-delta modulator has a feedback loop with 1-b DAC. Fig. 24 shows the transfer function of non-inverting and inverting integrator. We can only exchange the clock φ1 and φ2 to the switches which are on the feedback loop. Hence, a simple 1-b DAC can be designed by this approach.

Fig. 24 First-order A/D modulator: [8]

(block diagram and switched-capacitor implementation)

New proposed MASH employs the time-division concept for architecture. The time- and capacitor- multiplexing switched-capacitor integrator is mention in chapter 2.

3.1.3 Quantizer

The second major component of modulator is the quantizer. The 1-bit quantizer of the modulator can be realized with a comparator. Three principle design parameters of this comparator are speed, which must be adequate to achieve the desired sampling rate, hysteresis and a latch control by clock which can hold data when in integration state.

Often, comparators are used to convert a very slowly varying input signal into an output with abrupt edge, or they are used in a noisy environment to detect an input signal crossing a threshold level. If the response time of the comparator is much faster than the variation of the input signal around the threshold level, the output will chatter around the two stable levels as the input crosses the comparison voltage. Fig. 25(a) shows the input signal and the resulting comparator output. In this situation, by employing positive (regenerative) feedback in the circuit, it will exhibit a phenomenon called hysteresis, which will eliminate the chattering effects and cycle oscillation [21]. The response of the comparator with hysteresis to the input signal is shown in Fig. 25(b).

Fig. 25 Response of a fast comparator (a) without hysteresis (b) with hysteresis To combine the sample-and-hold function and the comparator function in a quantizer, I choice the source-coupled differential pair with positive feedback for hysteresis. Consider

the circuit of Fig. 26, Vin and Vip are connected to the differential outputs of integrator.

Suppose Vip is larger than Vin, M36 is on and M35 is off and all the tail current flows through M36 and M39. The current through transistors M35, M38, M42 and M43 are zero and the node voltage V(out) is low. Next assume that the input voltage Vip is gradually decreased and Vin is gradually increased so that transistor M35 begins conducting and part of the tail current start flowing through it. This process continues until the current in transistor M35 equals the current in M43. Any increase of the input voltage beyond this point will cause the comparator to switch state so that M36 turn off and all the tail current flows through M35.

The complete schematic of a comparator with hysteresis, which consists of a source-coupled differential pair with positive feedback, is shown in Fig. 26. For this circuit the value of α is greater than 1 [22] and the simulation result with 25mV (typical) hysteresis is shown in Fig.

27.

The gain of comparator which can be read in Fig. 27 is about3.3v

=3300

1mv , or 70dB.

And the propagation delay of the comparator is 5ns.

Fig. 26 The schematic of latch comparator with hysteresis

Fig. 27 The .DC simulation result of latch comparator with hysteresis

Fig. 28 The .Tran simulation result of latch comparator with hysteresis