Simulation results

The simulated performance of the 1-1 MASH or cascaded architecture will now be presented. In the case of digital audio, various sampling frequencies might be fs=5.6448MHz, 2f0=44.1 kHz, which represent an oversampling ratio of 128. As discussed in 3.2, a number of circuit imperfections cause the modulator performance to deviate from this ideal prediction. A capacitor mismatch will be simulation by Matlab Simulink to show the impact of SNR.

3.3.1 Matlab (Simulink) simulation results

The Simulink model of 1-1 modulator structure is shown in Fig. 41. Note that both of the integrators have a sampled-and-hold delay. This sampled-and-hold signal is then applied to an A/D delta-sigma modulator, which has as its output a 1-bit digital signal. This 1-bit digital signal is assumed to be linearly related to the input signal, although it includes a large amount of out-of-band quantization noise. To remove this out-of-band quantization noise, a digital decimation filter is used as shown. Conceptually, one can think of the decimation process as first reducing the quantization noise through the use of a digital low-pass filter.

This decimation process does not result in any loss of information, since the bandwidth of the original signal was assumed to be f0.

Finally, it should be noted that much digital circuit complexity can be saved by combining the digital low-pass filter with the re-sampling block to directly produce the down sampled signal. It is of interest to look at what element most strongly affects the linearity of this oversampling A/D system. Setting all of the coefficients to 1, and the quantization error from the first stage is completely cancelled at the modulator output when the second order feedback DAC gain is set to 1. By changing the DAC gain, a comparison of immunity to gain mismatch effects can be simulated.

Fig. 41 The Simulink model of conventional 1-1 modulator structure

The new proposed MASH structure of Simulink diagram is shown in Fig. 42. In order to ignore the timing switch, the double number of integrators and comparators are applied in Simulink model. Note that the same number of OPAMPs and comparators are used on chip actually by using time divided technique. The (A1) and (A2) modulators are used the same OPAMPs and comparators; the (B1) and (B2) modulators are used the same OPAMPs and comparators. A sampling period is divided by timing switch into 2 section periods. The input signal is sent into (A1) and (B1) at the same time during section period 1. After integrating and quantizing, the timing is into section period 2. Let the output data of (A1) and (B1) be intercrossed, the output of (A1) is sent to (B2) and the output of (B1) is sent to (A2). The mismatch error can be compensated by intercrossing the data path, the transfer function of new proposed MASH is list below again.

Y(z)= ^{1 2 -2 1 2 -1}

( )

⁽

⁾

K +K K -K K K

z X(z)+ z 1-z Q -Q + (1-z ) Q + (1-z ) Q

2 2 2 ′ 2 ′ (40)

The first order quantization error can be minimum by (K1-K2)×(Q1-Q2) which have been discussed in chapter 2.3.

Fig. 42 The Simulink model of new proposed 1-1 modulator structure

The Matlab (Simulink) simulation results between conventional MASH and new proposed MASH is shown in Fig. 43 and Fig. 44. The mismatch errors have rise the noise floor and reduced the SNR in conventional MASH which is shown in Fig. 43(b). Let’s take a look at Fig. 44, just a little difference can be found. A successful result is proved that the new proposed MASH can suppress the SNR degradation with mismatch effect.

Fig. 43 The Simulink simulation results of conventional MASH (a).No mismatch (b).With 20% mismatch

Fig. 44 The Simulink simulation results of new proposed MASH (a).No mismatch (b).With 20% mismatch

The comparison of immunity to mismatch effect with all kinds of structure is depicted in Fig. 45. An interesting thing is happened in the simulation results of new proposed MASH.

The SNR is better with a little mismatch. Due to it is supposed that no any variance is produced by behavior simulation. Another inference is proposed here and the transfer function must be list again.

Fig. 45 The Simulink simulation results between different mismatch (Comparison of immunity to mismatch effects)[3]

Y(z)=^{K +K1}₂ ^{2 z X(z)+-2 K -K1}₂ ^{2 z 1-z-1}

( )

⁽

⁾

The first-order quantization errors have been discussed in previous chapter. Now the second-order quantization errors are focused. We know that quantization error have two directions (+ and -) based on original signal, and the phase of quantization error is signal dependant. It can supposed that Q1 and Q2 are same phase due to the two modulators have the same input signal, but Q1’ and Q2’ can not be supposed to be the same phase. This is said that Q1’ and Q2’ have opposite direction in some case. When this case happened, better SNR can be found which is depicted in Fig. 45.

3.3.2 Hspice simulation results

After behavior simulation by Matlab Simulink, it is proved that the new proposed MASH has immunity to mismatch effects. The Hspice simulation results by circuit achievement are discussed here. Only modulator part is implemented to the chip, because decimator part can be done by DSP processor. The plan of this chip is only PCM (pulse code modulation) data output then calculate output data by Matlab (including math calculation of digital cancellation and plot the spectrum by FFT then measure SNR finally).

Note that the system simulation need a long time by transition Hspice simulation, and the accurate option is also a key element to get better SNR. In order to shorten the simulation time, only the worse case is simulated in Hspice simulation by a few FFT points in spectrum.

The signal bandwidth is 22.05 kHz for 44.1 kHz Nyquist rate which is applied by MP3 coding.

The clock is 5.6448MHz for OSR (oversampling ratio) is 128. The calculation of SNR is specified the signal bandwidth without any weighting filter by Matlab.

A 20% area mismatch of capacitor is placed in feedback loop DAC on purpose. An external signal can switch it from 20% mismatch to no mismatch. We can compare the mismatch effect by the measurement on chip.

Finally, the simulation results are summarized in Table III, and the specification is list as Table IV.

Table III Summary of simulation results

Pre-Sim Post-Sim

Conventional MASH(No mismatch) 78.9310 dB 75.1694 dB Conventional MASH(20% mismatch) 74.6885 dB 70.4242 dB New MASH(No mismatch) 78.5209 dB 75.2846 dB New MASH(20% mismatch) 78.4780 dB 74.5603 dB

Table IV Summary of specification

Technology TSMC 0.35um 2P4M Supply voltage Vdd=DVdd=IOVdd=3v

Bandwidth 22.05kHz