Digital Error Correction

In the practical pipelined ADC design, there is a lot of non-linearity effect which need to be reduced to the tolerable level. A number of error correction techniques have been developed to make high resolution analog-to-digital converter. The Redundant-Sign-Digit-Coding (RSD) is a digital correct algorithm which is easily implemented in digital circuits. It usually uses to overcome the comparator error. The amount of redundancy is commonly referred as 0.5 bits. This technique can relax the accuracy of the sub-ADC and keeping the gain of the stage low. For example, a 1.5 bit/stage MDAC output 2 bit digital code, but the gain of the MDAC is two, not four (2²).

The typical output signal range of each MDAC stage is the same with the input signal range to reduce design difficulty. Figure 3.6 (a) shows the typical transfer curve of a 2 bit/stage from input to output. The comparator offset and the gain error cause over-range problems, as shown in Figure 3.6 (b) (c). This over-range error may cause the missing code at ADC output. Therefore, we need to reduce the gain of the inter

stage and add the tolerance of comparator.

Figure 3.6 (a) Ideal transfer curve of a 2/stage with (b) Gain error (c) Comparator offset

The comparator offset usually is due to the noise and the process variations. The decision level may be shifted right (a positive offset) or left (a negative offset). It may make the output code of the MDAC greater or smaller than the ideal output code. An addition and a subtraction of the output are used to avoid this error. But it is hard to determine that the comparator offset is positive or negative. Thus we can shift right the decision level by Vref/4. The digital output code is always less than or equal to its ideal value if the comparator offset can shift the decision levels back to the left by no more than Vref/4. So we need only an addition to correct the output code. It only requires a small adder in digital domain. And reducing the inter stage gain half and

shifting down the output voltage Vref/2 is used to remain within the conversion range of the next stage from -Vref to Vref. This transfer curve is illustrated in Figure 3.7. The dashed line is the transfer curve of 2bit stage and the solid is the modify curve. Figure 3.7 indicates that we need to correct the code in gray area by using additions. Because the modify curve with non-ideal offset has no over-range problem and require only addition correction between two original decision level. The maximum tolerable offset of the comparator is ±Vref/4.

Figure 3.7 The modify 2bit/stage transfer curve

Reconstruction of the redundant sign digit code outputs is performed by adding up the properly delayed stage outputs with one-bit overlap. Figure 3.8 is an example of 2b RSD correction of 8 bit output. The LSB of stage i is added to the MSB of the stage i-1. It can be easily implemented with full adder. Thus the extra hardware caused by the error correction is very small. The 1.5 bit architecture can remove the top decision level at 3Vref/4, because the correction range is ±Vref/4, and the decision

level is Vref/4 below full scale. And the calibration technique can correct the code at output. Figure 3.9 shows the transfer curve of 1.5 bit/stage. It is called as the 1.5 bit/stage architecture because the output code of each stage miss (11)2. The reside transfer function of 1.5 bit/stage architecture is

=

where DOUT is the output code for the stage. Because the output of each stage are (00)2, (01)2, and (10)2, the 8bit ADC output code (11111111)2 is missing. Thus the last stage should be the real 2bit flash ADC for eliminating the error. This 2bit flash ADC’s decision level is at -Vref/2, 0, and Vref/2, and output code is (00)2, (01)2, (10)2, and (11)2. [2] [16] [18] [19]

Figure 3.8 2 bit redundant sign digital correction

Figure 3.9 1.5 bit transfer curve

An ideal behavioral model of an 8bit pipelined ADC with 1.5 bit/stage architecture is constructed by Matlab as discussed above. All parameters of the system are assumed ideal except the comparator offsets. We can observe how comparator offsets affect the output code of the system with digital error correction. First we assume the comparator in the real systems is symmetrical, so the decision level of the MDAC stage can be Vref/4+Voffset and -Vref/4-Voffset. The simulation result is illustrated in Figure 3.10. And the INL analysis is plotted in Figure 3.11.

(a) (b)

(c)

Figure 3.10 the effect of comparator offsets for the pipelined ADC with (a) offset=0 (ideal) (b) offset=0.2 Vref (c) offset=0.3 Vref

(a)

(b)

Figure 3.11 INL of the pipelined ADC with comparator offset = (a) 0.2 Vref (b) 0.3 Vref

We can find that comparator offsets less than Vref/4 do not affect the linearity of ADC output, but it increases INL. If the comparator offset is larger than Vref/4, the missing codes occur ( DNL(i)=-1 ). For example, there are 28 missing codes in ADC output, shown in Figure 3.10 (c).

We can find that the Redundant-Sign-Digit-Coding provides the tolerance for comparator offset. If the ADC uses redundancy and digital correction, the effect of stage resolution on linearity is small. The comparator requirements are also relaxed, and reducing the inter stage gain allow higher speed due to the fundamental gain bandwidth tradeoff of amplifiers. The architecture of 1.5 bit/stage is shown to be effective in high throughput.