2 1 full swing
3.4 Non-ideal Considerations and Stage Requirement
Errors introduced by practical circuits are important because these errors limit the maximum performance of the ADC. In this section, an analysis of op-amp settling behavior for gain and speed is considered. And the capacitor size is considered for noise and mismatch error.
3.4.1 Residue Amplifier Gain Error
The most critical block of a pipelined stage is the multiplying D/A converter (MDAC). Figure 3.12 shows the MDAC operation from sampling phase to holding phase in 1.5 bit/stage. The finite DC gain error increases the error of analog signal. It may cause the DNL of the ADC. We can use the charge conservation principle to analysis the effect of a finite DC open-loop gain.
During sampling phase, the input signal is sampled into both capacitors CS and CF. The total charge is Vin(CS +CF). During the holding phase, the charge on CS and CF redistributes follows:
Figure 3.12 the MDAC operation
( ) ( ) ( )
IN S F DAC − S OUT − F − P
V C + C = V − V C + V − V C − V C
(21) where the CP is the parasitic capacitance at the op-amp input, and V- is the voltage of the inverting input of the op-amp. Then we can get(
S F)
S(
S F PThe feedback f during the holding phase is given by
F
s F P
f C
C C C
= + +
(22)And the voltage of the inverting input of the finite gain A op-amp is
V
outV
−= − A
(23)Finally, we can get an approximate Equation (24) by combining Equation (21), (22), and (23).
Assuming that CS and CF are perfectly matched,
(2 )(1 1 )
out in DAC
V V V
= − − Af
(25)the error is approximately 1/(Af). In order to achieve N-bit linearity, this error should be less than 0.5/2N (0.5LSB) to prevent any missing code. Thus the requirement on the DC gain is given by
2
N 1A f
>
+ (26)In this design, for an 8-bit ADC, the output of MDAC in the first stage constitutes the input of the following 6 stages. The maximum tolerable DNL is 0.5 LSB at 7 bit level.
We can derive that the minimum required A is 54.18dB when CP is zero. [16] [17]
3.4.2 Finite Settling Time of Op-amp
The settling time of the op-amp limits the ADC conversion speed. The analog signal must settle before next stage is holding. In section 3.2, the time constant is given by Equation (13). It assumes the settling behavior as single pole system and only time constant effect. But the system need more time to be settling by the slew-rate limited transient response. Briefly we can assume the slew-rate limited transient response took 1/3 of the settling time. Equation (13) can be re-written
= t
(N+1) ln2
τ ⋅
(27)Where t is the time used for time constant limit can be settling. During the holding phase, the close-loop bandwidth is f×ωu, where ωu is the unity-gain frequency of op-amp. Therefore, the unity gain frequency of op-amp can be found:
( 1) ln
As the slewing took one third of the settling time, the remaining time for the
exponential settling is t = T/3 = 1/(3 fS). For t=6ns and Cp=Cs/4, the unity gain frequency of the op-amp must be greater than 330MHz which feedback factor is 4/9 for 7 bit level in this design. During the slew-rate limited transient response period, the critical case is full range swing in 3ns. We can calculate the requirement of slew rate as
0.5 167 / 3
SlewRate V V us
= ns = (29)
3.4.3 Capacitor Mismatch and Size
In switched capacitor MDAC, mismatch of the sampling CS and CF capacitors is a major error source. The matched capacitors play an important role in medium ADC design. In the previous section, the capacitors are assumed to be perfectly matched.
From Equation (24), when A is infinite and let CS=C+ΔC/2, CF=C-ΔC/2, and CS/CF~1+ΔC/2, the effect of a capacitor mismatch is given by:
(2 ) (1 )
the approximation holds if C 1 C
Δ << . It given that ΔC/C of each capacitor must be
less 1/2N to ensure that ΔVout is always less than an LSB.
Another consideration of capacitor is the thermal noise. A certain minimum signal capacitor size is needed to maintain adequate noise performance and dynamic range. In switch capacitor pipelined ADC, the dominating thermal noise components are the noise of the op-amp and sampling circuit. The sampling circuit is used to sample the input signal onto a sampling capacitor. The source of thermal noise is commonly referred to as kT/C noise because the noise power is proportional to kT/C where C is the size of the sample capacitor, k is Boltzmann’s constant, and T is the absolute temperature. The op-amp also contributes thermal noise degradation to the signal being processed. Although there is no general expression for the type of the
noise, in ADC based on op-amp, it is found that it is roughly equal to the switched-capacitor noise. Thus the total noise voltage introduced in an ADC stage can be approximated as
2
N
V kT
≈ C
(31)If we make the thermal noise equal to quantization noise, we can get
2 2
The minimum capacitor size for 8 bit resolution is 0.006pF for Vfull-swing is 1V. Thus we can know that the SNR is dominated by the quantization noise for medium resolution ADC. Capacitor is found that satisfies the bandwidth requirement, and capacitor matching requirement. If the capacitor size is too large, the op-amp might not to reach the required speed. If the size is too small, the clock feed-through and charge-sharing effect will be worse. In this design, we choose the sampling capacitor size is 0.8pF for matching consideration. [20]
3.4.4 Aperture Uncertainty
In any sampling circuit, electronic noise causes random timing variations in the actual sampling clock edge. The effect of the aperture uncertainty comes about because an ADC does not sample the input at precisely equal time-intervals, as shown in Figure 3.13. It adds noise to samples, especially if dVin/dt is large. The worst-case voltage error due to the aperture jitter corresponds to sampling a sinusoidal waveform with the Nyquist frequency, which is fS/2, for example a full-scale signal
( )
full swingsin(
S)
v t = V
−π f t
(33)The maximum error will occur when attempting to sample the signal v(t) at its zero-crossing, where its derivative gives the maximum slope of the signal