4 Circuit Design
4.6 Simulated Result of Pipelined ADC with Power Noise
There are both digital circuit and analog circuit in a pipelined ADC. The power noise due to the digital circuit impacts the analog circuit performance. Thus we use the separated power line to reduce the effect of the power noise. But the substrate noise still impacts the analog circuit performance. In the section, we add a pad which is shown in Figure 4.24 to simulate power noise at ground and VDD and the dirty power is shown in Figure 4.25. Figure 4.26 shows the DNL and INL. The simulation result is worse than ideal power line. Figure 4.27 shows the FFT spectrum with input signal at 292.96875 KHz. The SNDR is 49.503dB, and the SFDR is 62.018dB. It is worse than ideal case, but this ADC still can archive 8 bit resolution in this noisy environment.
Figure 4.24 The simulated power PAD
Figure 4.25 Power noise
(a) (b)
Figure 4.26 Simulated results of the pipelined ADC with power noise (a) DNL (b) INL
Figure 4.27 512 points FFT spectrum of the pipelined ADC at 292.96875KHz input signal
5 Conclusions
5.1 Conclusion
An 8 bit pipelined analog-to-digital has been designed and simulated in TSMC CMOS 0.35um 2P4M technology. Based on the analysis and simulation results, the summary is as follows:
1. The error due to the mismatch of devices dominates the ADC performance in low-to-medium resolution ADC, especially the capacitor matching in MDAC.
2. The 1.5 bit/stage architecture is adopted for high speed ADC that data latency is of little concern. It can reduce the requirement of the op-amp in switched capacitor.
3. The dynamic comparator provides high conversion speed and low capacitance loading. But it introduces a kickback noise to the analog signal path. In high speed ADCs, the noise must be reducing. The improved way is using static comparator or adding a new advanced clock.
4. The digital circuits inject noise into the substrate and power line, especially the clock generator. The analog and digital power line must be separated. The cross point of analog signal path and digital signal path must be reduced and design carefully in the layout, especially the input of the op-amp.
5. The higher sample rate pipelined ADC required high speed op-amp. The
telescopic op-amp will be required more current and device size to support high sampling rate. The parasitic capacitor at the input of the op-amp is also increased.
Thus the gain of the op-amp is required more. The simple telescopic op-amp may be not adopted for more high speed ADC.
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