Chapter 2 The Fundamentals of Low Noise Amplifier
2.4 Direct Conversion Receivers
Fig. 2.5 is a simple direct conversion receiver, where the LO frequency is equal to the input carrier frequency. The circuit of Fig. 2.5(a) operates properly only with double-sideband AM signals because it overlaps positive and negative parts of the input spectrum. For frequency- and phase-modulated signals, the down-conversion must provide quadrature outputs [Fig. 2.5(b)] so as to avoid loss of information. This is because the two sides of FM or QPSK spectra carry different information and must be separated into quadrature phases in translation to zero frequency.
The simplicity of the direct conversion architecture offers two important advantages. First, the problem of image is circumvented because ωIF=0. As a result, no image filter is required, and the LNA need not drive a 50Ω load. Second, the IF SAW filter and subsequent down-conversion stages are replaced with low pass filters and base-band amplifiers that are amenable to monolithic integration. But this architecture has a DC offset problem. We will discuss this issue in detail below.
DC Offsets problem:
Since in a direct conversion topology the downconverted band extends to zero frequency, extraneous offset voltages can corrupt the signal and, more importantly, saturate the following stages. To understand the origin and impact of offsets, consider the receiver shown in Fig. 2.6, where the LPF is followed by an amplifier and an A/D
converter. Let us make two observations. First, the isolation between the LO port and the inputs of the mixer and LNA is not infinite; that is, a finite amount of feedthrough exists from the LO port to points A and B [Fig. 2.6(a)]. Called “ LO leakage,” this effect arises from capacitive and substrate coupling and, if the LO signal is provided externally, bond wire coupling. The leakage signal appearing at the inputs of the LNA and the mixer is now mixed with the LO signal, thus producing a DC component at point C. This phenomenon is called “self-mixing.” A similar effect occurs if a large interferer leaks from the LNA or mixer input to the LO port and is multiplied by itself [Fig. 2.6(b)]. Second, the total gain from the antenna to point X is typically around 80 to 100dB so as to amplify the microvolt input signal to a level that can be digitized by a low cost, low power ADC. Of this gain, typically 25 to 30dB is contributed by the LNA/mixer combination.
Fig. 2.5 (a) Simple direct conversion receiver
(b) Direct conversion receiver with Quadrature downconversion
Fig. 2.6 Self-mixing of (a) LO Signal (b) A strong interferer
Chapter 3
Ultra-wideband Low Noise Amplifier
This chapter describes principle of Ultra Wideband Low Noise Amplifier and this chip fabricated by TSMC 0.18μm RF CMOS technology.
3.1 Introduction
Due to data communication capacity increase progressively and portable, the wide bandwidth and low power are the urgent requirements. Therefore, FCC allocated 7500MHz of spectrum for unlicensed use of UWB devices in 3.1 to 10.6GHz frequency band and defined power consumption must less than 250mW. The first stage of the UWB receiver front end is LNA. There are many critical parameters in design ultra wideband amplifier, such as broadband flat gain, good linearity, good noise performance, good group delay, and good input matching from dc to high frequency. Distributed Amplifier (DA) is a popular solution to implement ultra wideband amplifier. DA usually employs transmission line to transfer signal to next stage without loss. Its frequency range can extend to high frequency, but power consumption and die size are very large. Another method is used chebyshev band-pass filter to achieve broadband matching [6]. This method’s don’t consume more power consumption to achieve broadband function. In next chapter, we will use this method to implement a mixer. In this chapter, we employ resistance negative feedback to achieve broadband matching and use skill of pain peaking method to compensate the gain loss at high frequency.
3.2 Principle of the Circuit Design
In this section, the design of ultra wideband low noise amplifier is presented. Fig.
3.1 is the schematic of ultra-wideband low noise amplifier. The circuit includes two stage common source amplifiers. M1 is the input transconductance. The resistors, RF1
and RF2 provide input and output matching and self-biasing. The transistor M2 is the second stage transconductance. It provides better isolation and system LNA transconductance gain improve.
Fig. 3.1 Schematic of ultra wideband low noise amplifier
3.2.1 Input Matching principle
Fig. 3.2 Input matching of ultra wideband LNA
without L_deg
Fig. 3.3 Input small signal model and L-deg effect of ultra wideband LNA The LNA input stage is shown as the Fig. 3.2, and Fig. 3.3 is equivalent circuit.
The input matching network has combined two matching methods. One is inductive source degeneration matching, and another one is resistive negative feedback. Using this method, the input matching can rather extend to high frequency as Fig. 3.3’s smith chart. If the Cgd is neglected, the input impedance can be expressed as the following
In the low frequency, the input impedance is
in1 =0 fm F1
v1
Z | Z = R
1-A (s)
ω ≈ (3-2) Depending on equation (3-2), we can observe the resistance is determined by RF1 at the low frequency.
At the resonance frequency, Zin1 can express as the following equation.
o
Depending on equation (3-3), we can observe the Zin1≈ωT s1L at the resonance frequency. Since these two levels Zin1(ω=0) and Zin1(ω=ω0) give the impedance range as the frequency sweeps, adjusting both levels near 50Ω shall ensure good S11 over the entire frequency band.
3.2.2 Ultra wideband gain flatness analysis
Fig. 3.4 Small signal circuit of ultra wideband low noise amplifier
with L_deg without L_deg
2 4 6 8
0 10
-20 -15 -10
-25 -5
Freq (GHz)
S11(dB)
Fig. 3.5 S11 with and without L_deg input matching
with series peaking
Fig. 3.6 Gm with and without series peaking of second stage
Fig. 3.7 Frequency response of ultra wideband low noise amplifier
The Fig. 3.4 is the small signal circuit of ultra wideband amplifier. All the analysis, the Cgd is ignored. The complete voltage gain of ultra wideband LNA can be expressed as
where
where Rs is source impedance. Gm1 is the first stage of M1 transconductance. Gm2 is the second stage of M2 transconductance. Zin1 is the input stage impedance. Zin2 is the second stage input impedance. RL is the load impedance. ω ωo1, o2 are the resonance frequency of the first and second stage.
The purpose of the first stage of LNA let input matching S11 less than 10dB from dc to 10GHz which is described in section 3.2.1. According to the equation (3-5),
o1=1/ (L +L ) Cg1 s1 gs1
ω ⋅ , we can decide the Lg1=0.85nH and Ls1=0.7nH resonance at 10GHz. The Fig. 3.5 shows the condition with and without L_deg and the Gm1’s frequency response is shown in Fig. 3.7(a). Due to Gm1 frequency response is not flatness, we add another stage to compensate high frequency transconductance gain.
The Gm2 frequency response is shown as Fig. 3.6. The Lg2=1.2nH and Ls2=0.4nH resonance at 10GHz. The transconductance Gm2 is higher than low frequency at resonance frequency. According to (3-4), the voltage gain is Gm1*Gm2*output resistive. The Fig. 3.7 (c) is the frequency response after the gain compensation. The Gm1, Gm2 can be derived as
where o1 1
3.3 Chip Implementation and Measured Result
3.3.1 Microphotograph of Chip
A microphotograph of the UWB LNA circuit is shown in Figure3.6. The circuit is fabricated in the TSMC 0.18µm CMOS technology. The die area including bonding pads is 0.873 mm by 0.636 mm.
Fig. 3.8 Microphotograph of UWB LNA Lg1 Lg2
3.3.2 Measurement and Simulation Result
Measurement is conducted by on-wafer RF probing. Measured S-parameters are plotted in Fig. 3.7 to Fig. 3.14, together with simulation results and troubleshooting for comparison. The solid line is the measured data. The circle plot is the simulation result.
The square plot is the troubleshooting result.
The measured power gain S21 achieves the maximum value of 6.3dB at 100MHz.
It is almost matched the simulation result at low frequency. Above 6GHz, the measured power gain start to decrease and deviate from the simulation result. The measured 3dB bandwidth range is from 100MHz to 6.6GHz. Because of the lower gain measured in high frequency, the higher noise figure is measured. The Fig. 3.11 is shown the condition. The difference of measured data and simulation result on the S21 may be due to the lower transconductance. From the equation ωT=g /Cm gs, we can understand the transconductance and cutoff frequency is determined by transistor’s input capacitor. A capacitor (Cp=150fF) is included between the gate and source of the transistor. It is in order to reduce the input transconductance of the transistor for troubleshooting. In the Fig. 3.7, the square plot is the troubleshooting result which is similar to the measured result. The other S-parameters such as S11, S22 and S12 are similar to the simulation result.
The Fig. 3.11 is the measured and simulation result of noise figure. The measured data is above the simulation result. The average value of noise figure is 8.1dB. Discrepancy at high frequency may be the degradation of S21 and inaccurate noise model. The linearity analysis is conducted by the two-tone test. The Fig. 3.12 is the linearity measured data at 5GHz. The Fig. 3.13 is the IIP3 measured data at 3~8GHz. The Fig. 3.14 is the group delay simulation and measured data. The simulation result is 67~71ps. The measured result is 40~83ps. The total power of the
UWB LNA is 16.2mW with a power supply 1.8V. The table 3.1 is the summary of measured performance and comparison to other wideband amplifier.
Measured |S21|
Fig. 3.9 S21 simulation and measured result of UWB LNA
Measured |S11|
Fig. 3.10 S11 simulation and measured result of UWB LNA
Measured |S22|
Fig. 3.11 S22 simulation and measured result of UWB LNA
Measured |S12|
Fig. 3.12 S12 simulation and measured result of UWB LNA
Measured Noise Figure
Fig. 3.13 Noise Figure simulation and measured result of UWB LNA
IIP3= -1.5dBm
Fig. 3.14 Linearity at 5GHz of UWB LNA
4 5 6 7
3 8
-2 -1 0
-3 1
Freq (GHz)
IIP 3 ( d B m )
Fig. 3.15 Linearity measured result versus frequency
Measured Group Delay
Wt decrease+variation(Coner=SS) Simulation Group Delay
2.0E9 4.0E9 6.0E9 8.0E9 1.0E10
0.0 1.2E10
2.0E-11 4.0E-11 6.0E-11 8.0E-11 1.0E-10
0.0 1.2E-10
Freq(Hz)
Group Delay
Fig. 3.16 Group Delay simulation and measured result of UWB LNA
TABLE 3.1 Summary of measured performance and comparison to other wideband amplifier
BW[GHz] Gmax[dB] S11[dB] NFmin[dB] IIP3[dBm] Area[mm2] P[mW]
Simulation 0.1-10 6.7 <-10 4.1 -3.1 0.54 16.2
Measured 0.1-6.6 6.2 <-10 6.5 -1.6 0.54 16.2 [7] 2.9-9.2 9.3 <-9.9 4.0 -6.7 1.1 9 [8] 0.6-22 7.3 <-8 4.3 N/A 1.35 52 [9] 0.5-4 6.5 <-7 5.4 N/A 0.62 83.4 [10] 1.5-7.5 5.5 <-9.5 8.5 N/A 2.86 216
3.4 Conclusion
In this work, we design an ultra wideband low noise amplifier for the receiver path of UWB system which is used the standard TSMC 0.18µm CMOS process. This circuit uses the feedback resistor and inductive degeneration to achieve the input, output broadband matching. Between two stages, we add an inductor to compensation the high frequency transconductance. The measured result shows that S11, S22 and S12 parameters are similar to simulation result. It shows the L-degeneration method is useful at this work. The measured 3dB frequency range is from 0.1 to 6.6GHz. The measured maximum power gain is 6.2dB. The average IIP3 is -1.6dB. The noise figure minimum is 6.5dB. From Table 3.1, the power consumption of our work is lower than other distributed amplifier [8,9,10] and die size is also small than others.
Chapter 4
A 3 ~ 8 GHz Direct Conversion Broadband Mixer
This chapter describes circuit design principle of a 3~8GHz direct conversion broadband mixer. And this chip fabricated by TSMC 0.18μm RF CMOS technology.
4.1 Introduction
Due to data communication capacity increase progressively, the wide bandwidth and low power are the urgent requirements.
Direct conversion receiver (DCR) is most popular architecture in recently years.
The frequency of RF signal is the same with the frequency of LO (local oscillator) signal, and down converts to around DC frequency. The homodyne receiver (DCR) offers two important advantages over a heterodyne receiver. First, there are no image problems, so image rejection filter is not required. Second, the SAW filter and subsequent down-conversion stages are replaced with low pass filter and baseband amplifiers that are amenable to monolithic integration. In general, the homodyne receiver just needs small chip area.
In this chapter, we employ chebyshev filter to design a 3~8GHz direct conversion mixer. Its advantage has easy to achieve high gain, broadband matching and doesn’t consume extra power but it needs large die size and accurate inductor model. Therefore, this mixer can receive signals from 3~8GHz and down convert to baseband signal directly. The extra current source is used to decrease the current of switch MOS, and increase the lower stage’s transconductance gain. An inductor adds to the inter-stage between the switch and transconductance stage whose the high frequency gain can be improved.
4.2 Principle of the Circuit Design
Fig. 4.1 Schematic of 3~8GHz direct conversion broadband mixer
In this section, the circuit design principle of 3~8GHz direct conversion mixer is presented. This circuit of mixer uses chebyshev filter design to achieve broadband matching. In section 4.2.1 will introduce the broadband matching. Inductor adds to the inter-stage between the switch and transconductance stage then the high frequency gain can be improved. In section 4.2.2 will introduce the inductive peaking function. In order to down covert the RF signal, the mixing stage is needed. In section 4.2.3 will introduce the mixing stage.
4.2.1 Input Broadband Matching
Fig. 4.2 shows the input impedance matching of this circuit. Input matching uses the chebyshev filter design. The filter design technique has two kinds of methods. One
is the image parameter method, and another one is insertion loss method [11]. In this work, we use insertion loss method to design filter. Insertion loss uses network synthesis techniques to design filters with a completely specified frequency response.
The design is simplified by beginning with low pass filter prototypes that are normalized in terms of impedance and frequency. Transformations are then applied to convert the prototype designs to the desired frequency range and impedance level. So, the insertion loss method is the most common technique to design filter. The Fig. 4.3 shows the filter design procedure of insertion loss method.
Fig. 4.2 The input impedance matching
Fig. 4.3 Insertion loss method design procedure
4.2.1.1 Low Pass Filter Prototype
In the insertion loss method a filter response is defined by its insertion loss, or power loss ratio, PLR:
LR 2
Power available from source 1
P = Power delivered to load =1 | ( ) |− Γω (4-1)
where | ( ) | = ( )Γω 2 Γω ⋅ Γ*( )= ( ) (- )= | (- ) |ω Γω ⋅ Γ ω Γ ω 2, so
Substituting this form in equation (4-1), we get
(4-3)
hus, for a filter to be physically realizable its power loss ratio must be of the form in
2
equation (4-3). Notice that specifying the power loss ratio simultaneously constrains the reflection coefficient, ( )Γω . We now discuss two practical filter responses below.
<1>Butterworth filter:
Butterworth response provides the flattest possible passband response for a given filter complexity, or order. For a low pass filter, it is specified by
2 2N
P =1+k (LR )
c
ω
ω (4-4)
where N is the order of the filter
then a sharper cutoff will result, although the passband response will have ripples of amplitude , as shown in Fig. 4.4, since TN(x) oscillates between ±1 for |x| 1.
Thus, determines the passband ripple level. For large x,
1 k+ 2 ≤
k 2 T (x) 1/2(2x)N N
Fig. 4.4 Butterworth and Chebyshev Low pass filter responses (N=3)
From the power loss ratio equation of butterworth and chebyshev filter, then we could derive the normalized element values of L and C of low pass filter prototype.
The element values for the ladder type circuits of Fig. 4.5 and the normalize values of L and C are presented in Table 4.1 and Table 4.2.
Fig. 4.5 Ladder circuits for Low pass filter prototypes and their element definitions
Table 4.1 Element values for Butterworth Low Pass Filter prototypes(g0=1,ωc=1)
N (order) g1 g2 g3 g4
1 2.0 1.0
2 1.4142 1.4142 1.0
3 1.0 2.0 1.0 1.0
Table 4.2 Element values for Chebyshev Low Pass Filter prototypes(g0=1,ωc=1) Ripple=0.5dB
N (order) g1 g2 g3 g4
1 0.6986 1.0
2 1.4029 0.7071 1.9841
3 1.5963 1.0967 1.5963 1.0
4.2.1.2 Impedance and Frequency Scaling
Impedance scaling: In the prototype design, the source and load resistances are
un ).
A ltiplying the impedances of the
prototype d . Then, if we let prim note im nce scale antities, we have the new filter compone given
(4-6) ity (expect for chebyshev filters with even N, which have nonunity load resistance
source resistance of R0 can be obtained by mu
esign by R0 es de peda d qu where L, C, and RL are the component values for the original prototype
Frequency scaling for low pass filters: To change the cutoff frequency of a low pass prototype from unity to ωc requires that we scale the frequency dependence of the filter by the factor 1/ωc, which is accomplished by replacing ω by ω/ωc:
c
ω ω
←ω (4-10) then the new power loss ratio will be
LR LR
c
P' ( )=P (ω ω )
ω (4-11) where ωc is the new cutoff frequency; cutoff occurs when ω/ωc = 1, or ω=ωc.
Therefore, the new element values are determined by applying the substitution of (4-10) to the series reactances, jωLk, and shunt susceptances, jωCk, of the prototype filter. Thus,
y scaling are required, thus the new value is
= ⇒ (4-13)
responses illustrated in Fig. 4.6. If ω1 and ω2 denote the edges of the passband, then a bandpass response can be obtained using th
4.2.1.3 Bandp
r designs can also be transformed to have the bandpass
e following frequency substitution:
0 0 1 0
the fractional bandwidth of the passband. The center frequency, ω0, could be chosen ω2, but the equations are simpler if it is chosen as
the low pass response of Fig. 4.5(a) as follows:
When is
as the arithmetic mean of ω1 and the geometric mean:
Then the transformation of (4-16) maps the bandpass characteristics of Fig. 4.5(b) to
0= 1 2
Fig. 4.6 (a) Low pass filter prototype
(b) Transformation to bandpass filter frequency response frequency response for ωc=1
The new filter elements are determined by using (4-16) in the expressions for the series reactance and shunt susceptances. Thus,
k 0 k k which shows that a series inductor, Lk , is transformed to a series LC circuit with element values,
ansformed to a shunt LC circuit with element values, which shows that a shunt capacitor, Ck , is tr
k
The low pass filter elements are thus converted to series resonant circuits (low impedance
impedance at resonance) in the shunt arms. Notice that both series and parallel resonator elements have a resonant frequency of ω0. The Fig. 4.7 shows the condition. The Fig. 4.8 is the
(
at resonance) in the series arms, and to parallel resonant circuits (high
complete circuit of low pass filter transformed to bandpass filter.
Fig. 4.7 Components transformation of low pass filter transfer to bandpass filter (a) Series inductor transformed to series LC
(b) Parallel capacitor transformed to shunt LC
Fig. 4.8 Complete circuit of bandpass filter tansformation
4.
end mixer which help us
to understan ixer is the same as the
single end. In this double balanced gilbert mixer, we put an inductor (Lp1) between
2.2 Inductive-peaking Function
The Fig. 4.9 is the inductive peaking function of single d this function [12,13]. The differential pair m
the transconductance stage and mixing stage in order to enhance the high frequency gain. The equivalent circuit is shown in Fig. 4.10. The capacitor (Cp) and resistor (R) is the equivalent model that looking into the mixing stage. The capacitor (CL) is the equivalent element which looking into the drain node of transconductance stage. As the Fig. 4.10(a), we can derive
out in
L p
V =I R
sR(C +C )+1
⋅ (4-26)
where
L p
R (C +C )⋅
(4-27) is shown the pole location would be decrease the signal at high frequency.
As the Fig. 4.10(b) shown, we can derive relationship of current and voltage with inductive peaking function.
= -1
ω ( pole ) (4-27)
out
p L p1 L p1 p L
V =I ⋅ R (4-28)
We can adjust Lp1 to enhance transconductance gain (Gm) at high frequency. The Fig.
4.10 shows the result that with
in s RC C L +s C L +sR(C +C )+13 2
and without inductive peaking.
Fig. 4.9 The inductive peaking function
Fig. 4.10 (a) without inductive peaking (b) with inductive peaking
L-peaking non L-peaking
2 4 6 8
0 10
0.01 0.02 0.03 0.04
0.00 0.05
Freq (GHz)
Gm (A/V)
Fig. 4.11 Gm curve with and without inductive peaking
4.2.3 Switching Stage of the 3~8 GHz Direct Conversion Mixer
The Fig. 4.12 is the mixing stage of this mixer. The main noise source of the mixer comes from the flicker noise. The (4-29) is the noise current representation.
m2
2 2
n 2 T
ox
K g K
i f
f WLC f ω
= ⋅ ⋅ ∆ ≈ ⋅ ⋅ ⋅ ∆A f (4-29)
From the equation (4-29), we would observe two conditions to reduce noise. One is increase the transistor area size, and another one is decrease the transistor’s gm. The smaller gm means the less current flow of the transistor. The bias current of the transistor set to about 500μA which is around the saturation region. It can improve the noise figure that bias at around the saturation region. The current source is used to
From the equation (4-29), we would observe two conditions to reduce noise. One is increase the transistor area size, and another one is decrease the transistor’s gm. The smaller gm means the less current flow of the transistor. The bias current of the transistor set to about 500μA which is around the saturation region. It can improve the noise figure that bias at around the saturation region. The current source is used to