Dynamic Range

The dynamic range (DR) is defined as the ratio of the maximum allowed input signal level to the minimum input signal level at which the signal quality is maintained [2], [3]. Two definitions of dynamic range are adopted to evaluate the dynamic performance, as shown in Fig. 2.13. These are called spurious-free dynamic range (SFDR) and blocking dynamic range (BDR). For both definitions of dynamic range, the minimum boundary is defined as the noise floor plus SNR_min. The spurious-free dynamic range (SFDR) and blocking dynamic range (BDR) are interpreted as follows.

(a). Spurious-free dynamic range (SFDR).

The upper bound of SFDR is defined as an input two-tone test signal at which the third-order inter-modulation (IM3) distortion products do not exceed the noise floor, as displayed in Fig. 2.14.

P in (d B m )

Fig. 2.14 Upper band of SFDR

From Eqs. (2.9) and (2.17), a quick calculation of IM3 is,

Substituting Eq. (2.25) into Eq. (2.35) and taking logarithms, yields,

2

where Ain is the input level at each frequency.

2 2

PIM_, represents the power of the IM3 components at the output.

Since P_out =P_in +G and P_IM,out =P_IM,in +G, where G is the circuit gain,

2 3 3Pⁱⁿ P^IM,in

IIP −

= (2.39)

The input level for the IM products should become equal to the noise floor.

Thus,

The relationship between SFDR and SNRmin is thus obtained.

min

(b). Blocking dynamic range (SFDR)

The upper boundary of BDR is the P-1dB compression point, and the overall gain declines to zero since the small signal gain is attenuated by large interference.

Figure 2.13 is used to obtain the equation for calculating BDR.

1dB nF min

BDR =P₋ −P −SNR (2.42) Attempt to find out the relationship between SFDR and BDR.

Equations (2.26) and (2.41) are manipulated to yield, .

1_dB 3 9.64

P₋ ≅IIP − dB (2.43)

min

3 3( )

2 ^nf

IIP = SFDR+SNR +P (2.44)

Thus,

1 min

min

3 1

2 2 9.64

dB nF

BDR P P SNR

SFDR SNR dB

= − −

⇒ = + − (2.45)

Both compression and blocking reduce the desired signal and then SNR is degraded.

Chapter 3.

Design of a 5.5 GHz CMOS Active Mixer

The accuracy of MOSFET model for simulating high frequency characteristic will have direct and dramatic impact on the RF circuit design and performance optimization. A compact CMOS model should cover both active and passive devices, such as MOS transistors, varactors, capacitors, inductors, and resistors. An accurate compact RF CMOS model can help facilitate RF circuit design with increased first-pass success. In this thesis, TSMC 0.18 μ m mixed signal 1P6M silicide 1.8V/3.3V RF CMOS models are used in circuit simulation for the design of a new down-conversion mixer. This chapter discusses the trade-off of RF performance with the minimum noise figure (NFmin), conversion gain, and linearity.

A CMOS based RF amplifier or mixer circuit design can adopt common source and common gate for high-frequency applications. The common source exhibits a high conversion gain, and wide matching bandwidth in the deep-submicron process.

The mixer design focuses on the trade-off between various performance parameters, such as the conversion gain, linearity, and flicker noise in the direct conversion receiver.

3.1 Mixer

In general, the basic mixer architectures can be classified as two major categories, one is the active mixer and another is the passiver mixer. The passive mixer has advantages over the active mixer, such as broadband and high speed due to much smaller junction capacitance, high linearity, dynamic range, and lower flicker noise. However, a passive mixer sometimes suffers disadvantages, such as unsuitability for integration in SoC, inherent conversion loss, poor port-to-port isolation, and high LO power requirement. In the following sections, mixers adopting various topologies will be introduced and discussed.

3.1.1 Passive Mixer

The passive mixer has advantages of high linearity, low noise, and low power.

However, the major penalty suffered by the passive mixer is the worse loss in conversion gain.

A passive mixer can utilize MOS transistors or diodes as the basic devices in its circuit architecture. Most of passive diode mixers adopt Schottky diodes as shown in Fig. 3.1(a), mainly because the Schottky diodes represent majority carrier devices, and are faster than p-n junction diodes. MOS transistor is an essential element in active mixers and may be used in passive mixers, as shown in Fig. 3.1(b).

The passive mixer integration in SoC is very difficult since the Balun circuit is

almost passive or includes a center-tapped transformer, whose integration into SoC will occupy a large area on the chip. The passive mixer is generally popular for applications demanding high-linearity, low-noise, and low-power-consumption.

`

`

180 Balun

IF

LO

Fig. 3.1(a) Passive (Diode) mixer

L O +

L O + L O

L O

-VI F

R F i n

Fig. 3.1(b) Passive (MOS) mixer

3.1.2 Active Mixer

Gilbert cell is the most popular architecture adopted to build an active mixer and the resulted mixer is generally named as a Gilbert mixer. Figure 3.2(a) and (b) show the single and double balanced mixers, respectively. The noise figure of a typical Gilbert mixer circuit is between around 8~15 dB.

LO + LO

-RF

r

Vcc

IF + IF +

R

^L

R

^L

M1 M2

M3

Fig. 3.2(a) Single Balanced Mixer

LO +

RF +

r

Vcc

LO +

LO

RF

-r

IF + IF +

R

^L

R

^L

M1 M2 M3 M4

M5 M6

Fig. 3.2(b) Double Balanced Gilbert Mixer

3.2 Design of Low-Power-Consumption Circuit with LC-Tank

The basic circuit topology of a Gilbert mixer is a kind of cascade architectures incorporating RF stage and LO stage. Therefore, the supply voltages required for a Gilbert mixer have to include one set for LO and another one for RF, as shown in Fig.

3.3. A simplified circuit block in Fig. 3.3 illustrates the DC voltage and RF ground

signal through the full lines and dotted lines, respectively. The voltage (Vcc) applied to the drain-to-source of each MOS must be at least double the minimum threshold voltage (Vth_min), i.e. Vcc > 2 Vth_minthe or minimum active component turn-on voltage (Von), i.e. Vcc > 2 Von, to turn on all active components in normal operation. The standard Gilbert mixer requires a high voltage to maintain all MOS transistors in normal operating region. As a result, this kind of mixers generally suffer large power consumption. The voltage scaling limitation as identified in RF and LO explains the major bottleneck for low power design using the conventional Gilbert mixer. This work presents a low-voltage circuit design technology based on the LC tank for a down-conversion mixer, as show in Fig 3.4. A voltage is applied to turn on the active MOS transistors of the LO and RF circuits based on LC-tank resonance.

Fig. 3.4. shows a simplified circuit block diagram for the proposed low voltage mixer. The LC tank is designed with a target resonance frequency at 5.5 GHz for wireless applications, such as in 802.11a. The new topology can reduce the total supply voltage and keep LO or RF active elements in normal turn-on. Ideally, the passive components such as inductors (L) or capacitors (C) employed in a LC tank have no power consumption. In this way, the proposed circuit topology can help voltage scaling and achieve low power operation. For the circuit topology adopting a LC tank, there is headroom voltage in the DC equivalent circuit. The bypass capacitor

is used to couple the RF signal from the RF MOS transistor output to the LO MOS

transistor input and isolate the DC bias between the LO and RF stages. The inductors and capacitors are assumed to be ideal and operate at the targetted RF frequency (ωRF).

When the LC-tank operates ideally with a parallel resonant frequency equal to ωRF ,

its equivalent circuit is like an open circuit for an RF signal. Therefore, the minimum supply voltage can be reduced to a turn-on voltage (Von) of a single transistor, supporting the circuit with a cascade architecture.

LO Element Circuit

RF Element Circuit Load Element Circuit

`

`

`

Vcc (DC)

`

`

RF (Gnd)

Fig. 3.3 A circuit block diagram for a typical Gilbert mixer with RF, LO, and load

stages and the applied DC and RF ground (Gnd).

LO Element Circuit

RF Element Circuit Load Element Circuit

`

`

Vcc (DC)

`

`

RF (Gnd)

LC-Tank Circuit LC-Tank

Circuit

`

Vcc (DC)

`

Bypass Capacitor

Fig. 3.4 A new topology using LC-tank and bypass capacitors for low voltage

operation in a Gilbert mixer with applied DC, RF and RF Gnd.

3.3 5.5 GHz CMOS Down-Conversion Mixer

This section describes the combination of multiple gate MOS transistors at RF input, inductors at RF output, LC tanks at both RF and LO stages, bypass capacitors between RF and LO, and output loading capacitors. The low voltage design built on a CMOS Gilbert cell mixer has been described above. In the following section, the design for down-conversion mixing will be described and discussed.

3.3.1 5.5GHz Down-Conversion Mixer Circuit Block

The 5.5 GHz down-conversion mixer circuit design comprises eight circuit blocks, as shown in Figure 3.5. They are the multiple-gate RF amplifier, the parallel LC-Tank, the bypass capacitor, the local switch, the load circuit, the RF Balun, the LO Balun, and the measuring circuit. QFN package is used to integrate the on-chip and off-chip circuits together.

Fig. 3.5 The proposed CMOS RF mixer block

Figure 3.5 presents the on-chip circuit blocks by solid lines blocks and the

off-chip circuit blocks by dotted lines. The off-chip circuits occupy a much larger area than the on-chip circuits. Figure 3.6 displays the whole chip circuit design.

Fig. 3.6 The proposed double balanced RF mixer circuit tolopogies

The CMOS mixer is designed with the low-voltage topology described above.

Figures 3.5 and 3.6 are used to represent each circuit block and its function in the proposed RF down-conversion mixer.

3.3.1.1 LC-Tanks

Manku first utilized LC-tanks for low-voltage design and reported the application in RF circuits [4]. In this work, LC tanks were designed with a target resonant frequency of 5.5 GHz, given by

C L f_o

⋅

= ⋅ π 2

1 . A LC tank, at its

resonance frequency, operates like an open circuit, as shown in Fig. 3.8. Therefore, LC-tank circuits may solve the problem generally suffered by the typical cascade circuit. The LC tanks required for this design were implemented by off-chip PCB layouts to meet the chip area constraint defined by CiC for test chip tape-out. For the LC tank design, the L value was determined from the calculated capacitance (C) value 0.352pF at a resonant frequency of 5.5 GHz. This thesis proposes RF output pull-up to supply the source low voltage, and LO pull-down to common ground [5].

L= 2.369 nH C= 0.352 pF

Fig. 3.7 LC-tanks circuits

R F S i g n a l D C C u r r e n t

D C C u r r e n t O p e n f o r

R F S i g n a l D C C u r r e n t

D C C u r r e n t O p e n f o r

R F S i g n a l

R F S i g n a l V c c

L C - T a n k t o M u l t i - g a t e c i r c u i t s

L O c i r c u i t t o L C - T a n k t o G N D

Fig. 3.8 Illustration the LC-tank circuit resonating frequency for RF signal and DC biasing status.

3.3.1.2 Multiple Gate MOS Transistors used in RF Input Stage

For an RF front end amplifier, such as used in LNA and mixer applications, high linearity at low power consumption is very important. Some possible solutions for low power design has been mentioned previously. Many approaches have been developed to compensate for non-linearity. For instance, MOSFET operation in a triode region has been used to improve the linearity of the main RF amplifier [5]. B.

Kim proposed a new linearization method that is based on multiple gate transistors for the RF amplifier and the mixer in common source integrated circuits [7].

The linearity of LNA and mixer is generally related to the drain current i_DS, as plotted in Fig. 3.9. The linearity model is derived mathematically using Taylor series and Eq. 2.7 is applied to expand the i_DS harmonic terms. Eq. 2.7 is rewritten here and i_DS, gm and νgs used instead of y(t), α and )x_i(t [7].

Thus,

⋅⋅

The coefficient of v³_gs is well known to be important in the distortion of third-order inter-modulation (IM3) harmonics of an RF mixer.

+

Figure 3.10 (a) indicates the circuit schematics of a multiple gate topology for circuit simulation to verify its effect on linearity. Fig. 3.10 (b) presents the secondary derivative of transconductances (g_m”) of Q1 and Q2, and Fig. 3.10(c) is the effective g_m” as a combination of Q1 and Q2. Sweeping the gate bias (V_gs) in the range of interest, the first transistor Q1 contributes negative transconductance ^"_,Q1

gm whereas the secondary transistor Q2 presents positive transconductance ^"_,Q2

gm . Through appropriate tuning on V_gs applied to Q1 and Q2, g_m” can be nearly eliminated in a certain region of V_gs and the nonlinearity can be reduced. Simulation was carried out to investigate the differences between the single gate and multiple gate structures in

terms of linearity, conversion gain, and power consumption. The comparison results as shown in Fig.3.6 indicate that multiple gate structure can offer better linearity and conversion gain but suffers larger power consumption. A trade-off must be made between the power consumption and linearity. Table 3.1 makes comparison between single gate and multiple gate structures in terms of power consumption, P-1dB, IIP3, conversion gain, single side band noise (SSB), and double side band noise (DSB) predicted by simulation..

Table 3.1 Comparison between the single gate and multiple gate performance Simulation Item (Without package model)

freq=5500 MHz, LO freq=5490 MHZ

Simple Gate Multiple Gate

Power Consumption 2.51 mW 2.81 mW

Linearity of P-1dB 3.689 dBm 6.188 dBm

Linearity of IIP3 8.2 dBm 12.2 dBm

Conversion Gain 13.318 dB 20.908 dB

Single Side Band Noise (LO=2.5 dBm)

26.571 dB 27.27 dB Double Side Band Noise (LO=2.5 dBm)

21.748 dB 21.52 dB

0 0

Vcc

RF_IN RF_IN

Vgs Vgs-Vm

C1 Q1

Nr=18

R1

Q2

Nr=20 C2

R2

Fig. 3.10 (a) Multiple gated circuit topology.

(b)

(c) Fig. 3.10 (b) ^"

gmof Q1 and Q2 (c) the effective ^"

gmresulted from combining Q1

Q1 Q2

3.3.1.3 RF Output Inductors

An inductor was in series with the RF output to increase the conversion gain available at mixer output [3]. The inductance of around 3.799 nH was adopted to optimize the output matching and improve the conversion gain. Then, the first phase design for RF stage is completed for the downconversion mixer as shown in Fig. 3.5.

This circuit design improves the linearity by using multiple gate amplifier at transconductance stage and increases the conversion gain by using inductors at RF output. However, a large chip area consumed by the inductors for output matching becomes a major penalty in terms of cost and chip area utilization.

Vdd_1.0 V

nr=50 L6 2.369 nH

L1

Fig. 3.11 Circuit schematics with RF amplifier, input and output Baluns for simulation and first phase design of the mixer

Figure 3.11 illustrates the circuit schematics for simulation. Fig. 3.12 indicates the input return loss S₁₁ and conversion gain S₂₁ simulated for the RF amplifier. In this design, the conversion gain S₂₁ at 5.5 GHz achieve the maximum value of around 10, and S₁₁ can be pushed to around –20 dB.

3 4 5 6 7 8 9

2 1 0

- 3 0 - 2 0 - 1 0 0

- 4 0 1 0

f r e q , G H z

dB(S(2,1))

dB(S(1,1))

Fig. 3.12. RF amplifier S11, S21 calculated by circuit simulation

3.3.1.4 Balun Circuit Design [5]

Differential (balanced) inputs and outputs generally required for RF ICs can be realized by direct-coupled stages made up of pairs of transistors. These differential inputs and outputs must often be interfaced to single-ended (unbalanced) connections.

The deep submicron CMOS process supports high-frequency active devices for RF applications, but the integration of high-quality passive components such as inductors, transformers, resistors and capacitors on a single chip is difficult because that passive devices generally occupy a large area. Although high-quality inductors and transformers have been accurately modeled and Balun applications have been

of the resistive losses from trace metals and substrate loss associated with the underlying Silicon substrate.

In this section, a lumped element Balun was designed providing an effective solution to RFIC interfacing, which can achieve low cost and less PCB space than alternatives such as a transformer or transmission line Balun [8]. A comparative monolithic transformer with two coupled inductors has a greater quality factor (Q) than LC-Balun in differential circuits [10]. However, an accurate modeling and parameter extraction for monolithic transformers or inductors are more difficult and require more extensive effort and time to achieve accurate measurement and simulation [9].

P1

P2

+ P3

-R

^F

V

^s

R

^L

L

L

C C

C C

Fig 3.13 RF LC Balun Circuit.

Fig. 3.13 shows the LC Balun circuit applied to RF and LO inputs. It is easily

designed and can be fabricated on-chip or off-chip on PCB. In this thesis, it is implemented on PCB, i.e. an off-chip approach.

A circuit analysis was done on the LC Balun to determine the L and C values.

The half-circuit theorem was applied to analyze the LC Balun circuit. In this way, the original LC circuit was partitioned to two identical half circuits, which are symmetric with respect to the source node.The circuit is therefore redrawn as shown in Fig. 3.14.

P1 P2

P3

R

^HF

=2 R

^F

R

^HL

=0.5 R

^L

L

C C

C C

R

^HL

=0.5 R

^L

R

^HF

=2 R

^F

L

C C

R

^HF

=2 R

^F

L R

^HL

=0.5 R

^L

Z

^IN

Fig. 3.14 Half-circuit equivalent circuit

Let ZIN=RHL and XL = XC. Calculate ZIN for the equivalent circuit, as shown in Fig.

( ) // The LC Balun circuit is designed for a band frequency of approximately 5.5GHz.

Figure 3.15 plots the frequency response of LC-Balun , indicating that the amplitude mismatch is below 0.1 dB and the phase error between port 2 and port 3 is less than 1.5^o.

Fig. 3.15 Frequency response of LC-Balun in terms of magnitude error and phase error.

3.3.1.5 LO Switching

RF mixer is a kind of nonlinear circuit applied for wireless communication. The

mixer functions as a multiplication circuit that multiplies the input signal by the LO signal. Therefore, the IF harmonic equationf_IF =mf_LO+nf_RF, is obtained where m and n are integers. In this work, a double balanced mixer was adopted to gain better linearity. Gilbert cell mixer was selected as the basic structure to build the switching stage. In the following, an introduction and circuit analysis will be done for single balanced and double balanced mixers, respectively.

3.3.1.5.1 Single Balanced Mixers

A single balanced mixer accommodates a single-ended RF signal and a differential LO signal. The circuit schematics of a single balanced mixer shown in Fig.

3.2(a) is redrawn in Fig. 3.16. The RF signal passes through the M1 transconductor stage, providing an amplified signal that converts a voltage signal to a current signal, and the current signal passes through the current commutating stage M2 and M3 (i.e., switching stage), yielding down-conversion or up-conversion frequency at the IF terminal.

LO + LO

-RF

r

Vcc

IF + IF +

r

Vcc

IF + IF +

R^L R^L

R^L R^L

r

+g^m M1 M

M2 M3

V^RF Is

Fig 3.16 Circuit schematics of a single balanced mixer and the equivalent circuit of the LO switch.

The Fourier series is adopted herein to analyze the signal, as shown in Fig. 3.17.

r

V

^LO

(t)

V

^LO1

(t)

V

^LO2

(t)

Fig. 3.17 LO switch waveform.

1 2

( ) ( ) ( )

LO LO LO

V t =V t +V t (3.4)

1

3.3.1.5.2 Double Balance Mixer - Gilbert Cell Mixer

In contrast with the single balanced mixer, a double balanced mixer adopts differential signals at both RF and LO inputs. Fig. 3.18 presents the circuit schematics of a double balanced mixer, so called Gilbert mixer, and the equivalent circuit of the LO switch. The Gilbert cell mixer employs MOSFET differential pair serving as a transconductance amplifier and use four MOSFET realizing the LO switching function. Then, the LO inverse pair switches the down-grade/upgrade RF frequency to the IF terminal. The even-order harmonic frequency interference can be eliminated from the Gilbert cell mixer due to the feature of a differential pair balance architecture.

t

LO +

Fig. 3.18 Circuit schematics of a double balanced mixer and the equivalent circuit of the LO switch.

The ideal waveform of the LO switch is a square wave. Figure 3.18 shows the fundamental circuit architecture of an LO switch in a Gilbert cell mixer. All MOS transistors are assumed to work in the saturation region and all transistors to have the same characteristics. The substrate body effect and the output resistance are neglected

[11]. The drain currents can be expressed as

' 1 2

n' n ox

Equations (3.8), (3.9) and (3.11) can be rewritten

(3.12) (3.13) Subtracting Eq. (3.13) from Eq. (3.12) and substituting

(3.14) together to yield

(3.18)

(3.19)

Equations (3.18) and (3.19) are thus obtained. The limiting input RF signal magnitude can be calculated.

2

The relationship can be used to rewrite Eqs. (3.18) and (3.19) in the form

(3.23)

Given a long channel MOSFET operating in saturation region with a drain current at

ID , then the transconductance can be derived as

) and LO transistors, M3-M6 exhibits ideal switching. Following (3.7), (3.28), and (3.29), the drain currents of LO transistors can be rewritten,

The IF output drain current equation is

6 The negative represents a phase inversion of 180°

Substituting Eq. (3.30) to (3.33) into (3.34) yields relationship between the input and 2 )

the output signal.

(3.35) The first-order term in Eq. (3.35) is considered. The output signal is to be determined and the other terms represent the harmonic signals.

(3.36)

Thus, the conversion gain fo a standard Gilbert mixer is given by Conversion Gain = ⋅g_m⋅R_L

π

2 (3.37)

In practice, the LO signal is typically a sinusoidal wave rather than an ideal

In practice, the LO signal is typically a sinusoidal wave rather than an ideal

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