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國立交通大學

電機學院 電子與光電學程

碩 士 論 文

5.5GHz 低功耗射頻 CMOS 混頻器設計與研製

5.5GHz Low Power RF CMOS Mixer

Design and Chip Fabrication

研 究 生:盧笙豐

指導教授:郭治群 博士

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5.5GHz 低功耗射頻 CMOS 混頻器設計與研製

5.5GHz Low Power RF CMOS Mixer Design and Chip

Fabrication

研究生:盧笙豐 Student : Sheng-Feng Lu

指導教授:郭治群 Advisor : Dr. Jyh-Chyurn Guo

國 立 交 通 大 學

電機學院 電子與光電學程

碩 士 論 文

A Thesis

Submitted to College of Electrical and Computer Engineering National Chiao Tung University

in partial Fulfillment of the Requirements for the Degree of

Master of Science in

Electronics and Electro-Optical Engineering June 2007

Hsinchu, Taiwan, Republic of China

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5.5GHz 低功耗射頻 CMOS 混頻器設計與研製

研究生:盧笙豐 指導教授:郭治群 博士

國立交通大學 電機學院 電子與光電學程

摘 要

本篇論文介紹低功率消耗之無線區域網路之射頻吉伯特混波(Gilbert mixer) 之電路設計。對於單晶片(SoC)手持式無線網路之產品應用,低功率消耗之電子式 產品,以蔚為新的潮流及趨勢。本論文是以 TSMC 0.18µm 1P6M CMOS model 模 擬電路及實現低功率電路。主要電路是以吉伯特混波器(Gilbert mixer)為主,電源 供應系利用 LC 並聯諧振電路當作 RF-MOS 級 LO MOS 電源供應。吉伯特混波器 基本架構圖以 multi-gate 電路放大器,其主要功能有二:第一為增加 Gm 值,以增 加其增益轉換值(S21);第二增加其線性度,利用不同之輸入閘級電壓,將非線性的 部分做部分的互相抵銷,使其線性度增加。在閘級輸入電壓串聯一電感目的為使輸 入信號的能量集中在閘及輸入端作為阻抗匹配,使其有最大的能量轉換。並適當的 嘗試改變基本電路架構於射頻輸出端與 LO 間加入一電感,可得到更大的轉換增益 (Conversion Gain)。我們亦嘗試在 IF 輸出端並聯一被動元件-電容,以增加其線性 度。本合成器在實際封裝量測中,輸出 P-1dB 點為 2.5 dBm,IIP3 為 11dBm 即 轉換增益為 7.46 dB,消耗功率為 9.5 mW。

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5.5GHz Low Power RF CMOS Mixer Design and

Chip Fabrication

Student : Sheng-Feng Lu Advisor : Dr. Jyh-Chyurn Guo

Electronics and Electors-Optical Engineering

National Chiao Tung University

ABSTRACT

This thesis proposes a low-power mixer circuit design for wireless communication applications. For systems-on-a-chip (SoC) in portable wireless networks, low power requirement is increasingly important. In this study, TSMC 0.18μm 1P6M CMOS process and model are employed for circuit implementation and simulation to achieve low power. Gilbert cell mixer circuit is adopted and some new ideas are proposed to reduce power consumption. The proposed new ideas cover a parallel resonator realized by LC-tanks and multi-stage parallel RC networks for linearity improvement. Also, multi-gated structure is applied in the RF input as a transconductance amplifier to improve conversion gain and linearity . The higher conversion gain (S21) is due to larger Gm. The better linearity of higher IIP3 is attributed to third-order nonlinear term cancellation realized by gate bias tuning on the multi-gated structure. An on-chip inductor is added in RF input for impedance matching. For LO input impedance matching,

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off-chip inductor is employed. For RF output a pair of on-chip inductors were used to increase conversion gain. The parallel R-C networks add to IF output terminal can improver linearity with higher IIP3. Measured performance in terms of linearity is P-1dB at 2.5 dBm and IIP3 at 11 dBm The conversion gain can be achieved at 7.46 dB, and power consumption can be maintained as low as 9.5 mW.

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誌 謝

轉眼間,碩士在職專班生涯已過了三年半,前兩年以修課為主,後期即以 論文研究為主。在此,感謝很多人的支持和幫忙,讓我的學業及論文得以完成。 特別感謝我的指導教授 郭治群老師不辭辛勞的教誨及指導,並提供一個新的思 考方向,讓我在研究過程中得以解決重重困難且得到更多的寶貴經驗。 感謝 ED635 實驗室同學宏霖、益民、致廷、登陽、姵瑩的幫忙,讓我們 新的實驗室有更多的資源及提供我們一個更好的研究環境。再此也感謝鼎勳實驗 室所有同之幫忙。感寫我週遭關心我的好朋友,感謝您們的幫助及給我的鼓勵加 油,感謝國科會國家晶片中心(CIC)提供先進的半導體製程技術,讓晶片的的以 順利完成。 最後是要感謝我的父母及我的家人,僅以此論文的榮耀獻給我的家人與身 邊所有關懷我的朋友。

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Contents

Chinese Abstract

………...………….i

English Abstract

………..……….….ii

Acknowledgement

………...iv

Contents

……….……...v

Figure Caption

……..……….………....… viii

Table Caption

…………..……….………..………...xiii

Chapter 1 Introduction

1.1 Motivation………..1

1.2 IEEE 802.11a Standard………..………...2

1.3 Thesis Organization……..………..………...5

Chapter 2 Receiver Architecture

2.1 Introduction to RF Receivers………7

2.1.1 Heterodyne Receivers………...……….……8

2.1.1.1 Simple-Stage Heterodyne Receivers…..……….……9

2.1.1.2 Multiple Heterodyne Receiver……… 13

2.1.2 Homodyne Receivers………16

2.1.3 Comparison of the receiver architecture………...20

2.2 Design Parameters and Non-ideality………..……21

2.2.1 Linearity….………...22

2.2.1.1 P-1dB Gain Compression………..25

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2.2.1.4 Dynamic Range……….31

Chapter 3 Design of a 5.5 GHz CMOS Active Mixer

3.1 Mixer………..………...……36

3.1.1 Passive Mixer………..………...……...36

3.1.2 Active Mixer………..………...……..38

3.2 Design of Low-Power-Consumption Circuit with LC-Tank……….39

3.3 5.5 GHz CMOS Down-Conversion Mixer……….42

3.3.1 5.5GHz Down-Conversion Mixer Circuit Block……….……….43

3.3.1.1 LC-Tanks………..45

3.3.1.2 Multiple Gate MOS Transistors used in RF Input Stage…….46

3.3.1.3 RF Output Inductors………....50

3.3.1.4 Balun Circuit Design……….…...51

3.3.1.5 LO Switching……….…..54

3.3.1.5.1 Single Balance Mixers………....55

3.3.1.5.2 Gilbert Cell Mixer (Double Balance Mixer)…..….57

3.3.1.6 IF Output – Parallel RC Network for Linearity Improvement ……….…63

3.3.1.7 Package Topology………....63

3.4 Figure-of-Merit of RF CMOS Transistors…….. ………..65

3.5 Noise analysis for RF Active Mixers……….………67

3.5.1 Noise Analysis – Power Spectral Density (PSD) ……….67

3.5.2 Noise Analysis – Noise Figure ……….69

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Chapter 4 Chip Circuit Design and Simulation

4.1 Models……….……..72

4.1.1 RF MOS Model……….73

4.1.2 Spiral Induct Model……… .75

4.1.3 MIM Capacitor Model………..76

4.2 Simulation Results of Down-Conversion Mixer….………..77

4.2.1 Improved Linearity using Parallel RC Networks at IF Stage..……….77

4..2.2 Relationship Between LO Signal for Linearity and Noise Figure…...81

4.2.3 On-Chip Circuit Simulation Results..………...84

4.2.4 On-Board Circuit Simulation Results- QFN Package…….………….88

4.3 Chip Circuit Layout..………...………....…91

Chapter 5 Measurement

5.1 Measurement Setup………..………...93

5.1.1 Measurement Configuration………..…….………...94

5.1.2 Noise Measurement………...…...95

5.2 Measurement Results………...96

5.2.1 Conversion Gain Measurement………....…96

5.2.2 P-1dB/IIP3 Measurement………..98

5.2.3 Noise Figure Measurement……….102

5.3 Summary………..………...103

Chapter 6 Conclusion and Future Work

6.1Conclusion………...104

6.2 Future Work……….…….……….……104

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Figure Captions

Chapter 1

page

Fig. 1.1 Receiver mixer function block……... 2

Fig. 1.2 IEEE 802.11a Channel Location for 5GHz U-NII Bands……….. 4

Fig. 1.3 IEEE 802.11a Transmitted Spectral…... 5

Chapter 2

page Fig. 2.1 Transmitter front end of a wireless transceiver………. 8

Fig. 2.2 Receiver front end of a wireless transceiver………. 8

Fig. 2.3 (a) Simple heterodyne receiver………... (b) High IF rejection of image versus suppression of interferers………. (c) Low IF rejection of image versus suppression of interferers…………... 9 10 11 Fig. 2.4 (a) Dual-IF heterodyne receiver.………... (b) Dual-IF heterodyne receiver frequency conversion……… 14 14 Fig. 2.5 Quadrature down-conversion zero IF receiver.………. Fig. 2.6 Simple homodyne receiver. ………... 16 16 Fig. 2.7 Direct down-conversion architecture of DC-offset (self-mixer)………... (a) LO leakage………... (b) Strong interference signal ………... 18 18 Fig. 2.8 I/Q mismatch contributions for difference stage and on QPSK signal constellation. ………... (a) I/Q mistach contributions by several stages………... (b) Gain error………... (c) Phase error………... 19 19 19 Fig. 2.9 Even-order distortion on interferes………... 20

Fig. 2.10 Inter-modulation output spectrum in the frequency domain………. 25

Fig. 2.11 P-1dB compression gain point………... 26

Fig. 2.12 Third-order inter-modulation between two tone interferences………... 28

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Fig. 2.14 Upper band of SFDR………...………... 32

Chapter 3

Fig. 3.1 (a) Passive (Diode) mixer………. (b) Passive (MOS) mixer……….. 37 37 Fig. 3.2 (a) Single Balanced Mixer………. (b) Double Balanced Gilbert Mixer………... 38 39 Fig. 3.3 A circuit block diagram for a typical Gilbert mixer with RF, LO, and load stages and the applied DC and RF ground (Gnd)……… 41 Fig. 3.4 A new topology using LC-tank and bypass capacitance for low voltage operation a Gilbert mixer with applied DC, RF Gnd……... 42

Fig. 3.5 The proposed CMOS RF mixer block………... 43

Fig. 3.6 The proposed double balanced RF mixer circuit tolopogies... 44

Fig. 3.7 LC-tanks circuits……… 45

Fig. 3.8 Illustration the LC-tank circuit resonating frequency for RF signal and DC biasing status……….……….. 46 Fig. 3.9 MOSFET small signal model………. 47

Fig. 3.10 (a) Multiple gated circuit topology……… (b) " m g of Q1 and Q2 (c) the effective " m g resulted from combining Q1 and Q2 to increase linearity………. 49 49 Fig. 3.11 Circuit schematics with RF amplifier, input and output Baluns for simulation and first phase design of the mixer……….. 50

Fig. 3.12 RF amplifier S11, S21 calculated by circuit simulation………. 51

Fig. 3.13 RF LC Balun Circuit..……… 52

Fig. 3.14 Half-circuit equivalent circuit……… 53

Fig. 3.15 Frequency response of LC-Balun in terms of magnitude error and phase error………. 54

Fig. 3.16 Circuit schematics of a signal balanced mixer and the equivalent circuit of the LO switch………. 56

Fig. 3.17 LO switch waveform. ……… 56 Fig. 3.18 Circuit schematics of a double balanced mixer and the equivalent circuit of

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the LO switch………. 58 Fig. 3.19 Pin assignment for the bonding pads on board……….. 64 Fig. 3.20 Package model of the bonding pad and wires……… 65 Fig. 3.21 0.18um N-MOSFET NFmin versus drain current under varying frequencies 66

Chapter 4

Fig. 4.1 Equivalent circuit model for RF N-MOS transistor……….. 74 Fig. 4.2 Top view and physical dimension of rectangular spiral inductor………….. 75 Fig. 4.3 Equivalent circuit of rectangular spiral inductor….……….. 75 Fig. 4.4 (a) MIM capacitor layout...….……….………...

(b) Equivalent circuit for MiM capacitors………. 76 76 Fig. 4.5 (a) Conversion gain and P-1dB for IF stage with resistor networks

(without capacitor)………... (b) Conversion gain and P-1dB for IF stage with RC networks (with

capacitors)……… (c) Conversion gain and IIP3 for IF stage with resistor networks (without

capacitor)……….. (d)Conversion gain and IIP3 for IF stage with RC networks (with

capacitors)……… (e)Filering effect on high frequency harmonic by adopting parallel RC

networks to improve linearity……….. 79 79

79

80 80 Fig. 4.6 (a) LO=10dBm (e.g. 0.71V) noise figure, conversion gain and IIP3

plot……….. (b) LO=2.5 dBm (0.31V) noise figure, conversion gain and IIP3 plot……

82 83 Fig. 4.7 (a) 25°C@1.0V SS of corner model simulation plots for conversion

gain and P-1Db………. (b) 25°C SS of corner model simulation plots for conversion gain and

IIP3……….. (c) 25°C@1.0V SS of corner model simulation plots for noise figure for

SSB and DSB……… 85 85 86

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87 87 87 Fig. 4.8

Fig. 4.9

(a) 75°C@1.0V SS of corner model simulation plots for conversion gain and P-1dB……… (b) 75°C@1.0V SS of corner model simulation plots for IIP3……… (c) 75°C@1.0V SS of corner model simulation plots for noise figure for SSB and DSB……… (a) 25°C@1.0V SS of corner model simulation plots for conversion

gainand P-1dB………..

(b) 25°C SS of corner model simulation plots on QFN chip for conversion gain and IIP3………... (c) 25°C@1.0V SS of corner model simulation plots for noise figure for and DSB………

88 89 89

(a) 75°C@1.0V SS of corner model simulation plots for conversion gain

and P-1dB………

(b) 75°C SS of corner model simulation plots on QFN chip for conversion

gain and IIP3………... Fig. 4.10

90 90

(c) 75°C@1.0V SS of corner model simulation plots for noise figure for

SSB and DSB……… 91

Fig. 4.11 On-wafer chip layout of mixer for symmetric layout……… 92

Fig. 4.12 Turning in layout of perpendicular……… 92

Chapter 5

Fig. 5.1 Off-chip circuit and IF test board……….………... 93

Fig. 5.2 Down-conversion mixer measurement setup diagram……….. 94

Fig. 5.3 Noise Measurement Setup………. 95

Fig. 5.4 Instruments overview in RF measured laboratory………. 96

Fig. 5.5 Measured gain v.s RF Power input (RF=5.501 GHz, LO=5.500 GHz@ LO=2.5………... 97

Fig. 5.6 Measured gain v.s RF input freuency (RF=0 dBm, LO=2.5 dBm, IF output is constant 1MHz)………...……… 98

Fig. 5.7 Measured IF output magnitude ………... 99

Fig. 5.8 Measured P-1dB linearity curve.………... 100

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(b) Agilent spectrum analyzer measured 2-tone test result………... 101 Fig. 5.10 Measured IIP3 linearity curve by 2-tone test.………... 102 Fig. 5.11 Measured noise figure by NFA……….. 103

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Table Captions

Chapter 1

Table 1.1 IEEE 802.11a modulation scheme and EVM requirement…..………... 4 Table 1.2 IEEE 802.11a transmit maximum power levels 5

Chapter 2

Table 2.1 Comparison of Heterodyne and homodyne receivers architecture…….. 21

Chapter 3

Table 3.1 Comparison between the single gate and multiple gate performance…. 48

Chapter 4

Table 4.1 Bias ranges of RF MOS………... 73 Table 4.2 Compared IF stage with capacitor and without capacitor by simulation 78 Table 4.3 Compared linearity and noise figure for LO signal magnitude………... 82 Table 4.4 Corner model simulation results in biasing 1.0V and 25°C……… 84 Table 4.5 Corner model simulation results in biasing 1.0V and 75 °C…………... 86 Table 4.6

Corner model simulation results on QFN chip in biasing 1.0V and 25°C……….

88 Table 4.7 Corner model simulation results on QFN chip in biasing 1.0V and

75°C………... 90

Chapter 5

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Chapter 1

Introduction

1.1 Motivation

The advancement of semiconductor technology has driven the growth of wireless communication. Furthermore, the deep submicron CMOS technology has attracted much interest and effort to penetrate into wireless communication application due to advantage of lower cost and higher integration. Due to the fact, RF CMOS becomes a hot topic in academic research and technology development. Higher frequency and wider bandwidth can increase data rate and lower supply voltage is desired to achieve low power. However, the RF CMOS circuit design is traded off with many challenges like high frequency model accuracy, impedance matching, linearity, noise, and power consumption. Each factor influences circuit performance and its consideration increases the difficulty of RF circuit design. For RF MOSFET model, the major challenges include the parasitic resistance, inductance, and capacitance effects and accuracy in gate capacitance model, noise model, and subthreshold region models. As for passive device models, a broadband and scalable model for on-Si—chip inductors become a major challenge for RF integrated circuit simulation and design.

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In this thesis, a single band 5.5 GHz down-converter mixer is designed for application in the 802.11a standard. The major features for this new mixer design include low-power-consumption, high-performance, high linearity and high conversion gain. Figure 1.1 shows the 802.11a function block. The fundamental wireless communication architecture includes a switch, a power amplifier (PA), a low-noise amplifier (LNA), an up-converter mixer, a down-converter mixer, a synthesizer, and a filter.

1.2 IEEE 802.11a Standard

An IEEE 802.11a standard system has a total bandwidth of 300 MHz and a 20MHz bandwidth for each channel. The IEEE 802.11a standard applies the 5GHz unlicensed national information infrastructure (U-NII) bands, as shown in Fig. 1.2 [1]. The bandwidths available for 802.11a cover the lower band frequency from 5.15 GHz to 5.25 GHz, and the middle band frequency from 5.25GHz to 5.35GHz. Both bands

Fig. 1.1 Receiver mixer function block

A/D D/A Interface 5 GHz Synthesizer (Vco) LNA PA Tx Rx Base Band

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provide eight channels. Each band bandwidth is 200 MHz and outmost channel side band is 30 MHz. The upper band frequency 5.715GHz to 5.825GHz U-NII band accommodates four channels in the final 100 MHz of the bandwidth, and the outmost channel sideband is at 20 MHz.

This bandwidth is associated with an orthogonal frequency division multiplexing (OFDM) modulated signal, comprising 52 subcarriers, each of which has a bandwidth of 300KHz for each channel. Each subcarrier can be modulated by binary phase shift keying (BPSK), quadrature phase shift keying (QPSK), 16-QPSK or 64 QQPSK modulation. The RF signal can rise to a fast data rate of 54 Mbps in 20 MHz for each channel.

For performance evaluation of the IEEE 802.11a, an error vector magnitude (EVM) is generally used to represent the quality of a digitally modulated signal. The EVM can indicate a disfigurement, such as an amplitude mismatch, a phase error, phase noise, nonlinearity and others. The modulation parameters depend on the data rate and are set as shown in Table 1.

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5.150 GHz 5.350 GHz ` ` ` ` 5.250 GHz 30 MHz 20 MHz 30 MHz

Lower Band Middle Band

5.7250 GHz 5.8250 GHz 20 MHz 20 MHz 20 MHz Upper Band 52 carriers, each BW= 300 KHz 20 MHz

Fig. 1.2 IEEE 802.11a Channel Location for 5GHz U-NII Bands

Table 1.1 IEEE 802.11a modulation scheme and EVM requirement

Data Rate

(Mbits/s) Modulation Coding Rate EVM (dB)

Minimum sensitivity (dBm) 6 BPSK 1/2 -5 -82 9 BPSK 2/3 -8 -81 12 QPSK 1/2 -10 -79 18 QPSK 3/4 -13 -77 24 16-QAM 1/2 -16 -74 36 16-QAM 3/4 -19 -70 48 64-QAM 1/2 -22 -66 54 64-QAM 3/4 -25 -65

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channel. IEEE 802.11a regulations define the maximum power level and the transmission spectrum mask. The maximum emission power is determined by FCC regulations, as indicated in Table 1.2.

Table 1.2 IEEE 802.11a transmit maximum power levels

Frequency band (GHz) Maximum output power with up to 6dBi antenna gain (mW)

5.15~5.25 40 (2.5 mW/MHz)

5.25~5.35 200 (12.5mW/MHz)

5.725~5.825 800 (50 mW/MHz)

The transmitted spectrum density must have a 0 dBr bandwidth of not more than 18 MHz, –20 dBr at an 11 MHz frequency offset, –28 dBr at a 20 MHz frequency offset and –40 dBr at a 30 MHz frequency offset and above. The transmitted spectral density of the transmitted signal must fall within the spectral mask, as shown in Fig. 1.3.

Fig . 1.3 IEEE 802.11a Transmitted Spectral

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CMOS technology to achieve advantage of low power consumption, high linearity and high conversion gain. The method to realize the mentioned advantages will be described in the following chapters.

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Chapter 2

Receiver Architecture

Recently, commercial RF and wireless communication products have become more prevalent. The RF wireless communication carrier frequency has increased to 12 GHz and related fabrication processes have shrunk to the nanometer scale. Numerous RF and wireless products, such as mobile ‘phones, RFID, GPS, Bluetooth products and wireless networks, are now affecting daily life.

This chapter introduces several architectures, including an active mixer and a passive mixer. The architectures of heterodyne receivers and homodyne receivers are also discussed [2-3].

2.1 Introduction to RF Receivers

A wireless communication system transmits carrier information over a limited bandwidth, such as 30 kHz in IS-54, 200 KHz in GSM and 20 MHz in WLNA.

The narrow bandwidth of the system affects the design of an RF section. The transmitter must employ narrowband amplification and filter to prevent interference from an adjacent channel, as displayed in Fig. 2.1. The receiver must process a weak signal and reject strong interference from nearby antennae and bandpass filter signals, as presented in Fig. 2.2.

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B P F P ow er A m plifier A djacent C hannels T ransm itted C hannel

Fig. 2.1 Transmitter front end of a wireless transceiver

A d ja c e n t C h a n n e ls R e c e iv e r , D e s ir e d C h a n n e l B P F L o w n o i s e A m p li f i e r

Fig. 2.2 Receiver front end of a wireless transceiver

In this section, we will describe the heterodyne, homodyne and image rejection architectures for the receiver design.

2.1.1 Heterodyne Receivers

The heterodyne receiver transforms a signal from carrier radio frequency (RF) to intermediate frequency (IF), base-band frequency. Heterodyne receivers are of two types - (I) simple heterodyne receiver and (II) multiple heterodyne receivers. As described above, the receiver front end signal suffers large interference and distortion

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of the original signal and requires prohibitively high Q values.

2.1.1.1 Simple-Stage Heterodyne Receivers

The single stage heterodyne receiver in one stage converts radio frequency to intermediate frequency. It utilizes only one mixer. As shown in Fig 2.3, the radio frequency is received from the antenna, passed through an RF filter to suppress interference; sent to a low-noise amplifier (LNA) and then to the mixer, and eventually delivered to base-band chip. The simple heterodyne design must take into account the choice of IF and so depends on trade-offs among three parameters - (I) image reject filter loss, (II) image noise, and (III) spacing between image and desired band. Item III is of particular importance since designing a narrow band filter is very difficult.

RF Filter LNA

Lo Frequency

Image Reject

Filter Select FilterChannel IF Amplifier

A/D Converter

Base-Band

Off-Chip

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Desired Channel Image Reject Filter Image Interference

ω

1

ω

image

2ωif

ω

Channel Filter

ω

if

ω

image

ω

Image

0

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Desired Channel Image Reject Filter Image Interference

ω

1

ω

image

2ωif

ω

Channel Filter

ω

if

ω

image Image

0

Fig. 2.3 (c) Low IF rejection of image versus suppression of interferers

If the radio frequencyωrfloif, then the mirror image may happen at frequencyωrflo −ωif. The mixer and local oscillator frequencies make it difficult in the determination of the overlap frequency on the IF port. Accordingly, an image rejection filter (IR Filter) must be added before the mixer. The IR filter typically requires a high-Q filter, but the integration circuit (IC) does not allow the simple implementation of a high-Q solution. Therefore, the integration of the system is

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complicated.

This simple heterodyne raises a series problems associated with mirror image rejection frequency interference. The image frequency degrades the sensitivity and signal-to-noise ratio (SNR). The image frequency is defined as ωimage ≡ωrf −2ωif ; the frequency of the down-conversion to IF is defined ωif ≡ωrf −ωlo; RF is ωrf, and the local oscillator frequency is ωlo. The down-converter mixer process must be modeled mathematically to solve the image problem. The RF and LO input equations are defined as Vrf = Arf cosωrft and Vlo = Alocosωlot . and A =lo A = A is rf

assumed. Hence, t A t A t Vif( )= cosωrf ⋅ cosωlo (2.1) ] ) cos( ) [cos( 2 1 2 t t A ωrflo + ωrf −ωlo = (2.2) ] cos ) [cos( 2 1 2 t t A ωrflo + ωif = (2.3) The second term is the intermediate frequency (IF) of interest.

lo rf if ω ω

ω ≡ − and ωimage ≡ωrf −2ωif are used to rewrite the assumed image frequency equation ωimagelo −ωif.

t A

t A

t

Vif ( )= inagecosωimagelocosωlo (2.4) ] ) cos( ) [cos( 2 1 2 t t A ωlo −ωiflo + ωlo −ωif −ωlo = (2.5) ] cos ) 2 [cos( 2 1 2 t t A ωloif + ωif = (2.6)

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Therefore, strong interference at the image frequency affects the IF signal, then the IF will strongly interfere with the desired signal, degrading the system (SNR). For the simple heterodyne receiver, an accurate IF frequency must be chosen. The frequency declines to IF from RF and the local frequency only once. A high IF is chosen. Accordingly, a high Q filter must be employed. The high-Q filter is not simple to implement with SoC and high-speed A/D converter design is very challenging. If a lower IF is chosen, the image frequency will not be eliminated and the high image frequency noise on IF will be excessive. Figures 2.3(b) and 2.3(c) reveal that if the IF is high, then the image can be suppressed but complete channel selection is very difficult. Therefore, the simple heterodyne has sensitivity and selectivity problems.

A simple heterodyne receiver application must take into account sensitivity and selectively, and the problem of integration for a SoC system.

2.1.1.2 Multiple Heterodyne Receiver

To solve the problem described in the preceding section, the concept of the simple heterodyne can be expanded to multiple heterodyne down-converter mixers. The multiple heterodyne has at least two frequency levels from the RF frequency down to IF, to eliminate the filter Q value requirement. Partial channel selection can be conducted and the image rejected in two stages, as shown in Fig. 2.4 (a).

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RF Filter LNA

Lo Frequency 1

Image Reject

Filter 1 Select Filter 2Channel

A/D Converter Base-Band Lo Frequency 2 Channel Select Filter 3 IF Amplifier Off-Chip A B C D E F G H Mixer 2 Mixer 1 BPF 1 BPF 2 BPF 3

Fig. 2.4 (a) Dual-IF heterodyne receiver

Desired Channel Image RF Filter BPF 1

A

B

C

BPF 2

D

Mixer 1 Lo 1

E

Mixer 2 BPF 3

F

H

G

Lo 2 IF Amplifier

Fig. 2.4 (b) Dual-IF heterodyne receiver frequency conversion.

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integrating an SoC system will require that the band pass filter has a very large IC. Figures 2.4(a) and 2.4(b) show spectra at various points in the dual-IF receiver. The frond-end RF band selection filter suppresses image rejection and the spectra at point as shown figures Fig. 2.4(b) A and B. Following LNA and image reject filter, a spectrum from point as shown figures Fig. 2.4(b) B to C can be obtained. Then, the desired channel and the adjacent interference must be translated the spectrum at point C. The adjacent interference is slightly suppressed by BPF-2. Similarly, the second mixer provides reasonable linearity and signal translates to the second IF as shown figures Fig. 2.4(b) spectra D and E. After The BPF-3 channel filter absolutely suppresses the adjacent interference signal, as shown in Fig. 2.4(b), in spectra F to H. Finally, the IF signal is amplified.

The second down-conversion mixer typically generates both in-phase (I) and quadrature (Q) which components of the signal are used to translate the spectrum to zero frequency, yielding the block diagram in Fig. 2.5

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RF Filter

LNA

A/D

Converter

Base-Band

Off-Chip

LPF

LPF

90 Shifter

0

AGC

AGC

Lo

. Fig. 2.5 Quadrature down-conversion zero IF receiver.

Despite the addition of the extra complexity component of the RF and IR filter and the increased size on SoC, heterodyne receivers are conventionally used as the most reliable.

2.1.2 Homodyne Receivers

Figure 2.6 shows a fundamental architecture of a homodyne receiver. The Lo frequency equals the RF input carrier frequency; such receivers are called “zero-IF” or “direct-conversion”. The homodyne receiver is designed as a low-pass filter instead of a channel select function.

R F F ilte r

L N A

ω

L P F C o n v e rte rA /D B a se -B a n d 0

ω

0

ω

0

ω

0

ω

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The homodyne receiver architecture has evident relative characteristic without image reject signals. Since the homodyne receiver’s RF receiver signal is through RF filter, LNA, mixer, and to LPF, which can remove image frequency by itself, the homodyne architecture does not require an image reject filter. Consequently, the homodyne requires no external connected component module, and can be integrated as a single entity.

A direct down-conversion receiver with a spectrum translated to zero frequency suffers from such issue such as DC offset, I/Q mismatch, even-order distortion, flicker noise and LO leakage problem, as described below.

(a). DC Offset

Since the local oscillator frequency equals RF, the isolation between the LO port and the LNA input or mixer input is finite. The strong extraneous signal is fed through from the LO port to the LNA input and the mixer input, as shown in Fig. 2.7 (a). Similarly, if a large leakage from the LNA to mixer input interferes through to LO port, it is possible multiplied by itself signal as shown in Fig, 2.7 (b), then, LO port signal and mixer input signal couple signal can corrupt or distort the original signal of the LAN or mixer input. The signal coupling issue then involves partial DC offset and may cause A/D converter saturation, after causing a demodulation error. This effect arises from the substrate or capacitance coupling.

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RF Filter

LNA

ω

LPF ConverterA/D

0

ω

0

RF Filter

LNA

ω

0 LPF ConverterA/D

ω

0 LO Leakage LO Oscillator LO Oscillator Interference Leakage (a) LO leakage

(b) Strong interference signal.

Fig. 2.7 Direct down-conversion architecture of DC-offset (self-mixer).

(b). I/Q Mismatch

The mixer is input LNA RF signal and LO port signal. IF both signals phase mismatch condition, causing down-converters signal constellation distortion, increasing the bit error rate. Figure 2.8 displays the mixer input from LNA RF input signal and local signal input contributions of gain, phase error, and above makes I/Q mismatch QPSK signal constellation.

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R F F ilte r L N A A /D C o n v e rte r B a s e -B a n d O ff-C h ip L P F L P F 9 0 S h ifte r0 A G C A G C L O P h a se a n d G a in E rro r P h a s e a n d G a in E rro r Q I Id e a l Q I Id e a l (b ) G a in E rro r (c ) P h a se E rro r P h a s e a n d G a in E rro r P h a se a n d G a in E rro r

(a ) I/Q m ism a tc h c o n trib u tio n s b y se v e ra l s ta g e s

Fig. 2.8 I/Q mismatch contributions for difference stage and on QPSK signal constellation.

(c). Even-Order Distortion

The low noise amplifier (LNA) may cause even-order distortion interference adjacent to the IF channel, as shown in Fig. 2.9. The second term harmonic interferes with the zero-IF signal.

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ω

LO

ω

Interferences LNA Desired Channel

ω

0

IM2 IM3 Feed-through

0 IM2

ω

IM3

Fig. 2.9 Even-order distortion on interferes.

(d). Flicker Noise

The homodyne down-conversion spectrum is extended to zero frequency. Hence, in the homodyne architecture, low-frequency noise of the device generally approaches a function proportional to 1/f and named as flicker noise. The flick noise dominates in low frequency region and degrades the signal-to-noise ratio (SNR).

2.1.3 Comparison of the receiver architectures

Table 2 lists the key features for a receiver and makes comparison between heterodyne and homodyne receiver architectures.

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Table 2.1 Comparison of Heterodyne and homodyne receivers architecture Receiver Architecture

Comparison Item

Heterodyne receiver Homodyne Receiver

Frequency conversions Twice or More Once

Channel Filter IF Base-Band

Required Discrete Filter RF, Noise, IF RF

Required High Q filter Yes No

Monolithic integration base-band to signal chip (SoC)

Very Difficult (More passive component)

Suitable

IF Selection Base on system design specification.

Zero IF

Mainstream Implement to commercial product.

Researching…

2.2 Design Parameters and Non-ideality

For a down-conversion mixer design, the key performance parameters, such as linearity by gain compression (P-1dB) and third-order intercept (IP3), sensitivity, noise figure, dynamics range, and conversion gain, will be considered and discussed in the following sections.

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2.2.1 Linearity

Most of systems approximated as linear systems under sufficiently low power actually reveal nonlinear characteristics in higher power region. The small signals models used for RF and analog circuits, based on linear approximation are no longer valid under increasing power. The primary effect of nonlinearity is the frequency interference from adjacent channel frequency, which corrupts the desired signal. A strong signal driven RF amplifier or mixer will go into nonlinear region and the nonlinear signal generates an interference frequency, which may influence the desired signal. Therefore, the linearity of the receiver determines the maximum allowable input signal level.

For simplicity, these nonlinear systems are assumed to be memory-less and time-invariant. Taylor’s series are used to analyze the nonlinearity.

2 3 0 1 2 2 0 0 ( ) ( ) ( ) ( ) ( ) 1 ( ) | ! i n i i i n i n n n n x i y t x t x t x t x t d y t Where n dx α α α α α α ∞ = = = + + + + ⋅⋅⋅ =   =  

(2.7)

Here )xi(t is the input signal and y(t) is the output signal. Equation (2.7) describes the output DC offset coefficient α0 , )α1xi(t as the first-order term,

) (

2 2xi t

α as the second-order term, and so on. Here, the coefficient αn is assumed to

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system provided that the coefficient |αi1|>|αi| .

Generally, the analytic linearity problem involves a sinusoidal input in Eq. (2.7). Thus, we employ input signal as follows :

t A t A t x( )= 1cosω1 + 2cosω2 (2.8) Substituting equation (2.8) into (2.7).

⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ + + + + + + + = 3 2 2 1 1 3 2 2 2 1 1 2 2 2 1 1 1 0 ) cos cos ( ) cos cos ( ) cos cos ( ) ( t A t A t A t A t A t A t y ω ω α ω ω α ω ω α α (2.9)

[

]

0 1 1 1 1 2 2 2 1 2 2 2 1 2 2 2 1 2 1 2 1 2 3 1 1 3 2 2 3 1 3 2 2 1 2 2 3 1 2 2 3 1 2 1 ( cos cos ) 1 cos2 1 cos2 cos( ) cos( ) 2 2

cos3 3cos cos3 3cos

4 4 1 cos2 1 cos2 3 cos 3 cos 2 A t A t t t A A A A t t t t t t A A t t A A t A A t α α ω α ω ω ω α α α ω ω ω ω ω ω ω ω α α ω ω α ω α ω = + + + + + + + + + + + +  +  +         + +   +     2   +⋅⋅⋅⋅⋅⋅⋅⋅⋅    

Listing the fundamental and harmonic second-order and third-order terms gives the following.

The first-order terms with fundamental frequency is expresses by (2.10) and (2.11): 1 ω : t A A A A t A A t A t A 1 2 2 1 3 3 1 3 1 1 1 2 2 1 3 1 3 1 3 1 1 1 cos 2 3 4 3 cos 2 3 4 cos 3 cos ω α α α ω α ω α ω α             + + =       +       + (2.10)

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2 ω : 3 2 2 1 2 2 3 2 3 1 2 2 3 2 1 2 3 2 3 1 2 2 3 cos 3 cos cos 4 2 3 3 cos 4 2 t A t A A A t A A A A t ω α ω α α ω α α α ω     + +           = + +      (2.11) Second-order terms: 2ω1: 2A12cos2 1t 2 1α ω (2.12) 2ω2: 1 2 22cos 2 2A ω t (2.13) 1 1 ω ω ± : α2A A1 2

[

cos(ω ω1+ 2)t+cos(ω ω12)t

]

(2.14) Third-order terms: 3ω : 1 3A13cos3 1t 4 1α ω (2.15) 3ω : 2 3A23cos3 2t 4 1α ω (2.16) 2ω1±ω2:

[

]

2 3 1 2 1 2 2 3 1 2 1 2 1 2 3 cos 2 cos 2 3 cos(2 ) cos(2 ) 4 A A t t A A t t α ω ω α ω ω ω ω = + + − (2.17) 2 1 2ω ω ± :

[

]

2 3 1 2 1 2 2 3 1 2 1 2 1 2 3 cos cos 2 2 3 cos( 2 ) cos( 2 ) 4 A A t t A A t t α ω ω α ω ω ω ω = + + − (2.18)

Through the Fourier transformation from time domain to frequency domain, )

Y yields the inter-modulation output spectrum in the frequency domain, as shown in Fig. 2.10.

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ω

1

ω

ω

2 1 2

2

ω

ω

2 1

2

ω

ω

o

ω

2 1

ω

ω

)

(

ω

Y

1

2

ω

2

ω

2 2 1

ω

ω

+

Desired Signal Require narrow-band filter

Fig. 2.10 Inter-modulation output spectrum in the frequency domain. Generally, in RF linear systems, the saturation of conversion gain follows an increase in the input signal, accelerating conversion gain saturation. Equations (2.10) and (2.11) indicate that the amplitude of the desired signal is

2 2 1 3 3 1 3 1 1 2 3 4 3 A A A A α α α       + + (2.19) ForA1<<A2 the gain of the desired signal equals to

2 2 3 1 2 3 A α α       + (2.20) Assume that α3<0 (e.g., α1 =−α3) and that A is sufficiently large, the 2

output conversion gain in Eq. (2.20) can be dropped to zero. Accordingly, the third-order signal corrupts the gain as the input signal amplification increases.

2.2.1.1 P-1dB Gain Compression

As mentioned above, when the strength of the input signal to the amplifier drives the amplifier into saturation, the output signal from the amplifiers will be clamped. As a result, the linearity of a system determines the maximum range allowed

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for the input signals to the amplifiers. This amplifier working range is defined by the input signal level at which the small-signal gain drop by 1 dB. This is called the 1dB compression point (P-1dB), as shown in Fig. 2.11.

Pin 1 dB decay 20log(Ain)=Pin (dBm) Pout OP-1dB=Pout (dBm) Slop =1 IIP3 2 P ∆ 2 P ∆ Slop =3

P

OIP3

Fig. 2.11 P-1dB compression gain point

To determine 1dB gain compression point, a single tone excitation is carried out. A single input signal is assumed and given by A2=0 in Eq. (2.8). In this case α3<0

(negative) and the second term degrades the gain.

t A A t A A1 3 13 1 1 3 12 1 1 1 cos 4 3 cos 4 3α ω α α ω α       + =       + (2.21) The 1dB compression point is define as the input power level at which the

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output power drops by 1 dB. 2 1 3 1 2 1 3 1 1 2 1 3 1 20 1 1 2 1 3 1 1 4 3 10873 . 0 4 3 122 . 1 4 3 log 20 10 log 20 log 20 4 3 1 dB dB dB dB dB A A A A dB α α α α α α α α α α α ≈ − ⇒ + = ⇒       + = − ⇒ + = − ) ( | | | | 1449 . 0 3 1 1 dBV AdB α α = ⇒ (2.22)

Equation (2.22) does not take into account the high-order harmonic terms. Due to the fact, the actual P-1dB compression point value is generally below what expected from Eq. (2.22).

Most of the measured P-1dB are expressed in dBm. dBm is an absolute unit of RF power. Therefore, dBV is converted to dBm. dBm is defined as a power dissipation of 1 mW at a characteristic impedance of 50 Ω in a system.

Hence, 2 2 50 001 . 0 log 10 1 50 log 10 1 log 10       ⋅ =           Ω =       = ⇒ rms rms V mW V mW Power dBm ) ( 01 . 13 ) 05 . 0 log( 20 ) log( 20 V 12 dBV dBm rma − = + = (2.23)

2.2.1.2 Third–order Intercept Point (IP3)

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presented in Fig. 2.10. The narrow band filter design is not simple. Signal interference produces an inter-modulation of signals, affecting the RF system. The inter-modulation signal degrades system performance, and the bit error increases after demodulation.

The third-order intercept point is determined by a two-tone test, as shown in Fig. 2.12. The two-tone test is generally employed to identify adjacent channel frequency interferences, caused by the signal reciprocal effects of internal components. Two sinusoidal waves with frequencies of ω and 1 ω are applied to an amplifier. 2 Equation (2.8) is substituted into Eq. (2.6). The third-order terms are given by Eqs. (2.17) and (2.18) and the third-order intercept is plotted in Fig.2.11.

Linear System

ω

0 IM3 1 2 2ω −ω 2 1 2ω−ω Aout AIM3 ) (

ω

Y Fundamental

ω

0 Ain

)

(

ω

X

Fundamental Two tone 1 ω ω2 Desire Signal

Fig. 2.12 Third-order inter-modulation between two tone interferences.

As shown in Fig. 2.11, the third-order intercept point terms are set across equal to the first-order point terms. Setting A1=A2=A in Eq. (2.17), and equating the

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3 3 3 3 1 4 3 IIP IIP A A α α = (2.24) ) ( | | | | 3 4 3 1 3 dBV AIIP α α = ⇒ (2.25)

Comparing Eq. (2.22) with Eq. (2.25) yields

) ( 64 . 9 ) 201 . 9 log( 20 ) log( 20 ) log( 20 201 . 9 | | | | 1449 . 0 | | | | 3 4 | | | | 1449 . 0 | | | | 3 4 1 3 3 1 3 1 3 1 3 1 1 3 dB A A A A dB IIP dB IIP ≅ = − ⇒ = = = α α α α α α α α (2.26)

Hence, IIP3 is related to P-1dB by the equation as follows,

IIP3 = 1dB compression point + 9.64 dB (2.27) The graphic shown in Fig. 2.11 can be used to calculate the input and output third-order intercept points given by (2.28) and (2.29) for IIP3 and OPI3, respectively.

dBm in dB dBm P P IIP = ∆ + 2 3 (2.28) dBm out dB dBm P P OIP = ∆ + 2 3 (2.29)

2.2.1.3 Sensitivity

The sensitivity of an RF receiver system is determined by the minimum signal level that the receiver system can detect under an acceptable signal-to-noise ratio. Mathematically, the noise figure (NF) is defined as

in out out in out in in out in N S N S SNR N S SNR SNR NF ≡ = = (2.30) where Sin and Nin represent the input power and the source resistance noises per unit

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bandwidth. Sout= GSin and G is the power gain. The channel bandwidth (BW) is across the overall signal.

Therefore, the input signal power across the channel bandwidth is obtained by rewriting Eq. (2.30) as,

BW NF N SNR

Sin = outin ⋅ ⋅ (2.31) Taking logarithms gives,

) log( 10 min min , SNR N NF BW S dB Hz dBm in dB dBm in = + + + (2.32)

Equation (2.32) predicts the sensitivity performance from the output SNR. The receiver input system is assumed to exhibit conjugate matching at the input; Nin is

obtained as the thermal noise power :

Hz dBm kT R kTR N in s in 174 / 1 4 4 − = = ⋅ = (2.33) where T is the absolute room temperature (°K) and Nin at 300oK is equal to –174

dBm/Hz .

Thus, the minimum input power Sin,min is derived as

min min

, 174 dBmHz NF 10log(BW) SNR

Sin =− + + + (2.34) In Eq. (2.34), the sum of the first three terms is sometimes called the “ noise floor ”, which is generally employed to define the dynamic ranges, such as SFDR and BDR in the following section. Since SNRminis a function of the bandwidth, the noise floor is determined by setting SNRmin in Eq. (2.34) to zero.

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2.2.1.4 Dynamic Range

The dynamic range (DR) is defined as the ratio of the maximum allowed input signal level to the minimum input signal level at which the signal quality is maintained [2], [3]. Two definitions of dynamic range are adopted to evaluate the dynamic performance, as shown in Fig. 2.13. These are called spurious-free dynamic range (SFDR) and blocking dynamic range (BDR). For both definitions of dynamic range, the minimum boundary is defined as the noise floor plus SNRmin. The spurious-free dynamic range (SFDR) and blocking dynamic range (BDR) are interpreted as follows.

(a). Spurious-free dynamic range (SFDR).

The upper bound of SFDR is defined as an input two-tone test signal at which the third-order inter-modulation (IM3) distortion products do not exceed the noise floor, as displayed in Fig. 2.14.

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P in (d B m ) IIP 1 d B P o u t (d B m ) O P -1 d B Slop =1 IIP 3 Δ P 2 Slo p=3 O IP 3 P in , M ax P in , M in N F lo o r N F lo o r S F D R B D R m in S N R

Fig. 2.13 SFDR and BDR defined by the noise floor and linearity parameters.

Noise Floor

IM3

ω

Fig. 2.14 Upper band of SFDR

From Eqs. (2.9) and (2.17), a quick calculation of IM3 is,

2 3 1 3 3 1 3 2 , 1

1

3

4

4

/

3

in in in IM

A

A

A

A

A

α

α

α

α

ω ω

=

(2.35) Substituting Eq. (2.25) into Eq. (2.35) and taking logarithms, yields,

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2 2 3 2 3 1 1 3 4 in IIP in A A A = α α (2.36)

where Ain is the input level at each frequency.

2 2

1, 2 3 3

3 1, 2 3

20 log( ) 20 log( ) 20 log( ) 20 log( ) 1

20 log 20 log( ) 20 log( ) 20 log( ) 2 IM IIP in IIP IM in A A A A A A A A ω ω ω ω − = −   ⇒ = + (2.37) Thus, in out IM out P P P IIP = − + 2 3 , (2.38) out IM

P , represents the power of the IM3 components at the output.

Since Pout =Pin +G and PIM,out =PIM,in +G, where G is the circuit gain, 2

3

3 Pin PIM,in

IIP = − (2.39) The input level for the IM products should become equal to the noise floor.

Thus, ,max 3 3 2 in nf P P IIP = − ⇒ 3 3 2 max , IIP P Pin nf ⋅ + = (2.40) The relationship between SFDR and SNRmin is thus obtained.

min min 3 ) 3 ( 2 ) ( 3 3 2 SNR P IIP SNR P P IIP SFDR nf nf nf − − = ⇒ + − + = (2.41)

(b). Blocking dynamic range (SFDR)

The upper boundary of BDR is the P-1dB compression point, and the overall gain declines to zero since the small signal gain is attenuated by large interference. Figure 2.13 is used to obtain the equation for calculating BDR.

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1dB nF min

BDR =PPSNR (2.42) Attempt to find out the relationship between SFDR and BDR.

Equations (2.26) and (2.41) are manipulated to yield, . 1dB 3 9.64 PIIPdB (2.43) min 3 3 ( ) 2 nf IIP = SFDR+SNR +P (2.44) Thus, 1 min min 3 1 9.64 2 2 dB nF BDR P P SNR SFDR SNR dB = − − ⇒ = + − (2.45)

Both compression and blocking reduce the desired signal and then SNR is degraded.

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Chapter 3.

Design of a 5.5 GHz CMOS Active Mixer

The accuracy of MOSFET model for simulating high frequency characteristic will have direct and dramatic impact on the RF circuit design and performance optimization. A compact CMOS model should cover both active and passive devices, such as MOS transistors, varactors, capacitors, inductors, and resistors. An accurate compact RF CMOS model can help facilitate RF circuit design with increased first-pass success. In this thesis, TSMC 0.18 μ m mixed signal 1P6M silicide 1.8V/3.3V RF CMOS models are used in circuit simulation for the design of a new down-conversion mixer. This chapter discusses the trade-off of RF performance with the minimum noise figure (NFmin), conversion gain, and linearity.

A CMOS based RF amplifier or mixer circuit design can adopt common source and common gate for high-frequency applications. The common source exhibits a high conversion gain, and wide matching bandwidth in the deep-submicron process. The mixer design focuses on the trade-off between various performance parameters, such as the conversion gain, linearity, and flicker noise in the direct conversion receiver.

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3.1 Mixer

In general, the basic mixer architectures can be classified as two major categories, one is the active mixer and another is the passiver mixer. The passive mixer has advantages over the active mixer, such as broadband and high speed due to much smaller junction capacitance, high linearity, dynamic range, and lower flicker noise. However, a passive mixer sometimes suffers disadvantages, such as unsuitability for integration in SoC, inherent conversion loss, poor port-to-port isolation, and high LO power requirement. In the following sections, mixers adopting various topologies will be introduced and discussed.

3.1.1 Passive Mixer

The passive mixer has advantages of high linearity, low noise, and low power. However, the major penalty suffered by the passive mixer is the worse loss in conversion gain.

A passive mixer can utilize MOS transistors or diodes as the basic devices in its circuit architecture. Most of passive diode mixers adopt Schottky diodes as shown in Fig. 3.1(a), mainly because the Schottky diodes represent majority carrier devices, and are faster than p-n junction diodes. MOS transistor is an essential element in active mixers and may be used in passive mixers, as shown in Fig. 3.1(b).

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almost passive or includes a center-tapped transformer, whose integration into SoC will occupy a large area on the chip. The passive mixer is generally popular for applications demanding high-linearity, low-noise, and low-power-consumption.

`

`

180 Balun

IF

LO

Fig. 3.1(a) Passive (Diode) mixer

L O + L O + L O L O -VI F R F i n

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3.1.2 Active Mixer

Gilbert cell is the most popular architecture adopted to build an active mixer and the resulted mixer is generally named as a Gilbert mixer. Figure 3.2(a) and (b) show the single and double balanced mixers, respectively. The noise figure of a typical Gilbert mixer circuit is between around 8~15 dB.

LO + LO -RF r

Vcc

IF + IF +

R

L

R

L M1 M2 M3

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LO + RF + r

Vcc

LO + LO RF -r IF + IF +

R

L

R

L M1 M2 M3 M4 M5 M6

Fig. 3.2(b) Double Balanced Gilbert Mixer

3.2 Design of Low-Power-Consumption Circuit with

LC-Tank

The basic circuit topology of a Gilbert mixer is a kind of cascade architectures incorporating RF stage and LO stage. Therefore, the supply voltages required for a Gilbert mixer have to include one set for LO and another one for RF, as shown in Fig. 3.3. A simplified circuit block in Fig. 3.3 illustrates the DC voltage and RF ground

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signal through the full lines and dotted lines, respectively. The voltage (Vcc) applied to

the drain-to-source of each MOS must be at least double the minimum threshold voltage (Vth_min), i.e. Vcc > 2 Vth_minthe or minimum active component turn-on voltage

(Von), i.e. Vcc > 2 Von, to turn on all active components in normal operation. The

standard Gilbert mixer requires a high voltage to maintain all MOS transistors in normal operating region. As a result, this kind of mixers generally suffer large power consumption. The voltage scaling limitation as identified in RF and LO explains the major bottleneck for low power design using the conventional Gilbert mixer. This work presents a low-voltage circuit design technology based on the LC tank for a down-conversion mixer, as show in Fig 3.4. A voltage is applied to turn on the active MOS transistors of the LO and RF circuits based on LC-tank resonance.

Fig. 3.4. shows a simplified circuit block diagram for the proposed low voltage mixer. The LC tank is designed with a target resonance frequency at 5.5 GHz for wireless applications, such as in 802.11a. The new topology can reduce the total supply voltage and keep LO or RF active elements in normal turn-on. Ideally, the passive components such as inductors (L) or capacitors (C) employed in a LC tank have no power consumption. In this way, the proposed circuit topology can help voltage scaling and achieve low power operation. For the circuit topology adopting a LC tank, there is headroom voltage in the DC equivalent circuit. The bypass capacitor

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is used to couple the RF signal from the RF MOS transistor output to the LO MOS transistor input and isolate the DC bias between the LO and RF stages. The inductors and capacitors are assumed to be ideal and operate at the targetted RF frequency (ωRF).

When the LC-tank operates ideally with a parallel resonant frequency equal to ωRF ,

its equivalent circuit is like an open circuit for an RF signal. Therefore, the minimum supply voltage can be reduced to a turn-on voltage (Von) of a single transistor,

supporting the circuit with a cascade architecture.

LO Element Circuit

RF Element Circuit

Load Element Circuit

` ` `

Vcc

(DC) ` ` RF (Gnd)

Fig. 3.3 A circuit block diagram for a typical Gilbert mixer with RF, LO, and load stages and the applied DC and RF ground (Gnd).

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LO Element Circuit

RF Element Circuit

Load Element Circuit

` `

Vcc

(DC) ` ` RF (Gnd)

LC-Tank

Circuit

LC-Tank

Circuit

`

Vcc

(DC) `

Bypass

Capacitor

Fig. 3.4 A new topology using LC-tank and bypass capacitors for low voltage operation in a Gilbert mixer with applied DC, RF and RF Gnd.

3.3 5.5 GHz CMOS Down-Conversion Mixer

This section describes the combination of multiple gate MOS transistors at RF input, inductors at RF output, LC tanks at both RF and LO stages, bypass capacitors between RF and LO, and output loading capacitors. The low voltage design built on a CMOS Gilbert cell mixer has been described above. In the following section, the design for down-conversion mixing will be described and discussed.

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3.3.1 5.5GHz Down-Conversion Mixer Circuit Block

The 5.5 GHz down-conversion mixer circuit design comprises eight circuit blocks, as shown in Figure 3.5. They are the multiple-gate RF amplifier, the parallel LC-Tank, the bypass capacitor, the local switch, the load circuit, the RF Balun, the LO Balun, and the measuring circuit. QFN package is used to integrate the on-chip and off-chip circuits together.

Fig. 3.5 The proposed CMOS RF mixer block

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off-chip circuit blocks by dotted lines. The off-chip circuits occupy a much larger area than the on-chip circuits. Figure 3.6 displays the whole chip circuit design.

Fig. 3.6 The proposed double balanced RF mixer circuit tolopogies

The CMOS mixer is designed with the low-voltage topology described above. Figures 3.5 and 3.6 are used to represent each circuit block and its function in the proposed RF down-conversion mixer.

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3.3.1.1 LC-Tanks

Manku first utilized LC-tanks for low-voltage design and reported the application in RF circuits [4]. In this work, LC tanks were designed with a target resonant frequency of 5.5 GHz, given by

C L fo ⋅ ⋅ = π 2 1 . A LC tank, at its resonance frequency, operates like an open circuit, as shown in Fig. 3.8. Therefore, LC-tank circuits may solve the problem generally suffered by the typical cascade circuit. The LC tanks required for this design were implemented by off-chip PCB layouts to meet the chip area constraint defined by CiC for test chip tape-out. For the LC tank design, the L value was determined from the calculated capacitance (C) value 0.352pF at a resonant frequency of 5.5 GHz. This thesis proposes RF output pull-up to supply the source low voltage, and LO pull-down to common ground [5].

L= 2.369 nH

C= 0.352 pF

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R F S i g n a l D C C u r r e n t D C C u r r e n t O p e n f o r R F S i g n a l D C C u r r e n t D C C u r r e n t O p e n f o r R F S i g n a l R F S i g n a l V c c L C - T a n k t o M u l t i - g a t e c i r c u i t s L O c i r c u i t t o L C - T a n k t o G N D

Fig. 3.8 Illustration the LC-tank circuit resonating frequency for RF signal and DC biasing status.

3.3.1.2 Multiple Gate MOS Transistors used in RF Input Stage

For an RF front end amplifier, such as used in LNA and mixer applications, high linearity at low power consumption is very important. Some possible solutions for low power design has been mentioned previously. Many approaches have been developed to compensate for non-linearity. For instance, MOSFET operation in a triode region has been used to improve the linearity of the main RF amplifier [5]. B. Kim proposed a new linearization method that is based on multiple gate transistors for the RF amplifier and the mixer in common source integrated circuits [7].

The linearity of LNA and mixer is generally related to the drain current iDS, as

plotted in Fig. 3.9. The linearity model is derived mathematically using Taylor series and Eq. 2.7 is applied to expand the iDS harmonic terms. Eq. 2.7 is rewritten here and

iDS, gm and νgs used instead of y(t), α and )xi(t [7].

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⋅⋅ ⋅ + + + + =         =

∞ = ! 3 ) ( ! 2 ) ( ) ( ) ( ) ( ! 1 3 " 2 ' 0 t v g t v g t v g I t v dv t i d n i gs gs m gs m DC n n gs n gs DS n DS m (3.1)

The coefficient of v3gs is well known to be important in the distortion of third-order inter-modulation (IM3) harmonics of an RF mixer.

+

-V

gs

+

-

g

m

V

gs

+

-V

o

r

o

i

DS

Fig. 3.9 MOSFET small signal model

Figure 3.10 (a) indicates the circuit schematics of a multiple gate topology for circuit simulation to verify its effect on linearity. Fig. 3.10 (b) presents the secondary derivative of transconductances (gm”) of Q1 and Q2, and Fig. 3.10(c) is the effective

gm” as a combination of Q1 and Q2. Sweeping the gate bias (Vgs) in the range of

interest, the first transistor Q1 contributes negative transconductance ",Q1

m

g whereas the secondary transistor Q2 presents positive transconductance ",Q2

m

g . Through appropriate tuning on Vgs applied to Q1 and Q2, gm” can be nearly eliminated in a

certain region of Vgs and the nonlinearity can be reduced. Simulation was carried out

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terms of linearity, conversion gain, and power consumption. The comparison results as shown in Fig.3.6 indicate that multiple gate structure can offer better linearity and conversion gain but suffers larger power consumption. A trade-off must be made between the power consumption and linearity. Table 3.1 makes comparison between single gate and multiple gate structures in terms of power consumption, P-1dB, IIP3, conversion gain, single side band noise (SSB), and double side band noise (DSB) predicted by simulation..

Table 3.1 Comparison between the single gate and multiple gate performance

Simulation Item (Without package model) freq=5500 MHz, LO freq=5490 MHZ

Simple Gate Multiple Gate

Power Consumption 2.51 mW 2.81 mW Linearity of P-1dB 3.689 dBm 6.188 dBm Linearity of IIP3 8.2 dBm 12.2 dBm Conversion Gain 13.318 dB 20.908 dB Single Side Band Noise (LO=2.5 dBm)

26.571 dB 27.27 dB Double Side Band Noise (LO=2.5 dBm)

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0 0 Vcc RF_IN RF_IN Vgs Vgs-Vm C1 Q1 Nr=18 R1 Q2 Nr=20 C2 R2

Fig. 3.10 (a) Multiple gated circuit topology.

(b)

(c) Fig. 3.10 (b) "

m

g of Q1 and Q2 (c) the effective "

m

g resulted from combining Q1

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3.3.1.3 RF Output Inductors

An inductor was in series with the RF output to increase the conversion gain available at mixer output [3]. The inductance of around 3.799 nH was adopted to optimize the output matching and improve the conversion gain. Then, the first phase design for RF stage is completed for the downconversion mixer as shown in Fig. 3.5. This circuit design improves the linearity by using multiple gate amplifier at transconductance stage and increases the conversion gain by using inductors at RF output. However, a large chip area consumed by the inductors for output matching becomes a major penalty in terms of cost and chip area utilization.

Vdd_1.0 V Vcc_1.0 V Vcc_1.0 V Vdd_1.1 V C6 0.11 pF C7 0.11 pF Q8 nr=40 Q5 nr=16 Q3 Nr=16 Q2 nr=20 C11 0.352 pF L7 3.799 nH C8 0.11 pF L3 2.369 nH L10 2.369 nH R1 1 K Q4 nr=20 L9 2.369 nH Q6 nr=50 L6 2.369 nH L1 1.4 nH C4 0.5787 pF Q1 Nr=16 L5 2.369 nH Q7 nr=16 C5 0.11 pF C3 0.5787 pF L8 3.799 nH C2 0.5787 pF C9 0.352 pF L2 1.4 nH L4 2.369 nH C1 0.5787 pF Ideal Balun Terminal 2 50 Ohm Terminal 1 50 Ohm

Fig. 3.11 Circuit schematics with RF amplifier, input and output Baluns for simulation and first phase design of the mixer

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