6.3.1 P+N Ge Junction Characteristics
Figure 6.2 displays the effects of FGA on the junction characteristics of Ge p-FETs that had been subjected to dopant activation at 500 °C. The reverse leakage current density (JR) for the as-activated junction was 2 × 10–2 A cm–2 at –1 V. A gradual increase in JR occurred for temperatures above 500 °C (not shown), possibly because of a rougher surface morphology or a smaller dopant loss [22]. We suspect that the value of JR obtained in this case arose mainly from the contribution of the generation current, which is dependent on not only the level of substrate doping but also the extent of residual metal contamination after surface cleaning [23]
or device fabrication processing. A larger resultant depletion width for a substrate having lower levels of doping and metal contamination will obviously lead to more defects—including both bulky defects in the Ge substrate and on the surface states at the isolation region—residing inside the depletion region; in turn, this phenomenon will result in a larger generation current. Because the doping level of the substrate used here was as low as 1 × 1014 cm–3, we believe that, rather than metal contamination, defects arising from Ge wafer manufacturing and our employed isolation techniques were the primary culprits for the observed high leakage current [24]. Using previously reported equations for calculating the
diffusion (Jdiff) and generation (Jgr) current densities in a diode [14], we estimated the values of Jdiff and Jgr to be ca. 2.8 × 10–4 and 1 × 10–2 A cm–2, respectively, for our low-doped (1014 cm–3) n-Ge substrate—assuming the presence of a bulk trap density (NT) of 1015 cm–3 and a capture cross-section of 10–15 cm–2 [4], [26], [27]. Consistent with our experimental results, the value of Jgr prevailed over that of Jdiff to dominate the junction leakage. This behavior is consistent with a recent report in which the value of JR increased significantly in a Ge p+n junction when the substrate doping was as low as ca. 1015 cm–3, due to the enhanced rate of generation of thermally activated electron/hole pairs in the depletion layer [28]. Using a MEDICI simulator, those authors predicted this substrate dopant-level dependence of the Ge junction leakage, which was not observed in the Si counterpart. As a result, we think that the density of the defects in the Ge substrate shall be indispensably eliminated in order to obtain better electrical property of the diode.
We found that performing the FGA process mainly impacted the degree of reverse leakage and slightly enhanced the forward current of the diode. The inset to Fig. 6.2 presents the Weibull plots of the values of JR at a reverse bias (VR) of –1 V. Performing FGA at a low temperature of 300 °C decreased the value of JR to 10–2 A cm–2, whereas it increased continuously to 3 × 10–2 and 10–1 A cm–2 at FGA temperatures of 350 and 400 °C, respectively.
We suspect that the FGA process induced junction degradation as a result of the increased roughness around the contact hole periphery that accompanied bulk-trap generation during Al-germanide formation. Similar phenomena, either the presence of voids of different sizes [29] or metal-induced deep traps inside Ge [30], have been characterized during the formation of Ni- and Co-germanides. Scanning electron microscopy (SEM) images (not shown) did not reveal the formation of any voids after FGA at 400 °C; we did, however, observe an increase in morphological damage of the S/D metal pads, but not in the gate and channel regions.
6.3.2 Device, Reliability, and Mobility Characteristics
Several studies have demonstrated that FGA or pure H2 annealing can result in improved high-k/Ge interfaces [3], [7], [31]. Using the conductance method and charge pumping measurements, we did indeed obtain a lower value of Dit of 8 × 1011 cm–2 eV–1 for the MOS capacitors after performing FGA at 300 °C. Hence, we anticipated that the fabricated p-FETs would exhibit enhanced performance as a result of improvements to both the p+n junction and the dielectric interface. Figs. 6.3(a) and 6.3(b) display the respective Ids–Vgs and Ids–Vds
characteristics of the p-FETs fabricated with and without FGA. Not surprisingly, the devices subjected to FGA at 300 °C exhibited superior performance: a higher drive current (ca. 1.8×), a better on-off current ratio (greater than three orders of magnitude), a lower leakage current, and a reduced subthreshold swing (SS) of ca. 185 mV decade–1.
Negative bias temperature instability (NBTI) is an important reliability issue for high-k dielectrics on Si, and also on Ge. Figs. 6.4(a)–(d) present results for device degradation in terms of changes in the values of Isat, the transconductance maximum (Gm), and SS and the Vth
shift under NBTI stress. We applied two stress biases (–3.0 and –3.2 V) to the Ge p-FET samples. In the absence of hydrogen passivation, we detected severe electrical deterioration after applying the stress for 103 s, notably a value of ΔId/Id of 23–35%, a value of ΔGm/Gm of ca. 10%, rapid degradation in the value of SS, and a large negative Vth shift (>250 mV).
Because the mechanisms occurring during the NBTI degradation for high-k gate dielectrics are similar to those observed in SiO2 [32], we suspected that subsequent FGA might aid in effectively repairing dangling bonds and defects inside the GeOx IL, in turn boosting the dielectric quality and interfacial reliability. Fig. 6.5 presents a plot of the extracted channel hole mobility with respect to the effective electric field, together with data reported in two previous publications [7], [33]. Our ALD-Al2O3/Ge p-FET exhibited superior mobility behavior over the Si hole universal curve. The peak mobility was ca. 225 cm2 V–1 s–1, an improvement of ca. 25%. This value is comparable with that for an NH3-nitrided HfO2/Ge structure, but poorer than that for a reported HfO/Ge structure that had been subjected to Si
passivation. As a result, we believe that adopting an ultra-thin Si capping layer—the thickness of which needs optimization—should further improve the channel mobility [34], [35]. In addition, the techniques employed for deposition and Ge surface preparation are critical in determining the quality of this Si IL and the resultant improvement in mobility in the Ge devices.
6.4 Effect of Dopant Activation on N+P Ge Junction