Since forming a good Ohmic contact is essential to achieve the excellent performance of D-mode GaAs nMOSFET, therefore, the AES depth profiles of alloyed Au/Ge/Ni tri-layer on GaAs were analyzed in Figs. 6.12(a) and 6.12(b), respectively. Alloying at 400 °C caused extensive interdiffusion between metal layer and GaAs substrate with respect to the as-deposited profile. Both Ge and Ni diffused onto the top surface and also interacted with GaAs severely. Further from the TEM image in Fig. 6.13(b), Ni and Ge reacted with each other not only forming a NiGe compound (in the ratio of 1:1) in the upper layer but also causing pits inside the GaAs substrate. Some traces of Ga and As were also detected in the upper metal alloys. These findings showed the similar behavior to the several reported studies [45]-[47], and the reaction mechanism was also widely investigated [46], [47]. With the analysis of transfer length method (TLM), the measured specific contact resistivity was 2.9 × 10-5 Ω·cm2, acting a good Ohmic contact. Fig. 6.13(a) shows the TEM image of the overall GaAs n-MOSFET structure. The average distance between the Al gate and the AuGeNi S/D was ca. 3 um and also the rough morphology of AuGeNi alloy was observed at the S/D region.
From the zoom in picture of the Al/ALD-Al2O3/n-GaAs in Fig. 6.13(c), the physical dielectric thickness was 12.5(±0.5) nm, which corresponded to have the CET value of 5.4 nm.
Figure 6.14(a) illustrates the Id–Vg transfer characteristics in the linear and saturations for D-mode ALD-Al2O3/GaAs n-FET with (NH4)2S-C4H9OH interfacial passivation. For device with the gate length/width of 5/100 μm, the values of Vth was -3.8 V and the values of Gm at Vd = 1.1/3.1 V were 43/59 mS/mm, respectively. In addition, well saturation and pinch-off characteristics were presented in the Id–Vd curves [Fig. 6.14(b)] with the gate
overdrive Vg-Vth ranging from -1.2 to 4.8 V in steps of 1 V. The maximum Id was 250 mA/mm measured at Vg-Vth = 4.8 V, Vd = 4 V. The extracted peak electron mobility was only 336 cm2V-1s-1, higher than the value of 212 cm2V-1s-1 for the non-sulfidized GaAs device (not shown here). But, the device properties are still not comparable to the reported performance of D-mode HfO2/GaAs devices with α-Si interfacial passivation layer [48]. This may be correlated to a higher Dit still existed at the dielectric-GaAs interface. Further modulation of the ALD film deposition as well as optimization of the wet-chemical clean and PDA processes are required. Here, we want to reassert that executing the sulfidization with the solvents of lower dielectric constant, e.g., (NH4)2S + C4H9OH, is relatively effective to improve the quality of GaAs surface prior to high-k deposition. It is also possible to implant this chemical treatment along with other passivation methods in pursuit of superior high-performance high-k/III-V n-MOSFET.
6.7 Conclusions
In Chapter 6, we investigated the characteristics of Ge junction diodes and gate-last p- and n-MOSFETs with the ALD-Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p+n and n+p junctions exceeded three and four orders of magnitude (in the voltage range of ±1 V), respectively, with accompanying reverse leakages of ca. 10–2 and 10–4 A cm–2, respectively. It was also found that the origin of the leakage path, governed by surface perimeter or junction area, was mainly dependent on the thermal budgets adopted in devices (i.e., dopant activation and FGA). In addition, performing FGA at 300 °C boosted the device on-current, decreased the Al2O3/Ge interface states to 8 × 1011 cm–2 eV–1, and improved the reliability of bias temperature-instability. The peak mobility and on/off ratio reached as high as 225 cm2 V–1 s–1 and >103, respectively, for the p-FET (W/L = 100 μm/4 μm), while these values were less than 100 cm2 V–1 s–1 and ca. 103, respectively, for the n-FET (W/L = 100
μm/9 μm). The relatively inferior n-FET performance resulted from the larger S/D contact resistance, higher surface states scattering, and lower substrate doping concentration.
In accordance with the studies of (NH4)2S-C4H9OH chemical passivation on GaAs substrate in Chapter 5, herein, we employed such an alcoholic sulfide treatment to fabricate the D-mode GaAs n-MOSFETs and successively demonstrated their transfer and output characteristics. The maximum Id was 250 mA/mm measured at Vg-Vth = 4.8 V, Vd = 4 V. The extracted peak electron mobility was only 336 cm2V-1s-1, indicative of the more optimization in the dielectric/GaAs interface quality. Perhaps, the (NH4)2S-C4H9OH treatment can be adopted on the InGaAs/InSb substrates or integrates with other passivation methods to provide the better surface quality for realizing high-performance high-k/III-V devices.
References (Chapter 6)
[1] H. Matsubara, T. Sasada, M. Takenaka, and S. Takagi, “Evidence of low interface trap density in GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation,” Appl. Phys. Lett., vol. 93, p. 032104, 2008.
[2] N. Wu, Q. Zhang, D. S. H. Chan, N. Balasubramanian, and C. Zhu, “Gate-first Germanium nMOSFET with CVD HfO2 gate dielectric and silicon surface passivation,”
IEEE Electron Devices Lett., vol. 27, p. 479, 2006.
[3] T. Maeda, M. Nishizawa, Y. Morita, and S. Takagi, “Role of germanium nitride interfacial layers in HfO2/germanium nitride/germanium metal-insulator-semiconductor structures,”
Appl. Phys. Lett., vol. 90, p. 072911, 2007.
[4] J. Vanhellemont and E. Simoen, “Brother silicon, sister germanium,” J. Electrochem. Soc., vol. 154, p. H572, 2007.
[5] E. Simoen, A. Satta, M. Meuris, T. Janssens, T. Clarysse, C. Demeurisse, B. Brijs, I.
Hoflijk, W. Vandervorst, and C. Claeys, “Defect removal, dopant diffusion and activation issues in ion-implanted shallow junctions fabricated in crystalline germanium substrates,”
Solid State Phenom., vol. 108–109, p. 691, 2005.
[6] D. Kuzum, A. J. Pethe, T. Krishnamohan, and K. C. Saraswat, “Ge (100) and (111) n- and p-FETs with high mobility and low-T mobility characterization,” IEEE Trans. Electron Devices, vol. 56, p. 648, 2009.
[7] P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L.-A. Ragnarsson, D.
P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M.
Heyns, “High performance Ge pMOS devices using a Si-compatible process flow,” in Tech. Dig. Int. Electron Device Meet., p. 655, 2006.
[8] H.-C. Chin, M. Zhu, Z.-C. Lee, X. Liu, K.-M. Tan, H. K. Lee, L. Shi, L.-J. Tang, C.-H.
Tung, G.-Q. Lo, L.-S. Tan, and Y.-C. Yeo, “A new silane-ammonia surface passivation technology for realizing inversion-type surface-channel GaAs n-MOSFET with 160 nm
gate length and high-quality metal-gate/high-k dielectric stack,” Tech. Dig. Int. Electron Devices Meet., p. 383, 2008.
[9] N. Goel, D. Heh, S. Koveshnikov, I. Ok, S. Oktyabrsky, V. Tokranov, R. Kambhampati, M. Yakimov, Y. Sun, P. Pianetta, C.K. Gaspe, M.B. Santos, J. Lee, S. Datta, P. Majhi, and W. Tsai, “Addressing the gate stack challenge for high mobility InxGa1-xAs channels for nFETs,” Tech. Dig. Int. Electron Devices Meet., p. 363, 2008.
[10] M. Radosavljevic, T. Ashley, A. Andreev, S. D. Coomber, G. Dewey, M. T. Emeny, M.
Fearn, D. G. Hayes, K. P. Hilton, M. K. Hudait, R. Jefferies, T. Martin, R. Pillarisetty, W.
Rachmady, T. Rakshit, S. J. Smith, M. J. Uren, D. J. Wallis, P. J. Wilding and R. Chau,
“High-performance 40nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (Vcc=0.5V) logic applications,” Tech. Dig. Int.
Electron Devices Meet., p. 727, 2008.
[11] T. H. Chiang, W. C. Lee, T. D. Lin, D. Lin, K. H. Shiu, J. Kwo, W. E. Wang, W. Tsai, and M. Hong, “Approaching Fermi level unpinning in oxide-In0.2Ga0.8As,” Tech. Dig. Int.
Electron Devices Meet., p. 375, 2008.
[12] P. D. Ye, “Main determinants for III–V metal-oxide-semiconductor field-effect transistors (invited),” J. Vac. Sci. Technol. A., vol. 26, p. 697, 2008.
[13] A. Saletes, J. Massies, and J. P. Contour, “Residual carbon and oxygen surface contamination of chemically etched GaAs (001) substrates,” Jpn. J. Appl. Phys. vol. 25, p. L48, 1986.
[14] S. Goto, M. Yamada, and Y. Nomura, “Surface cleaning of Si-doped/undoped GaAs substrates,” Jpn. J. Appl. Phys. vol. 34, p. L1180, 1995.
[15] F. Zhu, H. Zhao, I. Ok, H. S. Kim, J. Yum, J. C. Lee, N. Goel, W. Tsai, C. K. Gaspe, and M. B. Santos, “Effects of anneal and silicon interface passivation layer thickness on device characteristics of In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors,” Electrochem. Solid-State Lett., vol. 12, p. H131, 2009.
[16] H.-C. Chin, M. Zhu, G. S. Samudra, and Y.-C. Yeo, “n-channel GaAs MOSFET with TaN/HfAlO gate stack formed using in situ vacuum anneal and silane passivation,” J.
Electrochem. Soc., vol. 155, p. H464, 2008.
[17] H.-C. Chin, M. Zhu, X. Liu, H.-K. Lee, L. Shi, L.-S. Tan, and Y.-C. Yeo,
“Silane–ammonia surface passivation for gallium arsenide surface-channel n-MOSFET,” IEEE Electron Device Lett., vol. 30, p. 110, 2009.
[18] C.-C. Cheng, C.-H. Chien, G.-L. Luo, C.-H. Yang, C.-K. Tseng, H.-C. Chiang, and C.-Y.
Chang, “Improved electrical properties of Gd2O3/GaAs capacitor with modified wet-chemical clean and sulfidization procedures,” J. Electrochem. Soc., vol. 155, p. G56, 2008.
[19] F. Bellenger, M. Houssa, A. Delabie, V. Afanasiev, T. Conard, M. Caymax, M. Meuris, K. D. Meyer, and M. M. Heyns, “Passivation of Ge(100)/GeO2/high-k gate stacks using thermal oxide treatments,” J. Electrochem. Soc., vol. 155, p. G33, 2008.
[20] M. S.-Mathur, Y.-C. Perng, J. Lu, H.-O. Blom, J. Bargar, and J. P. Chang, “The effect of aluminum oxide incorporation on the material and electrical properties of hafnium on Ge,” Appl. Phys. Lett., vol. 93, p. 233501, 2008.
[21] J. J.-H. Chen, N. A. Bojarczuk, J. H. Shang, M. Copel, J. B. Hannon, J. Karasinski, E.
Preisler, S. K. Banerjee, and S. Guha, “Ultrathin Al2O3 and HfO2 gate dielectrics on surface-nitrided Ge,” IEEE Trans. Electron Devices, vol. 51, p. 1441, 2004.
[22] Y. Kamata, Y. Kamimuta, T. Ino, R. Iijima, M. Koyama, and A. Nishiyama, “Influences of annealing temperature on characteristics of Ge p-channel metal oxide semiconductor field effect transistors with ZrO2 gate dielectrics,” Jpn. J. Appl. Phys., vol. 45, p. 5651, 2006.
[23] Y. Kamata, T. Ino, M. Koyama, and A. Nishiyama, “Improvement in C–V characteristics of Ge metal-oxide semiconductor capacitor by H2O2 incorporated HCl pretreatment,”
Appl. Phys. Lett., vol. 92, p. 063512, 2008.
[24] A. Satta, G. Nicholas, E. Simoen, M. Houssa, A. Dimoulas, B. D. Jaeger, J. V.
Steenbergen, and M. Meuris, “Impact of germanium surface passivation on the leakage current of shallow planar p–n junctions,” Mater. Sci. Semi. Proc., vol. 9, p. 716, 2006.
[25] E. Simoen, S. Sonde, C. Claeys, A. Satta, B. De Jaeger, R. Todi, and M. Meuris,
“Processing factors impacting the leakage current and flicker noise of germanium p+n junctions on silicon substrates,” J. Electrochem. Soc., vol. 155, p. H145, 2008.
[26] P. Batude, X. Garros, L. Clavelier, C. Le Royer, J. M. Hartmann, V. Loup, P. Besson, L.
Vandroux, Y. Campidelli, S. Deleonibus, and F. Boulanger, “Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks,” J. Appl. Phys., vol. 102, p. 034514, 2007.
[27] E. Simoen, C. Claeys, S. Sioncke, J. V. Steenbergen, M. Meuris, S. Forment, J.
Vanhellemont, P. Clauws, and A. Theuwis, “Lifetime and leakage current considerations in metal-doped germanium,” J. Mater. Sci.: Mater. Electron., vol. 18, p.
799, 2007.
[28] G. Eneman, M. Wiot, A. Brugère, O. S. I. Casain, S. Sonde, D. P. Brunco, B. D. Jaeger, A. Satta, G. Hellings, K. D. Meyer, C. Claeys, M. Meuris, M. M. Heyns, and E. Simoen,
“Impact of donor concentration, electric field, and temperature effects on the leakage current in germanium p+/n junctions,” IEEE Trans. Electron Devices, vol. 55, p. 2287, 2008.
[29] D. P. Brunco, K. Opsomer, B. D. Jaeger, G. Winderickx, K. Verheyden, and M. Meuris,
“Observation and suppression of nickel germanide overgrowth on germanium substrates with patterned SiO2 structures,” Electrochem. Solid-State Lett., vol. 11, p. H39, 2008.
[30] K. Opsomer, E. Simoen, C. Claeys, K. Maex, C. Detavernier, R. L. V. Meirhaeghe, S.
Forment, and P. Clauws, “A deep-level transient spectroscopy study of Co- and Ni-germanided n-type germanium,” Mater. Sci. Semi. Proc., vol. 9, p. 554, 2006.
[31] C.-C. Cheng, C.-H. Chien, G.-L. Luo, J.-C. Liu, C.-C. Kei, D.-R. Liu, C.-N. Hsiao, C.-H.
Yang, and C.-Y. Chang, “Characteristics of atomic-layer-deposited Al2O3 high-k dielectric films grown on Ge substrates,” J. Electrochem. Soc., vol. 155, p. G203, 2008.
[32] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F.Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on high-κ dielectrics reliability issues,” IEEE Trans. Device Mater. Rel., vol. 5, p. 5, 2005.
[33] N. Wu, Q. Zhang, N. Balasubramanian, D. S. H. Chan, and C. Zhu, “Characteristics of self-aligned gate-first Ge p- and n-channel MOSFETs using CVD HfO2 gate dielectric and Si surface passivation,” IEEE Trans. Electron Devices, vol. 54, p. 733, 2007.
[34] N. Taoka, M. Harada, Y. Yamashita, T. Yamamoto, N. Sugiyama, and S.-I. Takagi,
“Effects of Si passivation on Ge metal-insulator-semiconductor interface properties and inversion-layer hole mobility,” Appl. Phys. Lett., vol. 92, p. 113511, 2008.
[35] D. P. Brunco, B. D. Jaeger, G. Eneman, A. Satta, V. Terzieva, L. Souriau, F. E. Leys, G.
Pourtois, M. Houssa, K. Opsomer, et al., “Germanium: the past and possibly a future material for microelectronics,” ECS Trans., vol. 11, p. 479, 2007.
[36] M. Posselt, B. Schmidt, W. Anwand, R. Grotzschel, V. Heera, A. Mucklich, C.
Wundisch, W. Skorupa, H. Hortenbach, S. Gennaro et al., “P implantation into preamorphized germanium and subsequent annealing: solid phase epitaxial regrowth, P diffusion, and activation,” J. Vac. Sci. Technol. B, vol. 26, p. 430, 2008.
[37] A. Satta, E. Simoen, R. Duffy, T. Janssens, T. Clarysse, A. Benedetti, M. Meuris, and W.
Vandervorst, “Diffusion, activation, and recrystallization of high dose P implants in Ge,”
Appl. Phys. Lett., vol. 88, p. 162118, 2006.
[38] A. Satta, T. Janssens, T. Clarysse, E. Simoen, M. Meuris, A. Benedetti, I. Hoflijk, B. D.
Jaeger, C. Demeurisse, and W. Vandervorst, “P implantation doping of Ge: diffusion, activation, and recrystallization,” J. Vac. Sci. Technol. B, vol. 24, p. 494, 2006.
[39] S. Brotzmann and H. Bracht, “Intrinsic and extrinsic diffusion of phosphorus, arsenic, and antimony in germanium,” J. Appl. Phys., vol. 103, p. 033508, 2008.
[40] R. Xie, N. Wu, C. Shen, and C. Zhu, “Energy distribution of interface traps in germanium metal-oxide-semiconductor field effect transistors with HfO2 gate dielectric and its impact on mobility,” Appl. Phys. Lett., vol. 93, p. 083510, 2008.
[41] M. Kobayashi, A. Kinoshita, K. Saraswat, H.-S. P. Wong, and Y. Nishi, “Fermi-level depinning in metal/Ge Schottky junction and its application to metal source/drain NMOSFET,” Tech. Dig. VLSI Symp., p. 54, 2008.
[42] Q. Zhang, J. Huang, N. Wu, G. Chen, M. Hong, L. K. Bera, and C. Zhu, “Drive-current enhancement in Ge n-channel MOSFET using laser annealing for source/drain activation,” IEEE Electron Devices Lett., vol. 27, p. 728, 2006.
[43] S. J. Whang, S. J. Lee, F. Gao, N. Wu, C. X. Zhu, J. S. Pan, L. J. Tang, and D. L. Kwong,
“Germanium p- & n-MOSFETs fabricated with novel surface passivation (plasma-PH3
and thin AlN) and TaN/HfO2 gate stack,” Tech. Dig. Int. Electron Device Meet., p. 307, 2004.
[44] A. Dimoulas, P. Tsipas, A. Sotiropoulos, and E. K. Evangelou, “Fermi-level pinning and charge neutrality level in germanium,” Appl. Phys. Lett., vol. 89, p. 252110, 2006.
[45] L. David, B. Kovacs, I. Mojzes, B. Pecz, and J. Labar, “Electrical and microstructure analysis of Ni/Ge/n-GaAs interface,” Thin Solid Films, vol. 323, p. 212, 1998.
[46] H. R. Kawata, T. Oku, A. Otsuki, and M. Murakami, “NiGe-based ohmic contacts to n-type GaAs. II. Effects of Au addition,” J. Appl. Phys. vol. 75, p. 2530, 1994.
[47] H. S. Lee, M. W. Cole, R. T. Lareau, S. N. Schauer, D. C. Fox, D. W. Eckart, R. P.
Moerkirk, W. H. Chang, K. A. Jones, S. Elagoz, W. Vavra, and R. Clarke, “The microstructure and electrical properties of nonalloyed epitaxial Au-Ge ohmic contacts to n-GaAs,” J. Appl. Phys. vol. 72, p. 4773, 1992.
[48] F. Zhu, S. Koveshnikov, I. Ok, H. S. Kim, M. Zhang, T. Lee, G. Thareja, L. Yu, J. C.
Lee, W. Tsai, V. Tokranov, M. Yakimov, and S. Oktyabrsky, “Depletion-mode GaAs metal-oxide-semiconductor field-effect transistor with amorphous silicon interface
passivation layer and thin HfO2 gate oxide,” Appl. Phys. Lett. vol. 91, p. 043507, 2007.
Fig. 6.1 Scheme of the depletion-mode GaAs n-MOSFET structure.
-2 -1 0 1 2
10-2 10-1 100 101 102
10-2 10-1
10-1 100 101
-ln(1-F)
Jden.@ -1 V (A/cm2)
Junction current Jden.(A/cm2 )
Voltage (V)
w/o FGA 300oC FGA 350oC FGA 400oC FGA
Fig. 6.2 I–V characteristics of p+n junctions activated at 500 °C, before and after performing FGA. Inset: Weibull plot of the value of JR at VR = –1 V.
-5 -4 -3 -2 -1 0 1
100 101 102 103
Fig. 6.4 NBTI characteristics of ALD-Al2O3/Ge p-FETs prepared with and without FGA at 300 °C.
Fig. 6.5 Effective hole mobility of ALD-Al2O3/Ge p-FETs plotted with respect to the effective field; published mobility data are also presented [7], [33].
Fig. 6.6 Effects of activation conditions and SiO2 capping layer on the n+p junction characteristics: (a) 500–700 °C, 30 s, without SiO2; (b) 600–700 °C, 30 s, with SiO2; (c) 700 °C, 30–90 s, with SiO2.
Fig. 6.7 SIMS depth profiles of the P-implanted Ge junctions discussed in Fig. 5: (a) 500–700 °C, without SiO2; (b) 600–700 °C, with SiO2; (c) 30–90 s, with and without SiO2. Inset: Expanded image of the SIMS profile at the surface region (<100 nm).
Fig. 6.8 (a) Schematic representation of the contact and transport resistances between two Al metal pads within the same P-implanted region. (b) Extraction of the values of Rtotal, Rtran, and Rcont under various activation conditions and SiO2
capping effects. The gray region labels are values equal to two times the respective values of Rcont (i.e., 2Rcont).
Fig. 6.9 Characteristics of n+p junction currents normalized by the (a) diode area and (b) diode perimeter. (c) Extraction of the perimeter leakage component Jp as functions of the activation conditions and SiO2 capping effects. Inset:
Schematic representation of the two main leakage paths (Jp and JA) at the S/D contact region; JA comprises the generation-recombination current (Jgr) and diffusion current (J ).
Fig. 6.10 Effects of FGA at 300 °C on the (a) Ids–Vgs and (b) Ids–Vds characteristics of ALD-Al2O3/Ge n-FETs (W/L = 100 μm/8.8 μm).
0.0 0.1 0.2 0.3 0.4 0.5 0.6
Fig. 6.11 Effective electron mobility of ALD-Al2O3/Ge n-FETs plotted with respect to the effective field; published mobility data are also presented [33], [42], [43].
4000 3000 2000 1000 0
Fig. 6.12 AES depth profiles of the Au/Ge/Ni S/D Ohmic contact (a) before and (b) after 400 °C for 1 min, respectively.