2.3.1 Structure and Composition Analyses
Figure 2.1 shows cross-sectional TEM image of as-deposited Pt/HfOxNy/Ge structure.
We characterized that the thicknesses of the HfOxNy bulk film and the IL were ca. 73 Å and ca.
19 Å, respectively. When HfOxNy/Ge system undergoes high-temperature process, of primary interest is the resultant germanium diffusion in the overlying HfOxNy films. As the SIMS depth profiles illustrated in Fig. 2.2, we observed a large Hf tail—a known SIMS artifact—at the end of the HfOxNy layer, and ion yield enhancements of both Ge and Hf at the beginning of the Ge substrate. Discarding these artificial phenomena, a U-shaped distribution of Ge did exist inside the overlying HfOxNy layer. From the concentration levels, we suggest that the higher thermal annealing indeed enhanced the incorporation of Ge, relative to the concentration in low-temperature processed sample. Assuming that the composition is the mixture of HfOxNy and GeOxNy, we evaluated the amount of incorporated Ge quantitatively through XPS measurements because of the lack of sputtering yield information for Ge in the HfOxNy layer. Considering the respective atomic sensitivity factors of the Ge 2p3, Hf 4f, O 1s, and N 1s core levels, we estimated an average Ge concentration of ca. 12(±1.4) at.% in their overlying high-k layers for the 400 °C-processed sample, with the values increasing to ca.
19.3(±2) at.% after 500 °C PDA for 5 min. Such a low-temperature annealing has led to severe Ge incorporation into the HfOxNy dielectric film. Note that the maximum sampling depth is ca. 45 Å in Ge 2p3 spectrum, and it exactly involves in a U-shaped distribution of Ge within the high-k films, therefore, we use an average value for evaluating the Ge contamination. These Ge atoms are incorporated in the form of GeOx through both external
and internal contamination mechanisms. A higher surface concentration of Ge oxide in the SIMS analyses has been identified as arising from gaseous GeO species diffusing out from the substrate and downward into the high-k layer via airborne transportation; the contamination depth has been estimated to be ca. 20 Å—at least for high-k thin films deposited on Ge substrates [21]. This kind of surface contamination, however, can be further suppressed by capping a thick SiO2 layer onto the back side of the Ge substrate prior to performing the annealing process. In addition, bulk contamination of GeOx may result from the desorption of a defective GeOx-containing IL and/or the oxidation of the Ge substrate due to residual oxygen existing in a N2 ambient [22].
2.3.2 Capacitance and Conductance Characteristics
Figure 2.3 displays multi-frequency C–V characteristics of Pt/HfOxNy/Ge capacitors before and after performing the 500 °C PDA and PMA, respectively. It should be pointed out that the sweep direction in all of the curves presented here is from strong accumulation to strong inversion and they seem not to reach fully saturation in the accumulation regimes. This phenomenon can be reasonably understood in term of fast detrapping of the trapped charges during the C–V sweep; on the contrary, when the voltage is swept from inversion to accumulation, the normal saturation behavior in C–V curves can be seen, as the results shown in Fig. 6. Here, we extracted the capacitance-equivalent-thickness (CET) at a value of Vg of +2 V in the C–V curves was ca. 28 Å for as-deposited sample; it decreased to ca. 27 Å and ca.
26 Å after PDA and PMA, respectively. Extending the annealing duration to 5 min leads to further CET reduction of ca. 23 Å (not shown here), and it partly arises from the shrinkage of the IL [22] due to the fact that Ge does not prefer to form the germinate HfGeO4 [23], [24]—unlike Si, which readily forms HfSiO4—through reaction with Hf. In addition, we observed that the C–V stretch-out behavior with the hump emerged in depletion for all
samples, indicating the existence of a large density of interface states at the dielectric interface.
Considering the frequency dependence of the interface properties, the deviation of the 10 kHz curve with respect to the 1 MHz curve was obviously abated by performing subsequent annealing processes. In particular, the PMA-processed sample revealed a deeper “dip＂ in depletion, indicative of its improved interface quality. The quantitative analyses of the Dit
showed that the as-deposited HfOxNy/Ge gate stack revealed a large value of Dit of ca. 8 × 1012 cm–2.eV–1 and it reduced to the value of Dit of ca. 3.5 × 1012 and ca. 1.4 × 1012 cm–2.eV–1 for the PDA and PMA samples, respectively. Interface traps and dangling-bond defects existing in near-interfacial Ge oxide or Ge oxynitride have been characterized in HfO2/Ge system [25]. Recently, C. O. Chui et al. also examined that the level of Dit was quite high and still on the order of 1012 cm–2.eV–1 for GeOxNy/Ge gate stack even though receiving forming-gas anneal (FGA) [26]. As a result, we believe that a higher value of Dit presented at the HfOxNy/Ge interface should be associated with poor quality of the defective GeOx IL.
Figure 2.4 presents the corresponding G–V curves of Pt/HfOxNy/Ge gate stacks measured at 100 kHz; the result of Pt/HfOxNy/Si control sample is also shown for comparison.
The G–V traces obviously exhibit an interface loss peak, corresponding to the hump observed in C–V depletion. The PMA process reduced the conductance peak that emerged in the G–V curve of the as-deposited sample to a greater extent than did the PDA process, which is consistent with the examination of Dit. Another noteworthy feature is that we measured a high value of conductance in inversion and it displayed gate-bias independence; this finding is rare for traditional Si MOS capacitors [27]. Generally, the equivalent parallel conductance passes through a peak in weak inversion and drops immediately to a very low value in strong inversion; in other words, an exponential decline of the conductance values should occur, like Si case shown here. In contrast, we observed gate-bias-independent conductance in inversion in our case, suggesting that the minority carriers in the Ge substrate, formed either through the generation/recombination via midgap trap levels or through a diffusion mechanism—do
indeed contribute an energy loss in inversion and compete with interface-state loss in depletion [28]. Y. Fukuda et al. have investigated the GeOxNy/Ge interface properties through the conductance method [29] and they also simultaneously explored the identical inversion conductance [30]. We have observed the anomalous G–V characteristics on low-doped (~1014 cm-3) Ge substrate for both types; this behavior can be minimized by increasing dopant concentration. C. O. Chui et al. characterized the gate-bias-independent conductance in inversion for MOS capacitors with GeOxNy dielectric thin film on n-type (ca. 1016 cm–3) Ge substrate, but not on p-type (ca. 5 × 1017 cm–3) Ge substrate [26]. We suggest that the onset of this strange behavior in Ge capacitor is strongly dependent on the substrate doping level because this in turn determines the amount of minority carrier and corresponding response time. Moreover, we noticed that the measured capacitance and conductance rose after different thermal processes, which are a typical characteristic of the increased number of bulk traps, presumably caused by impurity atoms introduced during high-temperature annealing.
These induced bulky defects in Ge, with energy levels near the midgap, not only contribute to greater bulk trap loss but also enhance the supply of minority carriers to the inversion layer, incurring the low-frequency-like behavior in the 10-kHz C–V curves. We suggest that both thermal mechanisms are significant in Ge because of a large intrinsic carrier concentration (ca.
2 × 1013 cm–3) since they obviously affect the room-temperature C–V characteristics measured at high frequencies—even as high as 1 MHz [31].
2.3.3 Flatband Voltage Shift and Gate Leakage Characteristics
As indicated in Fig. 2.5, we examine the variation of the VFB shift (the left-hand axis) and the gate leakage current Jg (the right-hand axis) with respect to the annealing temperature.
It can be seen that the value of VFB for the as-deposited sample (ca. 0.35 V) is lower than the value of the ideal work-function difference (ca. 0.9 eV) between a Pt gate and n-Ge substrate,
implying that a substantial number of positive charges have been introduced into the gate dielectric/IL bi-layer. High temperature annealing caused the positive shift of the VFB and increased the Jg considerably to 1 × 10-3 A/cm2 at (VFB + 1) V after 600 °C PDA; these behaviors are possibly correlated with the degree of GeO volatilization. As far as the positive VFB shift after thermal annealing is concerned, the desorption process of GeO is believed to generate additional negative charges and leads to charge neutralization. W. P. Bai et al. have examined that an increase of PMA temperature made the value of VFB shift positively and they interpreted this phenomenon in terms of the out-diffusion of GeOx from Ge substrate [32].
Another result demonstrated further by N. Wu et al. was that the thicker the Si layer capping onto Ge substrate is, the smaller the amount of Ge out-diffusion is. Accordingly, a less positive VFB shift was found owing to the reduction of these negative charges [33].
Furthermore, more severe out-diffusion of GeO was seen upon increasing annealing temperature; this in turn caused the high-k/Ge interface degradation [23]. This tendency is obviously different from that observed in the Pt/HfOxNy/Si capacitors which depict the reduction in Jg upon increasing PDA temperature. We thus suggest that the GeOx
incorporation into the overlying HfOxNy bulk film may form the leakage path and contribute to gate leakage current, especially after annealing at 600 °C.
2.3.4 Influence of NH3 Plasma Passivation
Most studies have demonstrated that the gate leakage current in high-k/Ge systems decreases significantly after receiving surface thermal-annealing in a NH3 ambient, especially prior to the deposition of HfO2 dielectric films [34]. We observed similar effects after NH3
plasma, as presented in the inset of Fig. 2.6. The gate leakage was lower after higher-temperature PDA for the NH3–treated sample relative to that of the HF-last sample.
Moreover, plasma treatment reduced the hysteresis loop in the bidirectional C–V curves
measured at 1 MHz (Fig. 2.6); reduction of the interface state density to the order of 1011 cm–2.eV–1 was also achieved. We obtained a corresponding value of Neff of ca. 4.8 × 1012 cm–2 for HF-last sample and it decreased to ca. 2.5 × 1012 cm–2 after surface nitridation. It was believed that sub-stoichiometric oxide may create a high-density of charge-trapping sites at the dielectric-substrate and they could induce charge trapping and detrapping. The formation of Ge–N chemical bonds and the inhibited growth of GeOx (x ≦ 2) may be responsible for the resulting improved electrical performance. The interposed GeOxNy IL may behave as a diffusion barrier and suppress the volatilization of GeO out-diffusion from Ge substrate;
therefore, causing a less significant increase in Jg after NH3 plasma pretreatment.
On the other hand, in order to obtain a deeper insight into the origin of the hysteresis behavior, we separately extended the inversion and accumulation biases in the C−V sweeps and found that the increased inversion bias did lead to an increased hysteresis width, but the increased accumulation bias did not, as is evident in Fig. 2.7. This fact implies that hole trapping is the dominant mechanism; the scheme of a charge trapping model for a Pt/HfOxNy/GeOx/Ge gate stack has been proposed in other studies [35]. We conclude that the minority carriers (in this case, holes for n-type Ge) tunnel from the Ge substrate and become trapped at the inner-interface and/or inside the deficient GeOx interlayer. This process causes the C−V curve to shift negatively with the deviation of the VFB when the sweeping bias is started further from the negative side, i.e, more inversion charges are trapped. In contrast, the C−V curve exhibits its own value of VFB without being trapped when the voltage is swept from accumulation to inversion.
2.3.5 HfOxNy/Ge Interface Chemistry
In Fig. 2.8 and Fig. 2.9 we investigate the distribution of GeO species in entire structures through analyses of the Ge 2p3 and Ge 3p core levels—a broad band consisting of Ge
dioxides and suboxides and elemental Ge. We compared the spectra of these two Ge photoemissions because they allow sampling at significantly different depths. We employed mixed Gaussian–Lorentzian line shapes to reproduce these two Ge core levels from three components—Ge, GeO, and GeO2. From the high-surface-sensitivity Ge 2p3 spectrum (Fig.
2.8), a quite high intensity ratio of the GeO2 and GeO to the Ge substrate was found for both samples; this feature arose primarily from the surface contamination of GeOx (x ≦ 2). The average Ge concentration estimated within the top of high-k bulk layer is ca. 12(±1.4) at.% for HF-last sample; with the value can be reduced to ca. 4.8 at.% providing that the Ge substrate receives surface pretreatment of NH3 plasma. Subsequently annealing the NH3 sample at 600
°C for 30 s causes the Ge concentration increasing to the value of ca. 14 at.%. From the concentration levels, we found that NH3 pretreatment did assist to minimize Ge incorporation behavior during annealing with respect to the result obtained in HF-last sample that the Ge contamination was up to ca. 19.3(±2) at.% after annealing at 500 °C for 5 min. However, we suggest that the finite improvements in characteristics of NH3-treatment samples as compared to the literatures [14], [33] using another passivation technique—the Si interlayer on Ge—can be attributed to the incomplete passivation of the dangling bonds on the Ge surface; such a surface would not fully diminish the formation of GeOx. Lower dissociated temperature (ca.
500 °C) of Ge–N bonds [15] is a major cause to result in a still higher concentration of Ge observed after high-temperature processing.
In contrast, the Ge 3p spectrum (Fig. 2.9) clearly demonstrated that the intensity from the GeOx (x ≦ 2) was lower than that from the substrate after NH3 plasma nitridation, especially for inhibiting a large amount of Ge suboxides; these phenomena are the opposite of that observed for the non-nitrided high-k/Ge sample. Our explanation for this experimental finding is that the Ge 3p core level is capable of examining the amount of Ge oxide existing at the high-k/Ge interface since it possesses a higher sampling depth (ca. 80 Å) relative to that (ca. 34 Å) of the Ge 2p3 spectrum [36]. Accordingly, such a low oxide/substrate emission
ratio after performing the nitridation process is a direct result of NH3 plasma pretreatment diminishing the number of GeOx (x ≦ 2) defects at the interface; in other words, the reduced charge trapping centers is achieved. These results also imply that surface nitridation does indeed assist in enhancing the thermal stabilities of Pt/HfOxNy/Ge MOS structures.
2.4 Passivation of Ultrathin Si Capping Layer
2.4.1 Composition and Interfacial Physical Analyses
Figure 2.10 displays the SIMS depth profiles of the chemical species present in the HfOxNy films on the Ge substrates (a) in the absence and (b) presence of the Si capping layer.
We estimate that the overall thicknesses of the bulk HfOxNy and IL were ca. 90 Å and >100 Å before and after Si passivation, respectively; the probable chemical composition is also identified. An important feature of the HfOxNy layer was that the distribution profile of Ge was U-shaped; the subsequent PDA process enhanced the incorporation behavior, provided that Si2H6 passivation was not performed. The amount of incorporated Ge was reduced ca.
fourfold after capping with the ca. 8-Å-thick Si layer; further retardation of Ge chemical species into the overlying high-k dielectric was achieved after subsequent annealing under the same conditions. This finding provides strong evidence that employing a Si capping layer on a Ge substrate improves the thermal stability of HfOxNy/Ge gate stacks.
Figure 2.11(a) displays the Si 2p and Ge 2p core-level XPS spectra of the Ge substrate having the Si capping layer both before and after deposition of Pt/HfOxNy bi-layers. Prior to deposition, two well-resolved peaks—originating from the signals of the Si capping layer and the Ge substrate, respectively—appeared in corresponding core-level spectra; i.e., the native oxide was absent. After completing the entire MIS fabrication process, most of the Si atoms had transformed into Si dioxide and Hf-silicate, with some nitrogen-related bonds formed;
meanwhile, GeOx (x ≦ 2) emerged at the top surface and also in the bulk of the high-k layer.
Next, in Fig. 2.11(b), we compared the relative intensities of the Ge 2p levels of the four SIMS samples investigated in Figs. 2.10(a) and 2.10(b), respectively; because of the lack of sputtering yield information for Ge in the HfOxNy layer, we performed XPS analyses to evaluate the amounts of incorporated Ge. We estimate Ge concentrations of ca. 13% and ca.
4.3% for the non-annealed samples lacking and containing the Si capping layer, respectively, with these values increasing to ca. 19.6% and ca. 6.1%, respectively, after dielectric annealing.
The non-annealed high-k dielectric sample lacking the surface passivation layer exhibited a severe degree of Ge diffusion into the top HfOxNy film even when post-metallization annealing (PMA) was performed at only 400 °C. Because the Ge 2p core level displays higher surface sensitivity [36], the GeOx species detected in the Ge 2p spectrum arose possibly through one of two incorporation mechanisms: (a) out-diffusion of gaseous GeO species from the substrate and downward into the high-k layer through airborne transportation [21]; (b) GeO volatilization from the IL and top surface of the Ge substrate. From the viewpoint that the same GeO desorption rate would be expected for mechanism (a), it is reasonable to attribute the obvious increase in the GeOx intensity of the sample lacking the Si capping layer, with respect to that of the sample containing one, to contamination of GeO in the bulk of the high-k layer; this hypothesis is in agreement with the SIMS data.
2.4.2 Capacitance Characteristics and Charge Trapping Model
Figure 2.12 displays the bidirectional sweep (1 MHz) C–V curves of the Pt/HfOxNy/Ge gate stacks lacking and containing Si capping layers. We found that increasing the capping layer thickness suppressed the hysteresis width dramatically; its value reduced to ca. 20 mV upon increasing the thickness of the Si capping layer to ca. 13 Å. This tendency is quite consistent with the recent results reported by N. Wu et al [33].Moreover, the VFB returned to
the work-function difference of ca. 0.8 eV between the Pt gate and the n-Ge substrate or undoped Si layer, indicating that the addition of the Si capping layer also eliminated the fixed positive charges in the gate dielectric. Our explanation for these phenomena is that it is more likely that SiOx and its silicate will form, rather than GeOx, after deposition and annealing when the Si capping layer is present because Si–O bonds have larger Gibbs free energies and higher thermodynamical stabilities [37]. Therefore, the formation of GeO at the interface and its out-diffusion are suppressed significantly upon increasing the thickness of the Si layer.
Also, we believe that the exacerbated hysteresis width might be due to the high-density of charge-trapping sites at the high-k/GeOx interface and/or within the defective GeOx IL. We found that the increased inversion bias did lead to an increased hysteresis width, but the increased accumulation bias did not (not shown), implying that the hole trapping mechanism was dominant. Fig. 2.13 displays our proposed charge trapping model for the Pt/HfOxNy/GeOx/Ge gate stack; the energy bandgaps of each material and their corresponding
Also, we believe that the exacerbated hysteresis width might be due to the high-density of charge-trapping sites at the high-k/GeOx interface and/or within the defective GeOx IL. We found that the increased inversion bias did lead to an increased hysteresis width, but the increased accumulation bias did not (not shown), implying that the hole trapping mechanism was dominant. Fig. 2.13 displays our proposed charge trapping model for the Pt/HfOxNy/GeOx/Ge gate stack; the energy bandgaps of each material and their corresponding