Chapter 1 Introduction 1
3.6 Formation of the Depletion Layer
The depletion region is formed with a layer of unscreened dopant ions. It is clear that Schottky barriers will be set up at electrode and insulator interface. In some investigations, the device manufactured by organic or polymer insulator with reversible conductivity reveals its capacitance change with applying voltage. Because when a positive voltage is applied to the device, some negative carriers or ions will drift to near interface region, and by applying negative voltage will attract positive ones to near interface region.
Table3-1 Basic conduction mechanisms in insulators [28].
Conducting mechanism Voltage and temperature dependence
Schottky emission ~ 2exp( a V q B)
Tunneling (field) emission ~ 2exp( 1) J V
V
−
Space-charge-limited current J ~V 2
Ohmic conduction ~ exp( 1)
Chapter4
Results and Discussion
4.1 Properties and Analyses of the LaNiO3 Buffer Layer and SrZrO3
Resistive Films
According to the previous studies, the Al/0.3% V-doped SZO/LNO structure device has resistive switching performances [26]. But the switching voltage of the tri-layer structure device is over than 10V. It is proposed due to the low conductivity of the LNO bottom electrode. Large amount of applied voltage drops on the LNO bottom electrode causing to the high operation voltage. In order to reduce the operation voltage, several methods are used to enhance the conductivity of the LNO bottom electrode, such as the RTA process of the LNO, controlling the sputtering parameters for the LNO, different bottom electrode used to replace the LNO, Al/0.3% V-doped SZO/LNO/Pt structure (four-layer structure), and so on. Among these methods, four-layer structure device has different resistive switching properties and best performance. Therefore, this thesis is focus on the resistive switching properties of the four-layer structure.
4.1.1 X-Ray Diffraction and Scanning Electron Microscope Analyses of the LaNiO3 Buffer Layer
In accordance with the previous studies, the Al/0.3% V-doped SZO/LNO structure device had good resistive switching properties while the preferred orientations of the SZO film are (100) and (200) [26]. At this study, the LNO electrode in four-layer structure becomes a buffer layer to deposit particular orientations or the crystallization of the upper layer, and the LNO film has similar
physical properties to the upper layer, which will improve the crystallization of the upper resistive layer. Besides, dependent on the previous studies, the LNO film has many advantages as listed in follows.
(1) It has (100) and (200) preferred orientations rather than (110), so the better electrical properties of the SZO film on the LNO film can be anticipated.
(2) The LNO film could efficiently crystallize at about 250oC, where has the advantage of the low temperature CMOS process in the future.
(3) The cost of LNO is much cheaper than other noble metals.
If the SZO film was directly deposited on Pt or other metals, such as Al, Ti, Ta, Zr, Ni, and Nb, no (100)-preferred orientation film can be obtained, and no good resistive switching behaviors can be observed [26]. Instinctively, the characteristics of the LNO buffer layer could influence the properties of the memory devices. Fig.
4-1 shows the expected crystallization of the LNO buffer layer grown on the Pt bottom electrode. It has (100) and (200) preferred orientations rather than (110). It shows that the crystallization of LNO buffer layer in four-layer structure is almost identical to that in tri-layer structure. Then, the expected crystallization of the V-doped SZO film was grown on the LNO film. The device is expected to have good resistive switching properties.
Fig. 4-2 shows surface micro-morphology of the as-deposited LNO buffer layer. The sputter-deposited LNO buffer layer is flat and uniform.
A thermal treatment was added to improve the properties of the LNO buffer layer before the deposition of doped SZO film. The crystallization orientation or better conductivity of the LNO buffer layer can be controlled by changing RTA ambience or the heating profile of the RTA temperature, and high RTA temperature process is also utilized to test the thermal stability of LNO buffer layer. From the
previous studies, the conductivity of LNO buffer layer is increased with the increasing RTA temperature, which is summarized in Table 4-1.
XRD patterns of the LNO buffer layers with various RTA temperatures are shown in Fig. 4-3. LNO (110) orientation appears for the 700 and 800oC-annealed films in O2 ambience. Figs. 4-4 and 4-5 show that the surface morphology of the LNO films in 600 and 700oC RTA, respectively. The surface morphology of the LNO annealed at 600oC is flat, but that of the 700oC-annealed film exists some precipitates at the LNO surface. By the XRD analysis and Scherrer’s formula, we consider that the precipitates are the crystallization of the (110) LNO (Fig. 4-3).
According to the XRD and SEM analyses, in order to avoid the LNO (110) orientation and precipitates to influence electrical properties of the device, RTA treatment temperature was set at 600oC in O2 ambience in this thesis. Fig. 4-6 shows the surface morphology of the as-deposited 0.3% V-doped SZO film. The surface morphology of the SZO film is uniform and without any precipitate.
4.1.2 Transmission Electron Microscope
Because the LNO buffer layer has similar physical properties with the SZO film, the interface between LNO and SZO films can not be identified by SEM.
HRTEM analysis shown in Fig. 4-7 is helpful to recognize the interface between the LNO and SZO films and understand the thickness of respective LNO and SZO films. The LNO buffer layer was sputtered at 250oC in a gas pressure of 40 mTorr with an Ar:O2 mass ratio of 24:16, and in a period of 85 min. The thickness of LNO buffer layer is about 100nm. The 0.3% V-doped SZO was sputtered at 500oC in a gas pressure of 40 mtorr with an Ar:O2 mass ratio of 24:16, and in a period of 90 min. The thickness of the 0.3% V-doped SZO film is about 45nm. Fig. 4-7 also shows the interface clearly between the LNO and SZO films. It proves no
inter-diffusion between LNO and SZO films.
4.1.3 Scanning Probe Microscope
Scanning Probe Microscopy has enabled researchers to image surfaces at the nanometer scale. The device with tri-layer structure is manufactured to be a contrast experiment. Figs. 4-8 to 4-11 show the SPM analyses of LNO and SZO films sputtered on different substrates. Table 4-2 shows the summarization of roughness of the SZO and LNO films deposited on different substrates. The trend is that the roughness becomes smaller after deposited the SZO film. It is proposed that the substrate was kept at high temperature and long time when the SZO film was deposited. Then, the sputtered atoms get more thermal energy to form an uniform film. In addition, it shows that the roughness of the SZO and LNO in four-layer structure is higher than that in tri-layer structure.
4.2 Electrical and Physical Properties of the Al/V-doped SrZrO3/LaNiO3/Pt Device
4.2.1 Forming Process
At beginning, the sample is at an Original-state lower than L-state. As shown in Fig. 4-12, when the voltage sweeps to a voltage about 5 or -5V, the leakage current suddenly increases and switches to the H-state. Then, the nonpolar resistance switching properties can exist without any delay time between every voltage sweep cycles. The first resistive switching process is called the forming process.
4.2.2 SrZrO3 Sputtering Parameters
The influences of sputtering power on the SZO film have components, deposition rate, crystallization, etc. Fig. 4-13 shows forming voltage uniformity versus deposition time and sputtering power. According to the results, it shows that sputtering power influences the variation of the forming voltage. The forming voltage of SZO film sputtered at 100W is more uniform as compared with that sputtered at 150W. The reason may be the SZO film sputtered at 100W is more uniform result in good uniformity of the forming voltage.
4.2.3 Electrical Properties of the SrZrO3 Resistive Films
Fig. 4-14 depicts the I-V curve of the Al/0.3% V-doped SZO/LNO/Pt device.
While the negative voltage is applied on the top electrode from 0 to -5V, the current rapidly increases at -3.5V, and then the device is switched from L-state to H-state.
During the measurement, the current is restricted to 1mA to prevent the degradation of the device. While the device is switched from L-state to H-state and limited at 1mA, it does not influence the H-state current of the device. The device altered from L-state to H-state is called as on process. Subsequently, the bias voltage sweeps from 0V to -2V and the device is switched from H-state back to L-state at -1.8V. The device altered from H-state to L-state is called as off process. When the positive voltage is applied on the top electrode from 0 to 5V, the device is altered from L-state to H-state at 3V. Then, the bias voltage sweeps from 0V to 2V and the device is changed from H-state to L-state at 1.8V. As shown in Fig. 4-15, the resistance ratio between two current states is over 106 measured at -1V. The resistive switching phenomenon switched by either positive or negative bias voltage can repeat over 10 times. The resistive switching properties of the device altered by either positive or negative bias voltage are called nonpolar resistive switching
characteristic.
Fig. 4-16 shows that I-V curve of the Al/0.3 % V:SZO/LNO device. The tri-layer device is switched from L-state to H-state at -13V, and from H-state to L-state at 10V. The resistance ratio of the Al/SZO/LNO device is 104 at measured -1V as shown in Fig. 4-17. The on and off processes are applied negative and positive bias voltage, respectively, which called bipolar resistive switching characteristic.
Compared Fig. 4-14 with Fig. 4-16, the differences between two devices are H-state current and switching voltage. Because the H-state current of the four-layer device is higher than that of tri-layer device over 1000 times, the resistance ratio between two states of the four-layer device is higher than 106. The switching voltage of the four-layer device is lower than that of the tri-layer device. The results are discussed in the next section.
4.2.4 Schematic Conducting Loop
Because the conductivity of the LNO buffer layer is lower than that of metal electrode, Pt electrode has replaced LNO electrode to be the bottom electrode. This is proved at this section. However, it results in different resistive switching characteristic which is discussed in the previous section.
As shown in Fig. 4-18 (a), the serial resistance of the carrier passing through the path1 is,
Rpath1=RW/Al+RAl+RAl/SZO+RSZO+RSZO/LNO+RLNO+RLNO/Pt+RPt+RPt/LNO+RLNO+
RLNO/Al+RAl+RAl/W………...….(1)
where the RW/Al and RAl/W are the contact resistance of probe and top electrode.
Because the fabricating processes of the SZO and LNO films in the four-layer structure are identical to those of the tri-layer structure, it is considered that the
conductivity of the carrier passed through path2 in four-layer structure is the same in tri-layer structure. As shown in Fig. 4-18 (a) and (b), the serial resistance of the carrier passed through path2 is,
Rpath2=RW/Al+RAl+RAl/SZO+RSZO+RSZO/LNO+RLNO+RLNO/Al+RAl+RAl/W………(2) The Rpath1 estimated by H-state current in four-layer structure shown in Fig.
4-14 is about 20Ω. The Rpath2 estimated by H-state current in tri-layer structure shown in Fig. 4-16 is about 15kΩ. Compared Eqns. (1) with (2), it is proposed that the RLNO is about 15kΩ, and the RPt is lower than 20Ω. Therefore, the conductivity of the LNO electrode worse than that of Pt electrode is proved and the LNO bottom electrode in four-layer becomes a buffer layer to deposit particular orientations of the upper layer.
The resistance ratio of the tri-layer device is three orders of magnitude lower than that of the four-layer device owing to the difference between the H-state current of two devices. According to Eqns. (1) and (2), the crabwise resistance of the LNO bottom electrode of the tri-layer device mainly influences on the H-state current, which is similar to the compliance effect although the resistance of the V:SZO film and parasitic resistance of two devices maybe have some differences under distinct on processes.
Because the conductivity of the LNO film is not very high, when the device is applied positive voltage on the top electrode, the speed of electrons passing through the SZO film is too slow to switch the device from L-state to H-state. Therefore, the switching characteristic is difference between two device structures.
4.2.5 Conducting Mechanisms
Fig. 4-19 depicts the plots of Ln(|I|) versus Ln(|V|) of both H-state and L-state currents for the Al/0.3% V-doped SZO/LNO/Pt device. The slopes of H-state curves
close to unity, indicating that the H-state current is dominated by Ohmic conduction, which is related to thermally excited electrons hopping from one isolated state to the next one [27]. On the other hand, the L-state curves are not straight lines, implying that the L-state current is dominated by other conduction mechanisms. Fig.
4-20 shows the plots of Ln(|I/V|) as a function of of H-state and L-state currents for this device. The linear fittings of the device indicate that the L-state current follows the F-P emission, which is corresponding to field-enhanced thermal excitation of trapped electrons into the conduction band [27].
|V|1/ 2
4.2.6 Possible Resistive Switching Mechanisms
In the on process, the biased electrons found one or few conduction paths consisting of possible point defects, such as oxygen vacancies and ionic and electronic defects associated with Zr replaced by V. Simultaneously, the electrons hopped passing through the V-doped SZO film in these paths and causing the current to dramatically increase. Consequently, the resistive switching mechanism of the on process is considered to form the formation of current paths [17] as shown in Fig. 4-21 (a). In the off process, while the defects in the V-doped SZO film trap electrons to some degree, and hence, the paths could be considered ruptured as shown in Fig. 4-21 (b).
4.3 Test of Memory Effects
Based on the dc sweep induce bistable conductivity switching character as mentioned, the device is suitable for nonvolatile random memory product. To satisfy criteria of memory product, there are several fundamental conditions that must be tested,
such as switching voltage, leakage current order, resistance ratio, switching speed, retention, endurance, stress test, and so on. The device will be test every criterion and improve its characteristics shown in follows.
4.3.1 Retention
For a NVM, the data storage time is also called retention time as an important index. It means how long time the current state can be kept in an acceptable range, once the memory cell is written in one state. As shown in Fig. 4-22, retention test of the Al/0.3% V-doped SZO/LNO/Pt device measured at RT after 107s is performed.
It is no doubt that there is no current variation after 107s, and the resistance ratio is over 106. It shows good retention performance at RT. Besides, thermal test is executed in order to accelerate degeneration speed of memory device. First, the devices are switched to H-state and L-state, respectively. After 1000s the devices are kept at 85oC and also measured at 85oC. Fig. 4-23 shows that the retention test of the devices kept at 85oC. H-state and L-state currents are stable at least 2× 106s and the resistance ratio between two state is about 106. The retention is not affected while measured at 85oC. Continuously, measured temperature arises from 85 to 120oC. H-state and L-state currents are stable at 120oC and the resistance ratio maintain at 106. Measured temperature continuously arises from 120 to 150oC. Two current states are still stable at 150oC and the resistance ratio hold at 106. According to previous statement, our device shows good retention performance and thermal reliability.
4.3.2 Pulse Switching
The dynamic characteristic of the device is used in memory array critically.
Fig. 4-24 shows the response of the device after applying a -6V, 10ns pulse on the
top electrode. The device is in L-state initially. When the device is applied a negative voltage pulse with -6V magnitude and 10ns pulse width on the device changed the L-state to H-state. On the other hand, Fig. 4-25 shows the switching of the H-state to the L-state after applying a -4V, 10ns pulse.
4.3.3 Non-Destructive Readout
Voltage stress test is performed to check reliability for reading data frequently and for affection of unexpected voltage noise. Voltage stress is measured with two applied voltage modes, sweep and pulse voltages. Fig. 4-26 shows that the two states of our device stressed at -0.5V for 3hr are stable and kept the resistance ratio over 106. Voltage stress test of the device switched by sweep or pulse voltage is stable. It shows the device can bear 1012 of -0.5V, 10ns pulse voltage with no change. The device has great non-destructive readout performance. The device is also measured voltage stress of the device at 85oC in order to accelerate degeneration speed of memory device. As shown in Fig. 4-27, the device is still stable at 85oC and keeps the resistance ratio over 106. At 85oC, the device also has great non-destructive readout performance.
4.3.4 Thermal Reliability
As shown in Fig. 4-28, the I-V curve of Al/0.3% V-doped SZO/LNO/Pt device is measured at varies temperatures. The resistive switching properties of the device measured at high temperature are the same as that at RT. The thermal reliability of the device is great.
4.3.5 Endurance
Several Al/0.3% V-doped SZO/LNO/Pt structure devices are measured to
calculate the uniformity of the device. The variation switching voltage of the device is shown in Fig. 4-29. The variation of on voltage is probably within 1V around -4V. The variation of off voltage is almost unchange. Fig. 4-30 shows that the variation of two current states of the Al/0.3% V-doped SZO/LNO/Pt device. The H-state current is light change. The variation of L-state current is about two orders and L-state current increase proportion to cycling number. It shows that the off process is more unstable, and the device degrades when cycling number increases.
But the resistance ratio of the device is kept at 10
±
5 and it is enough to be distinguished in memory application.
When the sweeping times are over 10, the top electrode of the Al/0.3%
V-doped SZO/LNO/Pt device appears sear status like the condition shown in Figs.
4-31 and 4-32. The burned top electrode would influence the contact of top electrode and SZO film. It may be the critical issue for endurance characteristic of the device.
Fig. 4-33 shows the I-V curves of the device after applying 1, 10, 20, 30, 40, and 50th voltage sweeping cycles measured at 150oC. While the number of voltage sweeping cycles increases, L-state current increase after 10th cycle, leading to decrease in resistance ratio. After 10th cycle, the resistance ratio of the device kept at least 102 as shown in Fig. 4-34, and the switching voltage compared with the device measured at RT is slightly changed as shown in Fig. 4-35.
4.4 Different Electrode Material Affecting Resistive Switching Properties of the Device
Table 4-3 shows the resistive switching properties of the SZO-, TiO2-, and PCMO-based memory devices reported by several well-known research groups. Based on
the experimental results shown in Fig. 4-14, the SZO-based memory device is nonpolar switching, which is different from the bipolar switching results reported in the previous
the experimental results shown in Fig. 4-14, the SZO-based memory device is nonpolar switching, which is different from the bipolar switching results reported in the previous