Chapter 4 Results and Discussion 41
4.3 Test of Memory Effects
4.3.2 Pulse Switching
The dynamic characteristic of the device is used in memory array critically.
Fig. 4-24 shows the response of the device after applying a -6V, 10ns pulse on the
top electrode. The device is in L-state initially. When the device is applied a negative voltage pulse with -6V magnitude and 10ns pulse width on the device changed the L-state to H-state. On the other hand, Fig. 4-25 shows the switching of the H-state to the L-state after applying a -4V, 10ns pulse.
4.3.3 Non-Destructive Readout
Voltage stress test is performed to check reliability for reading data frequently and for affection of unexpected voltage noise. Voltage stress is measured with two applied voltage modes, sweep and pulse voltages. Fig. 4-26 shows that the two states of our device stressed at -0.5V for 3hr are stable and kept the resistance ratio over 106. Voltage stress test of the device switched by sweep or pulse voltage is stable. It shows the device can bear 1012 of -0.5V, 10ns pulse voltage with no change. The device has great non-destructive readout performance. The device is also measured voltage stress of the device at 85oC in order to accelerate degeneration speed of memory device. As shown in Fig. 4-27, the device is still stable at 85oC and keeps the resistance ratio over 106. At 85oC, the device also has great non-destructive readout performance.
4.3.4 Thermal Reliability
As shown in Fig. 4-28, the I-V curve of Al/0.3% V-doped SZO/LNO/Pt device is measured at varies temperatures. The resistive switching properties of the device measured at high temperature are the same as that at RT. The thermal reliability of the device is great.
4.3.5 Endurance
Several Al/0.3% V-doped SZO/LNO/Pt structure devices are measured to
calculate the uniformity of the device. The variation switching voltage of the device is shown in Fig. 4-29. The variation of on voltage is probably within 1V around -4V. The variation of off voltage is almost unchange. Fig. 4-30 shows that the variation of two current states of the Al/0.3% V-doped SZO/LNO/Pt device. The H-state current is light change. The variation of L-state current is about two orders and L-state current increase proportion to cycling number. It shows that the off process is more unstable, and the device degrades when cycling number increases.
But the resistance ratio of the device is kept at 10
±
5 and it is enough to be distinguished in memory application.
When the sweeping times are over 10, the top electrode of the Al/0.3%
V-doped SZO/LNO/Pt device appears sear status like the condition shown in Figs.
4-31 and 4-32. The burned top electrode would influence the contact of top electrode and SZO film. It may be the critical issue for endurance characteristic of the device.
Fig. 4-33 shows the I-V curves of the device after applying 1, 10, 20, 30, 40, and 50th voltage sweeping cycles measured at 150oC. While the number of voltage sweeping cycles increases, L-state current increase after 10th cycle, leading to decrease in resistance ratio. After 10th cycle, the resistance ratio of the device kept at least 102 as shown in Fig. 4-34, and the switching voltage compared with the device measured at RT is slightly changed as shown in Fig. 4-35.
4.4 Different Electrode Material Affecting Resistive Switching Properties of the Device
Table 4-3 shows the resistive switching properties of the SZO-, TiO2-, and PCMO-based memory devices reported by several well-known research groups. Based on
the experimental results shown in Fig. 4-14, the SZO-based memory device is nonpolar switching, which is different from the bipolar switching results reported in the previous studies [15], [41]. Besides, in their studies the polarities of on and off voltages are fully opposite; Beck et al. proposed that their device with Au/Cr:SZO/SrRuO3 (SRO) structure could be turned on/off by applying a negative/positive voltage [15]; nevertheless, Park et al. reported that Pt/Cr-doped SZO/SRO device could be on/off by applying a positive/negative voltage [41]. The different switching behaviors between these two studies might be due to their different top electrodes used. Therefore, above results indicate that the electrode materials of the device determine the bipolar or nonpolar switching, and the polarity of bipolar switching. In Fig. 4-16, for instance, when the device is on, electrons are injected from Al top electrode into V-doped SZO film. While in off process, electrons are flowed from the LNO bottom electrode into V-doped SZO film slowly and trapped by defects uniformly [42]. However, the device cannot be on by applying a positive voltage because the electrons injected from LNO bottom electrode are trapped by the defects existed in the V-doped SZO film and cannot flow to the Al top electrode. Therefore, the distinct resistive switching properties of the devices shown in Figs. 4-14 and 4-16 are due to different bottom electrodes used. Similar results are also observed in TiO2- and PCMO-based memory devices. In TiO2-based memory devices, Fujimoto et al. proposed the bipolar switching of the Pt/TiO2/TiN device [43]; however, Choi et al. reported the nonpolar switching of the Pt/TiO2/Ru device [44]. In PCMO-based memory devices, Sawa et al. reported the bipolar switching of the Ti/PCMO/SRO device [45], while Fujimoto et al. showed the nonpolar switching of the Pt/PCMO/Pt device [46]. Consequently, we consider that the nonpolar switching is an intrinsic property of SZO-, TiO2-, and PCMO-based memory devices; however, the electrode materials employed in the device would dominate their bipolar or nonpolar switching behavior, and the polarity of bipolar switching. Therefore, the appropriate
electrode materials chosen are indeed very important for obtaining the RRAM devices with excellent properties. However, other factors such as the conductivity and work function of electrodes, contact resistance between two films, microstructure of resistive layer, and work function difference and property of each interface are still needed for further detailed studies for developing an excellent RRAM device.
4.5 One Diode and One Resistor Device
Above results indicate that the Al/V-doped SZO/LNO/Pt memory device with good switching properties is a possible candidate for next-generation NVM applications. But the issue of RRAM is read error. One diode and one resistor (1D1R) device structure could avoid the read error issue as shown in Figs. 4-36 and 4-37. The leakage current paths are rupture by diode. The 1D1R device has many advantages as listed in follows.
(1) Diode is compatible and easily manufactured in CMOS process.
(2) Diode is much cheaper than other rectifying elements.
The I-V curve of 1D1R device is shown in Fig. 4-38. While the negative voltage is applied on the top electrode from 0 to -5V, the current rapidly decreases at -5V and the device is switched from H-state to L-state. Subsequently, the bias voltage sweeps from 0 to -6V and the device is switched from H-state back to L-state at -5.5V. While the device is switched from L-state to H-state and the current is restricted at 10mA. The positive bias mode is rectified by diode. Fig. 4-39 shows that the resistance ratio of two states current is about 104 at -1V. Although the 1D1R device has resistive switching properties, the yield of the device is low. It is proposed that on-off voltage to be close results in the device is unstable [47]. Hence, the 1D1R device need more research to find optimal parameters.
Table 4-1 Conductivities of the LNO films with different sputtering temperature and annealing ambience.
Sputter temp.
RTA 200oC 250oC 300oC
W/O RTA 103 116 188
600oC O2 1min 47 77 133
700oC O2 1min 25 43 87
Sheet resistance (Ω/□)
Table 4-2 Roughness of the SZO and LNO films deposited on different substrates.
Structure Meam roughness (nm) Rms (nm)
LNO/SiO2 0.923 1.227
SZO/LNO/SiO2 0.812 1.037
LNO/Pt 2.218 2.842
SZO/LNO/Pt 1.458 2.035
Table 4-3 Resistive switching properties of the SZO-, TiO2-, and PCMO-based devices [15], [41]-[46].
Fig. 4-1 XRD patterns of the LNO buffer layer with different substrates.
Fig. 4-2 SEM surface micro-morphology of the as-deposited LNO buffer layer.
Fig.4-3 XRD patterns of the LNO buffer layer with different RTA temperatures.
Figs. 4-4 SEM surface morphology of the LNO after 600oC RTA treatment.
Figs. 4-5 SEM surface morphology of the LNO after 700oC RTA treatment.
Fig. 4-6 SEM surface micro-morphology of the 0.3% V-doped SZO film.
Fig. 4-7 FETEM cross section image of the 0.3% V-doped SZO film.
Fig. 4-8 SPM roughness analysis of the LNO deposited on the SiO2 substrate.
Fig. 4-9 SPM roughness analysis of the SZO deposited on the LNO/SiO2 substrate.
Fig. 4-10 SPM roughness analysis of the LNO deposited on the Pt/Ti electrode.
Fig. 4-11 SPM roughness analysis of the SZO deposited on the LNO/Pt/Ti substrate.
Fig. 4-12 I-V curve of the Al/0.3% V-doped SZO/LNO/Pt device with forming voltage.
Fig. 4-13 Forming voltage uniformity vs. deposition time and sputtering power.
Fig. 4-14 I-V curve of the Al/0.3% V-doped SZO/LNO/Pt device.
Fig. 4-15 Plots of resistance ratio versus bias voltage of theAl/0.3% V-doped SZO/LNO/Pt device.
Fig. 4-16 I-V curve of the Al/0.3% V-doped SZO/LNO structure device.
Fig. 4-17 Plots of resistance ratio versus bias voltage of the Al/0.3% V-doped SZO/LNO device.
Fig. 4-18 Schematic conducting path of (a) four-layer structure, (b) tri-layer structure.
Fig. 4-19 Current fitting curves of Ohmic conduction.
Fig. 4-20 Current fitting curves of Frenkle-Poole conduction.
.
Fig. 4-21 Hypothetical diagram of the current paths: (a) on process, and (b) off process.
Fig. 4-22 Retention of the Al/0.3% V-doped SZO/LNO/Pt device.
Fig. 4-23 Retention of the Al/0.3% V-doped SZO/LNO/Pt device kept at high temperature.
Fig. 4-24 I-V curve of the Al/0.3% V-doped SZO/LNO/Pt device turned on by -6V, 10ns pulse.
Fig. 4-25 I-V curve of the Al/0.3% V-doped SZO/LNO/Pt device turned on by -4V, 10ns pulse.
Fig. 4-26 Voltage stress of the Al/0.3% V-doped SZO/LNO/Pt device.
Fig. 4-27 Voltage stress of the Al/0.3% V-doped SZO/LNO/Pt device measured at 85oC.
Fig. 4-28 I-V Curves of the Al/0.3% V-doped SZO/LNO/Pt device measured at different temperatures.
Fig. 4-29 Variation of switching voltage of the Al/0.3% V-doped SZO/LNO/Pt device.
Fig. 4-30 Variation of two current state of the Al/0.3% V-doped SZO/LNO/Pt device.
Fig. 4-31 SEM image of cross section of the Al top electrode.
Fig. 4-32 SEM image of top view of the Al top electrode.
Fig. 4-33 I-V curves of the Al/0.3% V-doped SZO/LNO/Pt device after applying 1, 10, 20, 30, 40, and 50th voltage sweeping cycles measured at 150oC.
Fig. 4-34 Variation of two state currents of the Al/0.3% V-doped SZO/LNO/Pt device.
Fig. 4-35 Variation of switching voltage of the Al/0.3% V-doped SZO/LNO/Pt device.
GND Bias
1R
1D
Fig. 4-36 Cross section schematic diagram of the 1D1R device.
Fig. 4-37 Read error issue of the device.
Fig. 4-38 I-V curves of the 1D1R device.
Fig. 4-39 H-state and L-state currents of the 1D1R device.
Chapter 5
Conclusions
The experimental results reported in this thesis indicate that the resistive switching properties significantly are affected by the electrode materials. The Al/V:SZO/LNO/Pt device shows the nonpolar switching property, while the Al/V:SZO/LNO device depicts the bipolar switching behavior. The resistance ratios of two states are 107 and 104 for the Al/V:SZO/LNO/Pt and Al/V:SZO/LNO devices, respectively, which is due to the difference between the H-state current of two devices. The four-layer device has lower switching voltages and higher resistance ratio, while the tri-layer device shows higher switching voltages and lower resistance ratio. Such a different behavior is attributed to a high crabwise resistance of LNO bottom electrode in comparison with a low resistance of Pt bottom electrode. The conduction mechanisms of H-state and L-state currents are Ohmic and F-P conductions, respectively, which is considered the formation and disruption of local conducting paths in the resistive layer. The switching speed of the Al/V:SZO/LNO/Pt device is 10ns, which is the fastest speed in comparison with those of the previous reports. The non-destructive readout property of the Al/V:SZO/LNO/Pt device is demonstrated, and the retention time of the device longer than 106s is also performed in this thesis. The results are summarized in Table 5-1 and compared with criteria of RRAM. Read error is the issue of RRAM. 1D1R device suitable for avoiding read error issue are also investigated in this thesis.
But a more complete study of the 1D1R device is needed. Therefore, the Al/V:SZO/LNO/Pt memory device having good switching properties is a possible candidate for next-generation NVM applications.
Table 5-1 Work results comparison with the specification of RRAM.
Specification Work results
Operation voltage < 10 V < 5V
Current density at -1V 105~107 A/cm2 Estimated of 108 A/cm2 for 0.1μm technology node
Resistance ratio > 100 107
Operation speed < 1 us 10ns
Retention time > 10-year > 4-month (107s)
Endurance > 106 102
Readout disturbance > 1012 Voltage stress > 104s
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