Future work

In this experiment, the HfO2 film was deposited by MOCVD system. In the future, the ALCVD ( Atomic Layer CVD ) system will become another important deposition technology. Further experiment and analysis are required to clarify if the same treatment condition is also suitable for ALCVD film. On the other hand, the MOSFET will be fabricated by the same treatment condition to verify the effect on device characteristics, such as mobility, subthreshold swing, and transonductance.

The interfacial layer between high-k/ Si would be increased by increasing post-deposition-annealing temperature. In order to deeply realize the effect of the plasma treatment, we could use some methods to analysis the interfacial layer by

SIMS ( Secondary Ion Mass Spectrometer ) and TEM ( Transmission Electron Microscope ) analysis to verify the phenomenon observed from CV and JV curve.

Furthermore, we might have to understand the mechanism of leakage current of thin film and thick film individually. Finally, the mechanism of the generation of the defects in the high-k bulk or interface still needs to be solved.

References

[1] Wang Bin, J. S. Suehle, E. M. Vogel and J. B. Bernstein, ”Time-dependent breakdown of ultra-thin SiO2 gate dielectrics under pulsed biased stress,”

IEEE Electron Device Lett., 22, pp. 224-226, 2001.

[2] J. H. Stathis, A. Vayshenker, P. R. Varekamp, E. Y. Wu, C. Montrose, J.

McKenna, D. J. DiMaria, L. -K. Han, E. Cartier, R. A. Wachnik and B. P.

Linder, “Breakdown measurements of ultra-thin SiO2 at low voltage,” in IEDM Tech. Dig., 2000, pp. 94-95.

[3] M. Koyama, K. Suguro, M. Yoshiki, Y. Kamimuta, M. Koike, M. Ohse, C.

Hongo and A. Nishiyama, “Thermally stable ultra-thin nitrogen incorporated ZrO2 gate dielectric prepared by low temperature oxidation of ZrN,” in IEDM Tech. Dig., 2001, pp. 20.3.1-20.3.4.

[4] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A.

Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A.

Gribelyuk, H. Okorn-Schmidt, C. D Emic, P. Kozlowski, K. Chan, N.

Bojarczuk, L. -A. Ragnarsson and Rons, “Ultrathin high-K gate stacks for advanced CMOS devices,” in IEDM Tech. Dig., 2001, pp. 20.1.1-20.1.4.

[5] International Technology Roadmap for Semiconductor, 2001, pp. 38.75

[6] S. Song, J. H. Yi, W. S. Kim, J. S. Lee, K. Fujihara, H. K. Kang, J. T. Moon and M. Y. Lee, “CMOS device scaling beyond 100 nm,” in IEDM Tech. Dig.,

2000, pp. 235-238.

[7] International Technology Roadmap for Semiconductor, 1999.

[8] K. W. Kwon, C. S. Kang, S. O. Park, H. K. Kang, and S. T. Ahn, “Thermally robust Ta2O5 capacitor for 256-Mbit DRAM”, IEEE Trans. Electron Devices, 43(6), p.919, 1996.

[9] Max Schulz, “The end of the road for silicon,” Nature, Vol. 399, pp. 729, 1999.

[10] S. –H. Lo, D. A. Buchanan, Y. Taur, W. Wang, “Quantum-Mechnical Modeling of Electron Tunneling Current from the Inversion Layer of

Ultra-Thin Oxide nMOSFET’s,” IEEE Electron Device Lett., Vol. 18, pp.209, 199

[11] G. D. Wilk, R. M. Wallace, et. al., “High-k gate dielectrics: current status and materials properties consideration” J. Appl. Phys., Vol. 89, No. 10, pp.

5243,2001 .

[12] J. Robertson, J. Vac. Sci. Technol. B 18, pp1785, 2000.

[13] Robert M. Wallace, IRPS Tutorial, IRPS, 2004.

[14] K. J. Hubbard and D. G. Schlom, J. Mater. Res. 11, 2757 (1996).

Voorde,Wayne M. Greene, Johannes M. C. Stork, Zhiping Yu, Peter M.

Zeitzoff, Jason C.S. Woo, “The Impact of High-k Gate Dielectrics and Metal Gate Electrodes on Sub-100 nm MOSFET’s”, IEEE Transactions on Electron Devices, Vol. 46, No. 7, July 1999.

[16] C. T. Liu, “Circuit Requirement and Integration Challenges of Thin Gate Dielectrics for Ultra Small MOSFET’s” in IEDM Tech. Dig., p.747, 1998.

[17] S. P. Muraka and C. C. Chang, Appl. Phys. Lett. 37,639 (1980).

[18] M. Balog, M. Schieber,M. Michman, and S. Patai, “Chemical vapor deposition and characterization of HfO2 films from organo-hafnium compounds,” Thin Solid Films, vol. 41, pp. 247–259, 1977.

[19] J. Robertson, “Band offsets of wide-band-gap oxides and implications for future electronic devices,” J. Vac. Sci. Technol. B, vol. 18, pp. 1785–1791, 2000.

[20] K. J. Hubbard and D. G. Schlom, “Thermodynamic stability of binary oxides in contact with silicon,” J. Mat. Res., vol. 11, pp. 2757–2776, 1996.

[21] M. Balog et al. Thin Solid Films, ~01.41, 247 (1977).

[22] K. Onishi, C. S. Kang, R. Choi, H.-J. Cho, S. Gopalan, R. Nieh, S. Krishnan, and J. C. Lee, “Effects of high-temperature forming gas anneal on HfO2 MOSFET performance,” in VLSI Tech. Dig., 2002, pp. 22–23.

[23] K. Rim, E. P. Gusev, C. D’Emic, T. Kanarsky, H. Chen, J. Chu, J. Ott, K. Chan, D. Boyd, V. Mazzeo, B. H. Lee, A. Mocuta, J. Welser, S. L. Cohen, M. Ieong, and H.-S. Wong, “Mobility enhancement in strained Si NMOSFETs with HfO2 gate dielectrics,” in VLSI Tech. Dig., 2002, pp. 12–13.

[24] H.-H Tseng,Y. Jeon, P. Abramowitz, T.-Y. Luo, “Ultra-Thin Decoupled Plasma Nitridation (DPN) Oxynitride Gate Dielectric for 80-nm Advanced Technology “, IEEE Electron Device Letters, VOL. 23, NO. 12, December, 2002.

[25] Seiji Inumiya, Katauyuki Sekine, Shoko Niwa, Akio Kaneko, Motoyuki Sato,”

Fabrication of HFSION Gate Dielectrics by Plasma Oxidation and Nitridation, Optimized for 65 nm node Low Power CMOS Applications ”, VLSI, 2003.

[26] Satoshi Kamiyama, Tomonori,” Improvement in the uniformity and the thermal stability of Hf-silicate gate dielectric by plasma-nitridation”, IWGI, 2003.

[27] Katsuyuki Sekine, Seiji Inumiya, Motoyuki Sato, Yoshitaka Tsunashima,

“Nitrogen Profile Control by Plasma Nitridation Technique for Poly-Si Gate HfSiON CMOSFET with Excellent interface property and Ultra-low Leakage Current”, IEDM 03-103

[28] R. J. Carter, E. Cartier, M. Caymax, S. De Gendt, R. Degraeve, G.

Groeseneken, M.Heyns, T. Kauerauf, A. Kerber, S. Kubicek, G. Lujan, L.

Pantisano, W. Tsai, E. Young, “Electrical Characterisation of High-K Materials

[29] Benjamin Chih-ming Lai, Nan-hui Kung, and Joseph Ya-min Lee, “A study on the capacitance--voltage characteristics of metal-Ta2O5-silicon capacitors for very large scale integration metal-oxide-semiconductor gate oxide applications”, J. Appl. Phys. 85, 4087 1999.

[30] Wai Shing Lau, Merinnage Tamara Chandima Perera, Premila Babu, Aik Keong Ow, Taejoon Han, Nathan P. Sandler, Chih Hang Tung, Tan Tsu Sheng and Paul K. Chu, “The Superiority of N2O Plasma Annealing over O2 Plasma Annealing for Amorphous Tantalum Pentoxide (Ta2O5) Films”, Jpn. J. Appl.

Phys. Vol.37 pp.L435-L437 1998.

[31] Y. Chuo, D. Y. Shu, L. S. Lee, W. Y. Hsieh, M. –J. Tsai, A. Wang, S. B. Hung, P. J. Tzeng, Y. W. Chou, “In-Line Inspection on Thickness of Sputtered HfO2 and Hf Metal Ultra-Thin Films by Spectroscopic Ellipsometry”, 2004 IEEE.

[32] Takeshi Yamaguchi, Hideki Satake, Noburu Fukushima, “Band Diagram and Carrier Conduction Mechanisms in ZrO2 MIS Structures”, IEEE Transactions on Electron Devices, Vol. 51, No. 5 May 2004.

[33] International SEMATECH Confidential and Supplier Sensitive, “Status of High-k Gate Dielectric Development and the Demonstration of High-k Devices with Equivalent Oxide Thickness (EOT) of <= 1.0 nm”, 2002.

[34] Wai Shing Lau, Thiam Siew Tan, Nathan P. Sandler, Barry S. Page,

“Characterization of Defect States Responsible for Leakage Current in

Tantalum Pentoxide Films for Very-High-Density Dynamic Random Access Memory (DRAM) Applications”, Jpn. J. Appl. Phys., Vol.34, pp.757-761, 1995.

Table

Table 1-1 High-performance Logic Technology Requirements Roadmap.

( ITRS：2006 updae )

Table 1-2 Characteristics of various high-k materials.

Figure-chapter 1

Fig. 1-1 Conduction mechanism in oxide for the MOS structure.

Fig1-2 Roadmap of the gate dielectric

.

Fig. 1-3 With the marching of technology nodes, gate dielectric has to be shrunk and five silicon atoms thick of gate dielectric is predicted for 2012.[9]

Fig. 1-4 Measured and simulated I^g-V^g characteristics under inversion condition for nMOSFETs. The dotted line indicates the 1A/cm² limit for the leakage current. [10]

Fig. 1-5 Jg, limit versus Jg, simulated for High-Performance Logic ( ITRS: 2005 update )

Fig. 1-6 Jg,limit versus Jg,simulated for Low Operating Power ( ITRS: 2005 update )

Fig. 1-7 Jg,limit versus Jg,simulated for Low Standby Power ( ITRS: 2005 update )

Figure-chapter 2

Fig. 2-1 Scaling limits of MOCVD HfO² and ZrO².

(International SEMATECH Confidential and Supplier Sensitive, 2002)

Fig 2-2 The ICP plasma system that was used in this experiment.

1. Standard RCA cleaning.

P-type silicon wafer

2. MOCVD HfO

2

50Å.

4. Plasma treatment with N

₂

,NH

₃

or N

₂

O (30sec, 60 sec, 90 sec,120 sec)

HDP-CVD ICP Power

N O

N N

O N

O O

5. Post-Nitridation-Annealing (600℃-60sec)

6. Thermally evaporate 40 nm titanium.

7. Thermally evaporate 400 nm aluminum as top electrode.

8. Lithography：Define top electrode Æ Wet etch undefined Ti and Al.

9. Thermally evaporate 400 nm aluminum as bottom electrode

Fig. 2-3 The fabrication flow of the experiment.

Figure-chapter 3

Fig. 3-1 The capacitance-voltage (C-V) characteristics of HfO2 gate

dielectrics anneal with different temperature for 30 sec from -2 V to 1 V

Fig. 3-2 The J-V characteristics of HfO2 gate dielectrics anneal with different temperature for 30 sec from 0 V to -2 V

Fig. 3-3 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics treated with N2 plasma treatment for different process time.

Fig. 3-4 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics treated with NH3 plasma treatment for different process time.

Fig. 3-5 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics treated with N2O plasma treatment for different process time.

Fig. 3-6 The J-V characteristics of p-type HfO2 capacitors treated by N2 plasma with different process time from 0V to -2V.

Fig. 3-7 The J-V characteristics of p-type HfO2 capacitors treated by NH3 plasma with different process time from 0 V to -2 V.

Fig. 3-8 The J-V characteristics of p-type HfO2 capacitors treated by N2O plasma with different process time from 0 V to -2 V.

Fig. 3-9 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics treated with N2 plasma treatment for 60sec, NH3

plasma treatment for 90 sec and N2O plasma treatment for 90 sec.

Fig. 3-10 The J-V characteristics of HfO2 gate dielectrics treated with N2 plasma treatment for 90 sec, NH3 plasma treatment for 90 sec and N2O plasma treatment for 90 sec.

Fig. 3-11 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics treated with the same PDA temperature annealing and different PDA temperature annealing.

Fig. 3-12 The J-V characteristics of HfO2 gate dielectrics treated with the same PDA temperature annealing and different PDA temperature annealing.

Fig. 3-13 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics after N

2

nitridation and 800 ℃, 850 ℃, 900 ℃ 30 sec thermal treatment.

Fig. 3-14 The J-V characteristics of HfO2 gate dielectrics after N

2

nitridation and 800 ℃, 850 ℃, 900 ℃ 30 sec thermal treatment.

Fig. 3-15 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics after NH3 nitridation and 800 ℃, 850 ℃, 900 ℃ 30 sec thermal treatment.

Fig. 3-16 The J-V characteristics of HfO2 gate dielectrics after NH3 nitridation and 800 ℃, 850 ℃, 900 ℃ 30 sec thermal treatment

Fig. 3-17 The capacitance-voltage (C-V) characteristics of HfO2 gate dielectrics after N2O nitridation and 800 ℃, 850 ℃, 900 ℃ 30 sec thermal treatment.

Fig. 3-18 The J-V characteristics of HfO2 gate dielectrics after N2O nitridation and 800 ℃, 850 ℃, 900 ℃ 30 sec thermal treatment

Figure-chapter 4

Fig. 4-1 The hysteresis of p-type HfO2 gate dielectrics (sputter) without plasma treatment.

Fig. 4-2 The hysteresis of p-type HfO2 gate dielectrics (MOCVD) without

Fig. 4-3 The hysteresis of p-type HfO2 gate dielectrics (MOCVD) with PDA 600℃-30 sec, N2 nitridation 60sec, PNA 600℃-60 sec and 800℃-30 sec

Fig. 4-4 The hysteresis of p-type HfO2 gate dielectrics (MOCVD) with PDA 600℃-30 sec, NH3 nitridation 90sec, PNA 600℃-60 sec and 800℃-30 sec

Fig. 4-5 The hysteresis of p-type HfO2 gate dielectrics (MOCVD) with PDA 600℃-30 sec, N2O nitridation 90sec, PNA 600℃-60 sec and 800℃-30 sec

Fig. 4-6 The SILC curve of p-type HfO2 gate dielectrics treated with N2 plasma 60sec for PDA 600℃-30 sec and PNA 600℃-60 sec

Fig. 4-7 The SILC curve of p-type HfO2 gate dielectrics treated with NH3 plasma 90sec for PDA 600℃-30 sec and PNA 600℃-60 sec

Fig. 4-8 The SILC curve of p-type HfO2 gate dielectrics treated with N2O plasma 90sec for PDA 600℃-30 sec and PNA 600℃-60 sec

Fig. 4-9 Gate current shift of p-type HfO2 gate dielectrics treated with N2 plasma treatment for the same annealing process during Vg = 3V CVS for 180sec

.

Fig. 4-10 Gate current shift of p-type HfO2 gate dielectrics treated with NH3 plasma treatment for the same annealing process during Vg = 3V CVS for 180sec

.

Fig. 4-11 Gate current shift of p-type HfO2 gate dielectrics treated with N2O plasma treatment for the same annealing process during Vg = 3V CVS for 180sec

.

Fig. 4-12 The J-V curve of p-type HfO2 gate dielectrics treated with N2 plasma 60sec for PDA 600℃-30 sec and PNA 600℃-60 sec at 25℃, and 125 ℃from -2 V to 0 V.

Fig. 4-13 The J-V curve of p-type HfO2 gate dielectrics treated with NH

3

plasma 90sec for PDA 600℃-30 sec and PNA 600℃-60 sec at 25℃, and 125 ℃from -2 V to 0 V.

Fig. 4-14 The J-V curve of p-type HfO2 gate dielectrics treated with N

2

O plasma 90sec for PDA 600℃-30 sec and PNA 600℃-60 sec at 25℃, and 125 ℃from -2 V to 0 V.

Fig. 4-15 The J-V curve of p-type HfO2 gate dielectrics treated with N

2

60sec ,NH

3

90 sec and N

2

O 90 sec for PDA 600℃-30 sec and PNA 600℃-60 sec at 25℃, and 125 ℃from -2 V to 0 V.

簡歷

姓 名：湯鈞凱 性 別：男

出生日期：民國 68 年 3 月 10 日 出 生 地：台灣省基隆市

住 址：台北市大安區信義路 3 段 134 巷 76 號 15 樓 學 歷：

私立明志科技大學五專部(民國 83 年 9 月~民國 88 年 6 月) 國立台灣科技大學電子工程系(民國 91 年 9 月~民國 93 年 6 月)

國立交通大學電子工程所微電子奈米科技產學碩士班 (民國 95 年 2 月~民國 97 年 2 月)

碩士論文：電漿處理與退火製程對二氧化鉿熱穩定性之影響 The Effect of Plasma Treatment and Annealing Process on the

Thermal Stability of HfO ² Dielectric

在文檔中 沉積後電漿處理與退火製程對二氧化鉿熱穩定性之影響 (頁 49-84)