I-square circuit

In this section, the I-square circuit would be discussed in detail. Fig. 28 is the simplified circuit of the current squaring.

Msq1 Msq2

Msq3

Iout

+ Va

-+

Vb -Iin

V₂ I₃

I₁

I₂

Fig. 28 The simplified current squaring circuit.

Before the derivation of the current squaring function, some of the assumptions would be considered. First, the transistors of Msq1, Msq2 and Msq3 are operated in the saturation region and all of threshold voltage is the same. Second, the value of k1(W/L)1 is equal to the value of k2(W/L)2 and k3(W/L)3. Thus, all of them are respected as the symbol of K. The Iin is the ac signal of input current. From the Fig. 28, some of the equality could be obtained easily.

1

3 I

I

I_in = − (18)

2 1 K(V_a V_t)

I = − (19)

2

From the above equation, the equation of Iin could be derived as following:

) correlation between equation (21) and (23), the value of Va and Vb could attain.

)

Intuitively, the summing current of I1 and I3 would have the current squared the input current, Iin, Therefore, the output current of the I-square circuit is equal to the current of I1+I3.

₂

From the equation (27), some of the correlations would be obtained. The value of output current of current squaring circuit would be in reverse proportional to the value of V2-2Vt. For the same reason, the conversion gain of current mode down-conversion mixer is in reverse proportional to the value of V2-2Vt. Due to the fixed value of Vt, the conversion gain would be decided by the biasing voltage, V2. However, the performance of linearity is proportional to the biasing voltage. Therefore, the performance of conversion gain and linearity are trade-off in the design consideration of I-square circuit. Fig. 29 presents the simulated results about conversion gain and linearity. From the simulated results, the optimal value of bias voltage V2 is about 1V.

0.4 0.6 0.8 1.0 1.2 1.4 1.6

-40 -30 -20 -10 0 10

-40 -30 -20 -10 0 10

P1dB [dBm]

Converison gain [dB]

Bias voltage V2 [V]

Conversion gain P1dB

Fig. 29 Conversion gain and 1dB compression point of current-mode downconverter

Due to the short-channel effect of MOS device, the drain current ID is shown as following.

) 1

( ) 2 (

1

DS m

t GS ox

n

D V V V

L C W

I = μ − +λ ( 28)

The velocity saturation effect makes the drain current ID proportional to (V_GS −V_T)^m where 1≤ m<2. The drain current is correlated with VDS in the short-channel MOS devices. For the different VDS voltage of VDS1 and VDS3, the function of current square circuit would be worsened. The equation of Iout is shown as (29) and all of the detailed analysis would be introduced in the appendix I.

)

Thus, the smaller difference between VDS1 and VDS3 is the better for the current square operation. The following figure represents the impact of difference VDS voltage. The smaller difference of VDS voltage will have the greater conversion gain of current-mode mixer. Therefore, there are two important issues about the current square circuit. First, the channel length of MOS devices in the current square circuit should be chosen as larger channel length to alleviate the short channel effect.

Second, the biasing voltage of current square circuit should be chosen with the smallest difference of VDS between M1 and M3 MOS devices. While the V2 is equal to VDD, the voltage of VDS1 is very close to VDS3.

0.9 1.0 1.1 1.2 1.3 1.4 1.5

-8 -6 -4 -2 0 2 4 6

0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35

Difference between VDS1 and VDS3 [V]

Conversion gain [dB]

Biasing voltage V2 of current square circuit [V]

Conversion gain |VDS1-VDS3|

Fig. 30 The impact of difference of VDS voltage

The drain current ID of MOS devices may not a quadratic equation of VGS. Fig. 31 compares the difference of drain current between the modified quadratic equation of VGS-Vt and model definition. Below the bias voltage of 0.8V, the differences are very slight. The operated voltage of MOS device in the current squaring circuit is below 0.8V. Therefore, the drain current equation is closed to the quadratic equation of VGS.

The functionality of current squaring is acceptable.

Fig. 31 The difference of drain current of between the modified quadratic equation of VGS-Vt and model definition.

While the input current of I-square circuit is the summing current between ILO and IRF, the output current of I-square circuit could obtain the mixing frequency between ωRF and ωLO. Therefore, the operation of down-conversion mixing can be accomplished. The Fig. 32 shows the complete whole circuit implement.

Fig. 32 The complete whole circuit of I-square circuit.

The capacitance of Csq1 is the block capacitance between I-sum and I-square circuit. The inductor of Lsq1 resonates with the capacitance of Csq2 at the intermediate frequency of 5-GHz and provide high impedances at output terminal of I-square circuit.

Therefore, the Lsq1 and Csq2 could be used as the filter to percolate the leakage signal of LO frequency (19-GHz), RF frequency (24-GHz), up-conversion frequency (19-GHz+24-GHz), the double frequency of RF and LO frequency (48-GHz and 38-GHz) and third frequency of RF and LO frequency (72-GHz and 57-GHz).

2.2.2 Circuit Implementation

The complete schematic of current-mode mixer is shown in Fig. 33 and Table(ii) lists the detailed parameters of each device. The current-mode mixer is composed of three blocks, the I-sum circuit, I-square circuit and output current buffer. First, the I-sum circuit consists of transistors, Ms1 and Ms2, and the inductors, Ls1, Ls2 and Ls3.

The transistors of Ms1 and Ms2 are the common-gate topology connected the drain terminal together. The inductor of Ls1 and Ls2 resonate with the total parasitic capacitance seen at source node of Ms1 and Ms2, respectively. Thus, the LC resonance would provide the high impedance to feed the RF and LO current signal into the common-gate transistor connected the drain terminal together. Then, the inductor Ls3 resonates with the total parasitic capacitance seen at the output node of current summing circuit. Thus, the resonation of Ls3 would provide high impedance to feed the output current of summing circuit into the current squaring circuit. Second, the I-square circuit is composed of transistor of Msq1, Msq2 and Msq3, capacitance of Csq1 and Csq2, and the inductor of Lsq1. The transistor of Msq1, Msq2 and Msq3 would perform the operation of current squaring. The inductor resonates with Csq2 at intermediate frequency of 5-GHz. The resonation between Lsq1 and Csq2 would provide high impedance to feed the output current of current squaring into output current buffer. Finally, the output current buffer provided the performance of 0-dB consists of the transistor of Mb1, Mb2 and inductor, Lb1. Table(ii) lists the detailed parameters of current-mode downconverter.

Fig. 33 The complete circuit of the current-mode circuit.

Table(ii) Detailed parameters of current-mod downconverter.

M_s1,2 RF_MOS 1.2um*32 / 0.13um

Msq1,2,3 RF_MOS 1.2um*12 / 0.13um

M_b1 RF_MOS 1.2um*1 / 0.13um M_b2 RF_MOS 5.0um*30 / 0.13um

C_s1 Mmcap_um 7.5um*7.5um (62.996 fF ) C_s2 Mmcap_um 16um*16um (273.95 fF ) Csq1 Mmcap_um 11um*11um (131.881 fF ) C_sq2 Mmcap_um 31um*31um (1.0 pF)

C_b1 Mmcap_um 23.5um*23.5um (583.4 fF ) Ls1 Spiral_std rad= 20um w=3 nr=3.25 (945.25 pH ) L_s2 Spiral_std rad= 26um w=3 nr=2.75 (916.56 pH ) L_s3 Spiral_std rad= 27.0um w=3 nr=1.5 (443.21 pH ) L_sq1 Spiral_std rad= 15.5um w=3 nr=3.5 ( 884.52 pH) L_b1 Spiral_std rad= 20.0um w=3 nr=4.5 (1.693 nH )