CHAPTER 2 CIRCUIT DESIGN AND SIMULATION
2.1.1 Operational Principle and Design Consideration
2.1.1.2 Noise and Linearity
Low noise figure, low power consumption, high linearity and high gain are the fundamental characteristic in LNA circuit design. But the noise figure, linearity and gain are trade-off with each other for the fixed power consumption. Hence, the optimum value of noise figure, gain and linearity can not be achieved at the same time.
Due to the cascade topology of current-mode LNA, it is significant to understand the effects of cascading on figure-of-merit, such as noise figure and linearity. It is known as Friis’s equation [12] that the noise figure of a cascade of signal blocks can easily be shown in the following equation.
) 1 ( 1 1
2 1
1 1
−
+ −
− + +
=
m p p
m p
tot A A
NF A
NF NF
NF … … (5)
where NFm is the noise figure of the mth stage evaluated with respect to the driving impedance of the preceding stage and Apm is the power gain if mth stage. Therefore,
the noise contributed by each stage decreases as the gain preceding the stage increases, implying that the first few stage in a cascade are most critical. Similarly, we could estimate the linearity of two stage current-mirror amplifier. The production if intermodulation distortion in each stage is complicated. With some simplifying assumption, we could obtain the following equation [2].
+… +
+
≈ 2
3 , 3
2 2 2
1 2
2 , 3 2
1 2
1 , 3 2
3
1 1
IP p p
IP p
IP
IP A
A A A
A A
A (6)
Where AIP3,n denotes the input-referred third-order intercept point of the nth stage and Apn is the power gain of the nth stage. According to the equation (5) and (6), the trade-off between noise figure and linearity are involved with power gain. For example, the noise figure would reduce and linearity worse with a greater power gain. Therefore, the maximal power gain is not the best value. The design issue of the current-mode LNA is to achieve the lower noise figure and a greater power gain with a suitable linearity.
Since the noise figure in the first stage of current mode LNA would directly add to the system. Thus, the first stage of LNA would be performed with a low noise figure and greater gain. Then, the second stage would enhance the overall gain and achieve high linearity performance. However, the biasing voltage and transistor size would be involved with both of the power gain and noise figure performance. Therefore, the biasing voltage and transistor size need to choose carefully.
The noise contribution would be discussed in detail in the first instance. The dominant noise contribution brings from the MOS transistor. Therefore, the noise contribution of the CMOS device would be introduced clearly. The standard CMOS small signal noise model is shown in Fig. 17 [13] and the noise calculation would
adopt this noise model.
i
d2i
g2v
Rg2
Fig. 17 The standard CMOS small signal noise model [13].
The dominant noise source in the CMOS device is channel thermal noise. This source of noise is commonly modeled as a shunt current source in the output circuit of the device. The channel noise is white with a power spectral density given by
0 2
4 d
d kT g
f
i = γ
Δ (7) The parameter of gd0 is the zero-bias drain conductance of the device and γis a bias-dependent factor that, for long-channel devices, satisfies the inequality
3 1
2 ≤γ ≤ (8) The value of 2/3 holds when the device is saturated and the value of 1 is valid when the drain-source voltage is zero. For short-channel devices, however, γ does not satisfy equation (8). In fact, γ can be much greater the 2/3 for short-channel devices operating in saturation [14].
This excess noise may be attributed to the presence of hot electrons in the channel. The high electric fields in sub-micron MOS devices cause the electron temperature, Te, to exceed the lattice temperature. The excess noise due to carrier
heating was anticipated by van der Ziel as early as 1970 [15].
Then, an additional source of noise in MOS devices is the noise generated by the distributed gate resistance [16]. This noise source could be modeled by a series resistance in the gate circuit and an accompanying white noise generator. By interdigitating the device, the contribution of this noise source could be reduced to insignificant levels. For noise purposes, the effective gate resistance is given by [17]
L n
W Rg R 2
3
= □ (9) where R□ is the sheet resistance of the polysilicon, W is the total gate width of the device, L is the gate length and n is the number of gate fingers used to layout the device. The factor of 1/3 arises from a distributed analysis of the gate, assuming that each gate finger is contacted only at one end. By contacting at both ends, this term reduces to 1/12. In addition, this expression neglects the interconnect resistance used to connect the multiple gate fingers together. Interconnect can be routed in a metal layer that possesses significantly lower sheet resistance and hence is easily rendered insignificant. Its significance is further reduced in silicided CMOS process which possess a greatly reduced sheet resistance, R□. Due to the TSMC CMOS 0.13um technology which is a silicided CMOS process, the noise source of gate resistance would be neglected when calculating the noise contribution.
The gate-induced noise is proceeded to introduce. When the device is biased so that the channel is inverted, fluctuations in the channel charge would induce a physical current in the gate due to the capacitive coupling. At frequencies approaching ωT, the gate impedance of the device exhibits a significant phase shift from its purely capacitive value at lower frequencies. This shift could be accounted by including a real conductance, gg, and a shunt noise current, i . Mathematical expressions for g2 these sources are
g
g kT g
f
i 4 δ
2
Δ = (10)
0 2 2
5 d
gs
g g
g ω C
= (11)
where δ is the coefficient of gate noise, classically equal to 4/3 for long-channel devices. The equations of (10) and (11) are valid when the device is operated in saturation. However, in the gate noise expression, gg is proportional to ω2 and hence the gate noise is not a white noise source. Therefore, Fig. 18 is the simplified small signal noise model which neglected the Cgd capacitance for convenient estimation.
The Fig. 18 would apply to estimate the noise contribution of current-mode LNA.
i
d2i
2gFig. 18 The simplified small signal noise model.
The noise performance of a circuit is usually characterized by a parameter called noise factor (F) or noise figure (NF ≡10logF) that represents how much the given system degrades the signal-to-noise ratio [18].
out in
SNR
F ≡ SNR (12)
only souece to
due power noise
output Total
power noise
output Total
F = (13)
The simplified schematic diagram of noise source distribution of input stage is shown in Fig. 19. And the small signal equivalent circuit for noise calculation is shown in Fig.
20 where the channel thermal noise power of the mth MOS device isin2,m equal to
m
gdo
kT ,
4 γ , the gated-induced noise power of the mth MOS device is ig2,m equal to
m d
m gs
g C
, 0
2 , 2
5
ω and the thermal noise power of Rs is 2
RS
i equal to Rs
kT 4 .
M1 M2
L1 L2
L3 VDD_LNA
C1
2
i
Rs Rs in2,1 22 ,
in 2
12 ,
ig
i
out2VDD_LNA
X Zin
Fig. 19 The noise source distribution of the input stage.
i
dFig. 20 The small-signal circuit of input stage for noise calculations.
For noise calculation, the output noise power is estimated with some of the reasonable assumption. First, the inductor, L1, would resonate with the total parasitic capacitance at X node including the Cgs,12. Second, the inductor, L3, would resonate with Cgd2. From the diagram of Fig. 20, the output noise power in2,out could be driven as following equation (14).
2
Due to the definition of equation (13), the noise factor of input stage of the current-mode LNA is presented as the following equation.
2
From above equation, the noise figure performance is involved with the Cgs, gdo,
operating frequency and input impedance, Zin. However, the value of Cgs is proportional to the size value of transistor. The biasing voltage would influence the value both of gd0 and Zin. In order to obtain the minimum noise figure, the optimum value both of transistor size and biasing voltage would be chosen with the simulator tools. The setup of NFmim versus VGS simulation is shown in Fig. 21.
TSMC_013RF_CYWU_NMOS_RF M1
nr=nr lr=0.13 um wr=1.2 um model=nmos_rf L
L2 R=
L=1.0 H
L L1 R=
L=1.0 H
C C2 C=1.0 F
V_DC SRC1 Vdc=1.2
C C1 C=1.0 uF
Term Term2 Z=50 Num=2 I_Probe
IDS V_DC
SRC3 Vdc=VGS V
Term Term1 Z=50 Num=1
Fig. 21 The setup of NFmin versus VGS simulation.
The parameter of nr is the finger number of transistor. The simulation results are shown in Fig. 22, the diagram of minimum noise figure versus biasing voltage, VGS, with different transistor size. Then, the simulation result of the power gain, dB(S(2,1)), versus VGS with different transistor is shown in Fig. 23.
0.5 0.6 0.7 0.8 0.9 1.0 1.1
0.4 1.2
1.0 1.2 1.4 1.6 1.8 2.0
0.8 2.2
nr=8.00 nr=12.0 nr=16.0 nr=20.0 nr=24.0 nr=28.0 nr=32.0 nr=36.0 nr=40.0 nr=44.0 nr=48.0 nr=52.0 nr=56.0 nr=60.0 nr=64.0
VGS
N F mi n, dB
m2 m2 VGS=
NFmin[0]=1.280 nr=44.000000
650.0m
Fig. 22 The simulation result of minimum noise figure versus VGS.
0.5 0.6 0.7 0.8 0.9 1.0 1.1
0.4 1.2
-15 -10 -5 0 5
-20 10
nr=8.00 nr=12.0 nr=16.0 nr=20.0 nr=24.0 nr=28.0 nr=32.0 nr=36.0 nr=40.0 nr=44.0 nr=48.0 nr=52.0 nr=56.0 nr=60.0 nr=64.0
VGS
dB (S 21)
m1
m1 VGS=
dB(S21[0])=6.043 nr=44.000000
650.0m
Fig. 23 The simulation result of dB(S(2,1)) versus VGS.
From the simulation results, the noise figure would be worse with both of the larger transistor size and higher biasing voltage. But the power gain performance is greater with larger transistor size and biasing voltage. Thus, the minimum noise figure, power gain and power consumption are a trade-off. The design issue in this thesis is to achieve the lower noise figure with a suitable power gain and acceptable power consumption.
The linearity of the transistor is also involved with biasing voltage. Unfortunately, in the condition of the best noise figure performance is always the worst case of linearity performance. The Taylor series is used to expand the drain current. The drain current in Taylor expansions could be expressed as following:
+… +
+ +
≈ ( ) ' 2 " 3
)
( GS DS GS m gs m gs m gs
ds v I V g v g v g v
i (16)
The third-order intercept point (AIP3) of gate voltage amplitude is shown as the following equation.
"
3 3
4
m m
IP g
A = g (17)
where gm is the transconductance of transistor and g"m is the second-order differential of transconductance. And the simulation results about gm and g are m"
shown in Fig. 24.
Fig. 24 The transconductance of transistor device.
From the simulation result of Fig. 24, the worst case of the third-order intercept point occurs at the biasing voltage of 550mV. But, the biasing voltage of 550mV is the best value of noise figure performance. From the simulation results of Fig. 22, Fig. 23 and Fig. 24, the value of biasing voltage is chosen as 650mV with a lower noise figure, suitable power gain, acceptable power consumption and linearity.