Introduction of LC Ladder Filters

Although the subject of this thesis is the design of active filters, we shall discuss some details concerning the design of passive LC filters. As the name implies, an LC filter is a lossless transmission network consisting of only inductors and capacitors. In normal operation, the network is embedded between a resistive source and a resistive load as shown in Figure 4.1, and Figure 4.2 shows the ladder topology. A lossless ladder is a circuit structure where all components apart from source and load resistors are lossless, that is, they are inductors and capacitors that dissipate no energy. Passive LC ladders have an inherent advantage over active filters in terms of their sensitivity to component tolerances. With the growing pressure towards microminiaturization, inductors were found to be too bulky so that designers started to replace passive RLC filters by active RC circuits where gain, obtained from operational amplifiers, together with resistors and capacitors in feedback networks, was used to achieve complex poles.

Figure 4.1 Resistively terminated lossless twoport.

Figure 4.2 Resistively terminated ladder structure.

4.2.2 LC Ladder Simulation by Signal-Flow Graphs

Lossless filters designed for maximum power transfer have the best possible passband sensitivities, and such circuits are normally realized as LC ladders. A considerable amount of effort has been devoted in recent years to the development of active circuits which in one way or another simulate performance of passive ladders and thereby inherit their good sensitivity performance. Ladder simulations can be classified into two groups: operational simulation and element substitution. Both methods start from an existing LC prototype ladder; operational simulation endeavors to represent the internal operation of the ladder by simulating the equations describing the circuit’s performance, i.e., Kirchhoff’s voltage and current laws and the I-V relationships of the ladder arms. Fundamentally, this procedure is based on simulating the signal-flow graph (SFG) of the ladder where all voltages and all currents are considered signals which propagate through the circuit.

For our purposes, the signal-flow graph (SFG) method can be understood most easily by considering a section of a ladder as shown in Figure 4.3. The circuit is analyzed readily by writing Kirchhoff’s laws and the I-V relationships for the ladder arms as follows:

Figure 4.3 Section of a ladder network.

In the active simulation of this circuit, all currents and voltages are to be represented as voltage signals. In order to achieve this goal, we use a resistive scaling factor R as shown in one of these equations as an example,

n n-1 n+1

I R = I R - I R V = _n ^Zn I R = _n ^Zn (I R -I R)_{n-1 n+1}

R R (4.2) and introduce the notation

k k

The lowercase symbols are used to represent the scaled quantities; note that z and y

are now dimensionless voltage transfer functions and that both ik and vk are voltages.

We have retained the symbol ik in order to remind ourselves of the origin of that signal as a current in the original ladder. With Equation (4.3), equation group (4.1) takes on the following form:

n-2 n-3 n-1

This group of equations indicates that for a successful simulation we need to build voltage summers to implement Kirchhoff’s laws (e.g., to add the voltages in-1 and –in+1

to form the voltage in) and we need to realize the frequency-dependent multipliers or transfer functions (also called transmittances) zk or yk (e.g., to convert the voltage in

into the signal vn). Assuming that the necessary circuits are available, the flow diagram in Figure 4.4 with the indicated interconnections gives the realization of the ladder section in Figure 4.3. As is customary, we have drawn the “current signals” and their summing nodes in the top line and the “voltage signals” with their summing nodes in the bottom line.

The implementation is slightly inconvenient because it requires taking the difference of two signals. It is quite obvious that summing of signals is preferable.

Figure 4.5 shows that only additions are required, and it guarantees also that all internal loop gains are negative. The SFG diagram of Figure 4.5 is also referred to as leapfrog (LF) topology; the reason for this name becomes apparent when the circuit is redrawn as shown in Figure 4.6. At this occasion we also wish to emphasize that the correct realization of the transfer function poles implies that all loop gains, such as znyn+1, in the signal-flow graph must be realized correctly. For example, assuming in-3

to be the input, vn+2 the output, and in+3 = 0, the function realized by the graph in Figure 4.4 can be shown to equal

( )

The expression shows quite clearly that the transfer function poles can be expected to be accurate if all loop gains are realized correctly. It will serve as a guide in our later implementation of general signal-flow graph filters.

Figure 4.4 Signal-flow graph block diagram representation of the ladder section in Figure 4.3.

Figure 4.5 Transformation resulting in only positive input summers.

Figure 4.6 The diagram of Figure 4.5 redrawn in the leapfrog (LF) configuration.

Example: Let’s illustrate this process on a simple fourth-order all-pole lowpass filter.

Figure 4.7 shows an LC ladder with two series inductors and two shunt capacitors along with two terminating resistors. As discussed, let’s normalize all the elements by dividing them by a scaling resistor R and label

With this notation, the required equations are

Figure 4.7 Fourth-order lowpass ladder.

The corresponding signal-flow graph implementation is shown in Figure 4.8. We have introduced an arbitrary constant K at the input which multiplies all signals by K and permits us thereby to realize in the active circuit the prescribed transfer function with a gain K. At this point we have to investigate how to realize the conceptual diagram of Figure 4.8 as an active RC filter. It is apparent that we require summers as well as lossy and lossless inverting and noninverting integrators. Observe that the ladder simulation consists of a number of two-integrator loops, containing an inverting and a noninverting integrator each. The two integrators are shown in Figure 4.9 and they realize

where the minus sign is valid for the inverting lossy Miller integrator and the plus sign must be used for the phase-lead integrator.

1

1 sl +rs

2

1 sc

−

3

1

sl 4

1 sc gL

− +

Figure 4.8 Simulation flow diagram of the ladder of Figure 4.7

(a)

(b)

Figure 4.9 (a) Inverting lossy Miller integrator; (b) noninverting lossy phase-lead integrator.

Note from Figure 4.8 that the internal ladder arms are realized by lossless integrators (R3 = ∞) whereas the two end branches require lossy integrators (R3 is finite) in order to account for load resistors. Thus, it remains only to interconnect the appropriate versions of Figure 4.9 in the manner prescribed in Figure 4.8 to arrive at the final circuit shown in Figure 4.10. At the internal output nodes, we have indicated the signals of Figure 4.8 which correspond to the voltages in the final realization.

-+

+- -⁺

+

-+- +-

+-Figure 4.10 Active realization of the LC ladder of +-Figure 4.7.

All capacitors were chosen equal for convenience. One method for finding the values of the resistors from the known components of the LC ladder requires comparing the equations realized by Figure 4.10 with the corresponding equations, Eq. (4.7), that describe the original ladder:

1 2

6 2 7 4

Consider the needed equality of the time constants and from the dc gain factors of the signals Vin and (-v2) in equation (4.9a), we find respectively

1 By substituting equations (4.10) into (4.11) and (4.12), we obtain

1

Note that the value of R1 determines the realized gain K. Similarly, we find from equations (4.9b) through (4.9d):

2

The scaling resistor R and the capacitor C have arbitrary values and can be chosen to obtain convenient and practical components.