Chapter III Design of Tuning Circuit
3.4 Simulation Results of the Tuning Circuit
Figure 3.10 Transient response of the output control voltage, Vnctrl.
Figure 3.10 shows the transient response of the output control voltage, Vnctrl.
This output control voltage which varies from 372mV to 384mV is stabilized at the voltage of 378mV when the amplitude of the input signal of the OTA is 0.7V. Figure 3.11 shows the transient response of the output control voltage, Vpctrl, and at the stable situation, the output voltage, Vpctrl, is -661mV with 10mV amplitude when the amplitude of the input signal of the OTA is 0.7V.
Figure 3.11 Transient response of the output control voltage, Vpctrl.
Chapter IV
Design of Continuous-Time Gm-C Filters
4.1 Fundamental Concepts of Analog Filters
A filter is a twoport that shapes the spectrum of the input signal in order to obtain an output signal with the desired frequency content. Thus, a filter has a passbands where the frequency components are transmitted to the output and stopbands where they are rejected. The oldest technology for realizing filters makes use of inductors and capacitors, and the resulting circuits are called passive LC filters. Today, in order to miniaturize the size of filters, inductors cannot be used because their size cannot be reduced to a level compatible with modern integrated electronics. Therefore, there has been considerable interest in finding filter realizations that do not require inductors.
The inductors can be avoided if we have access to gain. Therefore, the only passive components we need are resistors and capacitors, and gain is provided by operational amplifiers or operational transconductance amplifiers (OTAs). Such filters are referred to as active filters, sometimes more specifically as analog active filters to distinguish them from digital filters. Signals in analog active filers are normally continuous functions of time, sometimes sampled, whereas in digital filters signals are digitized. In modern communication systems, both analog signals and digital signals must be processed. Often both analog and digital circuits and filters must be implemented together on the same integrated circuit chip for so-called mixed-mode signal processing.
4.2 LC Ladder Simulation by Signal-Flow Graphs
4.2.1 Introduction of LC Ladder Filters
Although the subject of this thesis is the design of active filters, we shall discuss some details concerning the design of passive LC filters. As the name implies, an LC filter is a lossless transmission network consisting of only inductors and capacitors. In normal operation, the network is embedded between a resistive source and a resistive load as shown in Figure 4.1, and Figure 4.2 shows the ladder topology. A lossless ladder is a circuit structure where all components apart from source and load resistors are lossless, that is, they are inductors and capacitors that dissipate no energy. Passive LC ladders have an inherent advantage over active filters in terms of their sensitivity to component tolerances. With the growing pressure towards microminiaturization, inductors were found to be too bulky so that designers started to replace passive RLC filters by active RC circuits where gain, obtained from operational amplifiers, together with resistors and capacitors in feedback networks, was used to achieve complex poles.
Figure 4.1 Resistively terminated lossless twoport.
Figure 4.2 Resistively terminated ladder structure.
4.2.2 LC Ladder Simulation by Signal-Flow Graphs
Lossless filters designed for maximum power transfer have the best possible passband sensitivities, and such circuits are normally realized as LC ladders. A considerable amount of effort has been devoted in recent years to the development of active circuits which in one way or another simulate performance of passive ladders and thereby inherit their good sensitivity performance. Ladder simulations can be classified into two groups: operational simulation and element substitution. Both methods start from an existing LC prototype ladder; operational simulation endeavors to represent the internal operation of the ladder by simulating the equations describing the circuit’s performance, i.e., Kirchhoff’s voltage and current laws and the I-V relationships of the ladder arms. Fundamentally, this procedure is based on simulating the signal-flow graph (SFG) of the ladder where all voltages and all currents are considered signals which propagate through the circuit.
For our purposes, the signal-flow graph (SFG) method can be understood most easily by considering a section of a ladder as shown in Figure 4.3. The circuit is analyzed readily by writing Kirchhoff’s laws and the I-V relationships for the ladder arms as follows:
Figure 4.3 Section of a ladder network.
In the active simulation of this circuit, all currents and voltages are to be represented as voltage signals. In order to achieve this goal, we use a resistive scaling factor R as shown in one of these equations as an example,
n n-1 n+1
I R = I R - I R V = n Zn I R = n Zn (I R -I R)n-1 n+1
R R (4.2) and introduce the notation
k k
The lowercase symbols are used to represent the scaled quantities; note that z and y
are now dimensionless voltage transfer functions and that both ik and vk are voltages.
We have retained the symbol ik in order to remind ourselves of the origin of that signal as a current in the original ladder. With Equation (4.3), equation group (4.1) takes on the following form:
n-2 n-3 n-1
This group of equations indicates that for a successful simulation we need to build voltage summers to implement Kirchhoff’s laws (e.g., to add the voltages in-1 and –in+1
to form the voltage in) and we need to realize the frequency-dependent multipliers or transfer functions (also called transmittances) zk or yk (e.g., to convert the voltage in
into the signal vn). Assuming that the necessary circuits are available, the flow diagram in Figure 4.4 with the indicated interconnections gives the realization of the ladder section in Figure 4.3. As is customary, we have drawn the “current signals” and their summing nodes in the top line and the “voltage signals” with their summing nodes in the bottom line.
The implementation is slightly inconvenient because it requires taking the difference of two signals. It is quite obvious that summing of signals is preferable.
Figure 4.5 shows that only additions are required, and it guarantees also that all internal loop gains are negative. The SFG diagram of Figure 4.5 is also referred to as leapfrog (LF) topology; the reason for this name becomes apparent when the circuit is redrawn as shown in Figure 4.6. At this occasion we also wish to emphasize that the correct realization of the transfer function poles implies that all loop gains, such as znyn+1, in the signal-flow graph must be realized correctly. For example, assuming in-3
to be the input, vn+2 the output, and in+3 = 0, the function realized by the graph in Figure 4.4 can be shown to equal
( )
The expression shows quite clearly that the transfer function poles can be expected to be accurate if all loop gains are realized correctly. It will serve as a guide in our later implementation of general signal-flow graph filters.
Figure 4.4 Signal-flow graph block diagram representation of the ladder section in Figure 4.3.
Figure 4.5 Transformation resulting in only positive input summers.
Figure 4.6 The diagram of Figure 4.5 redrawn in the leapfrog (LF) configuration.
Example: Let’s illustrate this process on a simple fourth-order all-pole lowpass filter.
Figure 4.7 shows an LC ladder with two series inductors and two shunt capacitors along with two terminating resistors. As discussed, let’s normalize all the elements by dividing them by a scaling resistor R and label
With this notation, the required equations are
Figure 4.7 Fourth-order lowpass ladder.
The corresponding signal-flow graph implementation is shown in Figure 4.8. We have introduced an arbitrary constant K at the input which multiplies all signals by K and permits us thereby to realize in the active circuit the prescribed transfer function with a gain K. At this point we have to investigate how to realize the conceptual diagram of Figure 4.8 as an active RC filter. It is apparent that we require summers as well as lossy and lossless inverting and noninverting integrators. Observe that the ladder simulation consists of a number of two-integrator loops, containing an inverting and a noninverting integrator each. The two integrators are shown in Figure 4.9 and they realize
where the minus sign is valid for the inverting lossy Miller integrator and the plus sign must be used for the phase-lead integrator.
1
1 sl +rs
2
1 sc
−
3
1
sl 4
1 sc gL
− +
Figure 4.8 Simulation flow diagram of the ladder of Figure 4.7
(a)
(b)
Figure 4.9 (a) Inverting lossy Miller integrator; (b) noninverting lossy phase-lead integrator.
Note from Figure 4.8 that the internal ladder arms are realized by lossless integrators (R3 = ∞) whereas the two end branches require lossy integrators (R3 is finite) in order to account for load resistors. Thus, it remains only to interconnect the appropriate versions of Figure 4.9 in the manner prescribed in Figure 4.8 to arrive at the final circuit shown in Figure 4.10. At the internal output nodes, we have indicated the signals of Figure 4.8 which correspond to the voltages in the final realization.
-+
+- -+
+
-+- +-
+-Figure 4.10 Active realization of the LC ladder of +-Figure 4.7.
All capacitors were chosen equal for convenience. One method for finding the values of the resistors from the known components of the LC ladder requires comparing the equations realized by Figure 4.10 with the corresponding equations, Eq. (4.7), that describe the original ladder:
1 2
6 2 7 4
Consider the needed equality of the time constants and from the dc gain factors of the signals Vin and (-v2) in equation (4.9a), we find respectively
1 By substituting equations (4.10) into (4.11) and (4.12), we obtain
1
Note that the value of R1 determines the realized gain K. Similarly, we find from equations (4.9b) through (4.9d):
2
The scaling resistor R and the capacitor C have arbitrary values and can be chosen to obtain convenient and practical components.
4.3 Fifth-Order Elliptic Low-Pass GM-C Filter
Figure 4.11 shows a fifth-order elliptic low-pass LC-ladder prototype filter. By using signal-flow graph methods [13, 18, 25], it can be transformed into a fifth-order elliptic low-pass gm-C filter which consists of seven identical differential-input OTAs and seven capacitors. Here we will introduce a very successful and popular way which is used to transform an LC passive filter into a active Gm-C filter. The way is based on the powerful signal-flow graph (SFG) method which, after impedance scaling, treats all voltages and currents in the passive circuit as voltage signals and realizes the effect of both inductors and capacitors via integrators. For example, the voltages V1 in Figure 4.11 is obtained by integrating the difference between I1 and I2:
1 1
1
1 (
V I
= sC −I2) (4.17)
Figure 4.11 Fifth-order elliptic LC lowpass filter
We also note as a further advantage of the SFG method the possibility of scaling
range[23]. Because integrators can be realized with transconductances and grounded capacitors, it stands to reason that Gm-C design methods can be adapted to the SFG procedure. Specifically, it has been shown that ladder filters with quite arbitrary branches can be implemented as Gm-C circuits where furthermore all transconductors, with the exception of possibly one, are identical and all capacitors are grounded.
Inevitably, this approach is very desirable because it results in simple processing technologies. The insistence on only grounded capacitors, however, entails a penalty:
the realization requires many active devices (transconductors) because floating capacitors, such as C2 in Figure 4.11, result in equations with terms proportional to s,
(
1 3) (
which with integrators must be realized in the form 1/(1/s). A very efficient realization with savings of a large number of transconductors can be achieved, however, if floating capacitors are acceptable[20]. Consider the typical ladder section in Figure 4.12. The relevant equations describing this circuit can be written as
(
Figure 4.12 Typical ladder section with a floating capacitor.
where IL2 and IC2 can be expressed as:
By substituting equations (4.20) and (4.21) into (4.19), we obtain
( ) (
To convert the currents into voltages for active SFG simulation, we multiply both equations in (4.20) and (4.22) by a normalizing resistor R and a transconductance value gm to obtain the expressions(
1 3)
which are realized by the circuits in Figure 4.13+
Figure 4.13 Realizations of Equations (4.23) and (4.24)
In the Figure 4.13, we have labeled: VI1=RI1 and VI2=RIL2. Let us now set R=1/gm.
From Figure 4.13, the capacitors representing the inductors are then obtained by CL=gm2L. Combining the appropriate blocks identified in Figure 4.13 in the way specified via Figure 4.11 gives the Gm-C simulation of the fifth-order elliptic lowpass ladder in Figure 4.14. Observe that the realization is very efficient, it uses only seven capacitors and seven OTAs for the seven reactances in the original ladder, including the source and load resistors that were simulated via R=1/gm. From filter tables[21]
we will find the values of the seven capacitors.
Vin
Vout
+ + +
+ + +
+
C2 C4
C1 C3 C5
Cl2 Cl4
Figure 4.14 Gm-C SFG simulation of the circuit in Figure 4.11.
4.4 Total Harmonic Distortion (THD)
If a sinusoidal waveform is applied to a linear time-invariant system, it is known that the output will also be a sinusoidal waveform at the same frequency, but possibly
with different magnitude and phase values. However, if the same input is applied to a nonlinear system, the output signal will have frequency at harmonics of the input waveform, including the fundamental harmonic. For example, if the input signal is a 1-MHz sinusoidal waveform, the output signal will have power at the fundamental, 1 MHz, as well as at the harmonic frequencies, 2MHz, 3MHz, and so on. The total harmonic distortion (THD) of a signal is defined to be the ratio of the total power of the second and higher harmonic components to the power of the fundamental for that signal. In units of dB, THD is found using the following relation:
2 2 2
where Vf is the amplitude of the fundamental and Vhi is the amplitude of the ith harmonic component. Sometimes THD is presented as a percentage value as follow:
2 2 2
It should be noted that the THD value is almost always a function of the amplitude of the input signal level, and thus the corresponding signal amplitude must also be reported. Also, for practical reasons, typically the power of only the first few (say, the first 5) harmonics are included since the distortion components usually fall off quickly for higher harmonics.
4.5 Simulation Results of the Filter
After designing the low-voltage CMOS fifth-order elliptic low-pass Gm-C filter and the frequency tuning circuit, the simulation result would be shown in this section.
Figure 4.15 shows the frequency response of the gm-C filter with the common-mode voltage at 0V, -0.6V, and 0.6V. In this thesis, the filter can operate at large input signals and wide common-mode voltage ranges, and the cutoff frequencies of this filter at different input common-mode voltages are about 2MHz. By using a simple way to analyze the fifth-order elliptic LC lowpass filter, suppose R1=RS and we will know that the magnitude are always at -6dB when we input the signal with low frequency. Figure 4.16 shows the tunable range of the cutoff frequency of the filter, and the cutoff frequency range of the filter is from 1.6MHz to 2.4 MHz.
Figure 4.15 The frequency responses of the gm-C filter with the common-mode voltage at 0V, -0.6V, and 0.6V.
Figure 4.16 Tunable range of the cutoff frequency.
The Total Harmonic Distortion (THD) of the filter is shown in Figure 4.17. The THD is less than -40dB when the input peak-to-peak voltage varies from 0V to 1.4V at 100kHz frequency.
Figure 4.17 Total harmonic distortion of the filter for different input voltages.
Chapter V
Post Layout Simulation Results
5.1 Post Layout Simulation Results of the OTA
The DC response of the OTA was shown in Figure 5.1 and 5.2. Figure 5.1 shows the V-I curves of the differential-input OTA with different corner at V1=0v, and Figure 5.2 shows the V-I curves of the differential-input OTA with different corner at V2=0v. The OTA circuit can operate at the input common voltage of ±0.8v with a power supply of 1.8v depending on the 0.18um UMC technology.
(a)
(b)
(c)
Figure 5.1 Post layout: DC response of the OTA with different corner (a)tt (b)ss (c) ff at V1=0v
(a)
(b)
(c)
Figure 5.2 Post layout: DC response of the OTA with different corner (a)tt (b)ss (c) ff at V2=0v
5.2 Post Layout Simulation Results of the gm-C filter
Figure 5.3 Post layout: frequency responses of the gm-C filter with the common-mode voltage at 0V, -0.6V, and 0.6V.
Figure 5.3 shows the frequency response of the gm-C filter with the common-mode voltage at 0V, -0.6V, and 0.6V, and the -3dB frequencies are all about 2MHz. The magnitude are at -6dB when we input the signal with low frequency.
Figure 5.4 Post layout: transient response of gm-C filter with 1MHz input signal.
Figure 5.5 Post layout: transient response of gm-C filter with 2MHz input signal.
The transient response of the filter was evaluated with a 1.4V peak-to-peak and 2MHz input sinusoidal signal. Figure 5.4 shows the output signal with 1.4Vpp and 1MHz input signal. The amplitude of the output signal is about a half of the amplitude of input signal. Figure 5.5 shows the output signal with 1.4Vpp and 2MHz input signal, and the amplitude is about 200mV.
Figure 5.6 FFT analysis of the filter output.
Figure 5.6 shows the FFT analysis of the output of the filter. The input is a sine wave with 100kHz frequency and 1.4Vpp, and the total harmonic distortion is below -40dB. In addition to Figure 5.6, Figure 4.16 shows total harmonic distortion of the filter for different input voltage.
Specifications Results Process UMC 0.18µm CMOS
Mixed-Signal
Power supply ±0.9V
Filter category fifth-order elliptic low-pass gm-C filter Cutoff frequency
range 1.6MHz-2.4MHz
Dynamic input range 1.4Vpp Input common-mode
voltage range -0.7v～0.7v Chip area 1.16 x 0.93mm2 Power dissipation 0.75mW
Table 5.1 The specifications of the fifth-order elliptic low-pass gm-C filter
A table of post layout simulation results of the fitler has been shown in Table 5.1.
The results of the simulation prove that the filter is working at a cutoff frequency of 1.6MHz-2.4MHz and its input common-mode voltage and input signal ranges are
±0.7v. Figure 5.7 shows the layout of the gm-C filter including the principal part of the filter and two frequency tuning circuits and the chip area is 1.16 x 0.93mm2.
The principal
part of the gm-C
filter
Two frequency tuning circuits.
Figure 5.7 The layout of the gm-C filter.
Chapter VI
Conclusions and future research
This thesis presents a 2MHz low-voltage CMOS fifth-order elliptic low-pass gm-C filter with large differential input swings and wide common-mode ranges. By using a technique, the dynamic input range is increased to 1.4Vpp at 1.8V power supply. The frequency tuning circuitry is used to adjust the cutoff frequency of the gm-C filter, which can be tuned from 1.6MHz to 2.4MHz by changing the clock frequency of the switched-capacitor equivalent resistor. The total harmonic distortion is less than -40dB when the input peak-to-peak voltage varies from 0V to 1.4V at 100kHz frequency, and the power consumption is 0.75mW.
With the progress of the process, the power supply voltage can be decreased, but the dynamic range of circuits will diminish. Hence many researches are mainly aimed at improving the dynamic range. Besides, in the future, we have to find the way to make the other performance better, including reducing the supply voltage and power consumption, improving the linearity of OTAs and the total harmonic distortion, and increasing the tunable bandwidth range of the filter, etc.
Bibliography
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Electron Lett., vol. 29, pp. 1145–1146, 1993.
[2] Chung-Chih Hung, Kari Halonen, Veikko Porra, and Mohammed Ismail,
“Low-Voltage CMOS GM-C Filter with Rail-to-Rail Common-Mode Voltage,” IEEE 39th Midwest symposium on Circuits and Systems, Volume 2, pp.921 – 924, Aug.
18-21, 1996.
[3] Chung-Chih Hung, K. A. I. Halonen, M. Ismail, V. Porra, and A. Hyogo, ”A
[3] Chung-Chih Hung, K. A. I. Halonen, M. Ismail, V. Porra, and A. Hyogo, ”A