Chapter 3 SiC power MOSFET
3.3 Material advantages of 4H-SiC for power devices
By using the known material properties of semiconductors, it is possible to select those that will exhibit a lower ideal specific on-resistance when compared with silicon by using this expression It has been found that most promising semiconductor are gallium arsenide, whose Baliga’s figure of merit is 12.7 times larger than silicon, and silicon carbide whose Baliga’s figure of merit is 200 times larger than silicon. Although some research has been performed on the fabrication of vertical power MOSFET’s from gallium arsenide, this material has been found to be difficult to work with due to dissociation of the compound during processing. In contrast, silicon carbide offers a such larger improvement in ideal specific on-resistance and is stable even at extremely temperatures.
In the case of Si, the extract dependency of the electron mobility and the breakdown field on the doping concentration is known [23]
91 MOSFET’s, a closed form analysis which requires the solution of ionization integral, using an abrupt junction diode, is used for calculating expressions for
N
B andW
for a Si power MOSFET are obtain as [17]4
the dependency of the breakdown field strength of 4H-SiC and 6H-SiC on
N
B was determined from the calculated values from [17,9]. The empirical relationship betweenE
BandV
B onN
B was obtained as voltage for Si and SiC power MOSFET’s. This analysis suggests that 4H-SiC MOSFET would have lowerR than 6H-SiC. For a given breakdown voltage,
onR for the SiC
on MOSFET is at least two orders of magnitude smaller than for Si MOSFET, and the ratio ofR of the Si MOSFET to that of SiC MOSFET increases with increasing breakdown voltage.
onDue to the excellent characteristics of SiC, it would be desirable to utilize power MOSFET for high voltage power applications. Unfortunately, the specific on-resistance of the drift region increases very rapidly with increasing breakdown voltage because of the need to reduce its doping concentration and increase its thickness [4]. Thus, in spite of the ability to obtain nearly ideal specific on-resistance with silicon power MOSFET structures, they are not
satisfactory for applications that require breakdown voltages above 300V due to their high on-state power dissipation. So, many reasons make SiC an attractive candidate for fabricating power devices.
3-4 Summary
The superiority of 4H-SiC illustrated in this chapter is just one of the potential projections in using this wide semiconductor material for high power devices. These advantages in terms of calculated figure of merits provide a motivation for the design and development of power devices on SiC. Despite the unique problems in device fabrication, which many are not yet totally resolved, promising progress in the device development has taken place in the area of power MOSFETs.
Chapter 4
The electrical performance of SiC MOSFET
Silicon-based switching devices have reached the theoretical limitations for high power and for high power and high temperature applications whereas silicon carbide (SiC) has emerged as an alternate material system to overcome the limitations and can be used in extreme environment.
4-1 Introduction
Since SiC is a attractive semiconductor materials for high-power electric devices because they have excellent physical properties such as a wide bandgap, high breakdown voltage, and high saturation electron drift velocity. However, due to higher layer mobility as compared to inversion layer mobility, ACCUFETs emerge as the preferred solution for power MOSFETs on SiC [24]. Channel mobility of power MOSFET’s is one of the most important parameters that determines the on-resistance in the conducting state. More work need to be done to reduce the specific on-resistance and increase the blocking voltage capability in SiC power MOSFEET. The emergence of ACCUFET structures in SiC reveals important advantages in terms of higher channel-carrier mobility [6]. The ACCUFETs structure shows a much promising result in terms of their specific on-resistance compared to the inversion power MOSFET. The main focus in this chapter based on the introduction of design of accumulation-mode power MOSFETs and its optimization using MEDICI two-dimensional device simulator [1].
It should be noted, however, that the contribution and the conclusions in this thesis do
not rely on quantitative results. The methodology used in this paper focuses on the merits of the devices structure itself, independent of the specific parameter values, which are still dominated by different technology imperfections.
4.2. The trench and planar ACCUFET
4-2-1 The trench ACCUFET
Many researchers focus their attention on the SiC MOSFET designed using trench technology, since it offers high channel density and eliminates JFET effect characteristic of DMOS structure. In spite of their advantages, the trench MOSFET have several drawbacks such as high threshold voltage and poor mobility in the channel, which is adversely affects the on-state resistance. Another serve drawback of the trench MOSFET is the gate oxide breakdown, which can occur in off state, under high electric field [8,16].
As it was mentioned earlier, the strongest limitations of SiC trench MOSFET are the dielectric breakdown can occur before semiconductor breakdown. Writing the Gaussian low in the SiC-SiO2 interface
Considering the ration of dielectric constant of SiC/ SiO2 (9.7/3.9) and ESiC-BR is 3MV/cm ,it is found that the maximum allowable of electric field in the oxide is 7.46x106V/cm. However, due to two-dimensional simulations at the trench corner, the value in the oxide can be higher
than 7x106 V/cm without encountering semiconductor breakdown. Nevertheless, in ordered to have a reliable device, the oxide electric field should be kept under it practical value of 7x106 V/cm.
The simulations of breakdown structure have been shown in the Fig 4.1, drift thickness and concentration are 10μm and 1x1016cm-3 respectively, channel length of 2.0μm, an N+ polysilicon gate electrode over an 100nm thick gate oxide (QF=1x1011 cm-2), an N+ region concentration of 1x1020 cm-3. It has been found that, for a breakdown voltage of 980V, the electric field at the trench corner has the value of 7.8x106 V/cm, consider the theoretical value calculated earlier, it is clear that the device will breakdown because of oxide rupture. To improve this problem, try to wide the trench and round the corner. Because in this way, the curvature of potential lines at the trench corner would be soften [10].
In Table 4.1 the value of electric field as a function of the trench width, for rectangular and rounded corners and a tox of 0.1μm, breakdown voltage of 980V are simulated. As a consequence, by using wide trench in conjunction with rounded trench corners, the electric field in the oxide corner can be kept in the critical value. The influence of gate oxide thickness upon the breakdown voltage has also been investigated. For the rounded trench MOSFETS , breakdown simulation has been carried out, for different oxide thickness and trench width. The simulation results are shown in Table 4.2.
From the results shown in Table 4.2, it can be inferred that there is an inverse proportionality relationship between the oxide thickness and breakdown voltage. Although the simulator does not taken into account the oxide breakdown, we can state that above 7.46x106 V/cm the device breakdown through the avalanche tunneling gate oxide.
4-2-2 The planar ACCUFET
In silicon, a double-diffused MOSFET (DMOSFET) is the most common structure used for fabricating power MOSFETs [12].The DIMOS/DMOS structure offers high reliability, ease of integration with ICs and simplicity of fabrication because the gate oxide is shielded from the high electric fields by the adjacent p-type base regions. The cross section of the ACCUFET structure is shown in Fig. 4.2 the n-drift region doping and thickness have been designed to support a high voltage, the entire device is expected to have a high blocking voltage, and since the ACCUFET is a planar device, it does not suffer from any enhanced electric fields, unlike the UMOSFET. In this structure, a thin n-type region is formed below the MOS gate by using a buried p implanted layer. The thickness and doping of this n layer is carefully chosen such that it is completely depleted by the built in potentials of the p /n junction and the MOS gate at zero bias, resulting in a normally-off To obtain reasonable reliability for a device, the electric field in the SiC must be restricted to below 3 MV/cm. The ACCUFET achieves this by suppressing the peak electric field from the surface between SiC and SiO2, to below the p base region [5].
Two different P-base region spacing LP designs were fabricated with different lengths observe the effect of this parameter on the performance of this device. From the simulations, it was found that the electric field near the interface of SiO2 and SiC can be controlled by adjusting When LP was reduced, When LP was reduced, the region above it gets shielded from the high drain voltage thereby reducing the electric field near the oxide. The relationship between P-base spacing (LP) and Ron also be simulated by MEDICI simulator. The dominant sources of on-resistance in an ACCUFET are [14]: the channel resistance of the accumulation layer; the “JFET resistance” between the adjacent P-base regions; and the drift resistance of
the low doped, voltage-blocking layer. The simulation results of Fig. 4.3 show that a distinct minimum exists for specific on-resistance as is changed from 1 μm to 6 μm. This is because a trade-off exists between the JFET region resistance and the channel resistance. An increase in results in an increase in unit cell pitch, which increases the channel resistance per unit area. On the other hand, as is reduced below 2.5 μm, a dramatic increase in the JFET region resistance occurs because of a reduced current carrying width between adjacent P-base regions [15].
4-3 The innovative SiC ACCUFET
The cross section of the proposed structure is shown in Fig. 4.4 In this structure, a thin N-type region is formed below the MOS gate by using a buried P implanted layer. The thickness and doping of this N-layer is carefully chosen such that it is completely depleted by the built-in potentials of the P+/ N- junction and the MOS gate at zero gate bias, resulting in a normally-off device with the entire drain voltage supported by the P+/N-drift junction. Since this P+/ N- junction can support high voltages. When a positive gate bias is applied, an accumulation channel (of electrons) is created at the interface between SiO2 and SiC. This results in a low resistance path for the electron current flow from the source through the channel, then down to the drain through the drift region to the drain. Assuming that the higher accumulation layer mobility (as compared to the inversion layer mobility) observed in silicon applies to silicon carbide also, a lower on-resistance is expected for the device, which will be referred to as the planar ACCUFET. The main feature of this accumulation type MOSFET is the N-type channel, epitaxially grown on P-base region. Two-dimensional numerical simulations were done using MEDICI with parameters taken from [28] for the ACCUFET structure.
4-4 Analysis and optimization of device parameters
In the following, we will discuss the relationship blocking and driving capability of this structure upon these parameters including, the doping concentration and thickness of P-base layer, and the peak doping concentration of ion-implanted trench region. Two-dimensional numerical simulation structure (including the mesh, the boundaries, and the impurity profiles) for the device was generated in MEDICI. Due to the symmetry of the devices, only half of the device structure was simulated. The structure has a fixed 10μm N-drift region at 1x1017cm-3, an N+ type polysilicon gate electrode with an 100nm thick oxide(QF=1.0x1011cm-2) , a channel length of 2.0μm. The simulation results were used to calculate Baliga’s Figure of Merit (BFOM) as the criterion for structure optimization and comparison.
Peak trench region concentration
We choose the peak concentration of ion-implanted trench region has to be set higher than the P-base concentration (NA). The two P-base concentration 1.1x1017 cm-3, 1.6x1017 cm-3of 2μm thick p-base thick epilayer, were selected. The peak trench concentration of ion-implanted region was varied from 1.15x1017 cm-3 to 1.6x1017 cm-3 for
N
A=
1.1x1017cm-3, from 1.65x1017cm-3 to 2.1x1017 cm-3 forN
A=
1.6x1017 cm-3.The simulation results were shown in Fig. 4.5, Fig. 4.6 the maximum blocking voltage was 1780V with NA =1.1x1017 cm-3 with a slightly higher peak trench region concentration of 1.15x1017 cm-3. The maximum operating voltage in this region is determined by the dielectric breakdown before the semiconductor breakdown. When NA =1.6x1017 cm-3, avalanche breakdown occurring in the trench region determines the blocking capability of the device.
From the results, to obtain the maximum operating voltage of the device, also thinking about figure of merit for power devices that is used to optimize the considered parameters. The best trade-off between the breakdown voltage and on-resistance in terms of BFOM is achieved with peak trench region concentration 1.45x1017cm-3for NA =1.1x1017cm-3
.
P-base layer thickness
The simulation results of p-base thickness upon blocking voltage, on-resistance are shown in Fig. 4.7.In this simulations, the optimum values of the parameter considered in the previous simulation with peak trench region concentration 1.45x1017cm-3 for
N
A=
1.1x1017cm-3. As shown in Fig. 4.7, the P-base thickness play an important role on Blocking voltage. The simulation results shows that the p-base epilayer thickness of 2μ
m is the optimum value in terms of BFOM. Furthermore, we use the same models and parameters in the MEDICI device simulator to obtain and compare the performance characteristics of the structures mention above with innovative ACCUFET. These structures set to have a drift region thickness and concentration 10μm and 1.1x1017 cm-3, respectively, channel length of 2.0μm, an N+-type polysilicon gate electrode over an 100nm thick gate oxide( QF=1.1x1011 cm-2 ) , an N+ region concentration of 1.0x1017cm-3, and a Gaussian doping profile with characteristic width of 0.15μm. The results of simulation are shown as for Table 4.3.The results show clearly that the innovative ACCUFET structure enables a better performance than the trench and planar structure.4-5 Summary
Power devices made with silicon carbide ( SiC ) are expected show great performance advantages as compared to those made with other semiconductor. Therefore, conventional SiC
MOSFETS suffer high specific on-resistance due to low channel mobility.
The innovative structure of accumulation mode MOSFET for high power applications has been proposed and analyzed in MEDICI. The peak concentration of the ion-implanted trench region strongly influences the breakdown voltage and on-resisitance of the device. To obtain the maximum operating voltage, the peak concentration of the ion-implanted trench region has to be slightly higher than the p-base epilayer. The thickness of p-base epilayer does not play an important role in on-resistance. How ever, it changes the maximum blocking voltage significantly. By using the MEDICI simulator, the best trade off between on-resistance and maximum blocking voltage by setting the thickness of p-base layer precisely. The electrical performances of trench and planar ACCUFET, are mainly limited by the oxide breakdown and p-well spacing.
Chapter 5 Conclusion
The analysis of 4H-SiC as compared to Si as a semiconductor material for power MOSFET has been shown in favor of 4H-SiC due to its superior material properties. An improvement of two-order magnitude in the specific on resistance of ideal 4H-SiC MOSFET over ideal Si MOSFET is projected. However, a review of the state of the art of SiC power MOSFETs indicates that the performance progress of SiC power devices have been hampered by MOS interface related issues which resulted in high channel resistance and oxide breakdown. Numerical device simulation-based optimization efforts for this novel device have been performed which resulted in optimum device with blocking voltage more than 1.2kV.
Parameter extraction for numerical device simulation of 4H-SiC unipolar devices is the first major topic developed in this thesis. Using 2D numerical device simulation MEDICI , in the models describing electronic devices, the material parameters of Si are replaced by respective parameters of 4H-SiC reported in literature. Using the MEDICI two-dimension simulator, with already existing models to design and optimization of 4H-SiC MOSFETs.
As the main objective of the MOS device research is to bring the channel mobilities in SiC MOS devices as high as the bulk mobilities in SiC and improve reliability of SiO2 layer.
The future generation of SiC MOS based devices should the necessary quality dielectric layers and low defect between dielectric and semiconductor interface.
Reference
[1] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York:
Springer-Verlag, 1984.
[2] Technology Modeling Associates, inc., TMA MEDICI Two-dimensional Devices Simulation Program ver.2. 3., MEDICI user’s Manial, vol. 1, 1997.
[3] B.J. baliga, Modern Power devices, New York: Wiley, 1987.
[4] J. wang, and B. W. Williams, “Evaluation of high-voltage 4H-SiC switching devices,”
IEEE Trans. Elect. Dev., vol.46,p. 589,1999.
[5] P. M. shenoy and B. J. Baliga, “ The planar 6H-SiC ACCUFET: A new high-voltage power MOSFET structure,” IEEE Elect. Dev. Lett ., vol.18, p.589,1997.
[6] S.Harada, S. Suzuki, J. Senzaki, R. kosugi, K. Adachi, K. Fukuda, and K. Arau, “High channel mobility in normally-off 4H-SiC buried channel MOSFETs”, IEEE Elect. Dev.
Lett., vol. 22, p. 272,2001
[7] B. J. Baliga, “Power semiconductor device figure of merit for high-frquency applications ”, IEEE Elect. Dev. Lett., vol.10,p. 455, 1989.
[8] K. G. Pani Dharmawardana and Gehan A. J. Amaratunga, “ Modeling of high current density trench gate MOSFET ”, IEEE Elect. Dev. Lett., vol.47,p. 2420, 2000.
[9] R.Raghunathan and b. J. Baliga, “Temperature dependence of hole impact ionization coefficients in 4H and 6H ”, Solid-State Elect., vol. 43, p.199, 1999.
[10] K.Shenai, “Optimized trench MOSFET technologies for power devices,” IEEE Trans.
Elect. Dev., vol. 39, p. 1435, 1992
[11] C. Lombarbi, S.Mazini, A.Saporito, and M. Vanzi, “ A physical based mobility model for numerical simulation of nonlanar devices” ,IEEE Trans. on Computer-Aided Design, vol. 7, no. 11, p. 1164, 1988.
[12] J. N. Shenoy, J. A. Cooper, Jr, and M. R. Melloch, “High-voltage double-implanted power MOSFET’s in 6H-SiC”, IEEE Elect. Dev. Lett ., vol.18, p.93,1997.
[13] M. Ruff, H. Mitlehner, and R. Helbig, “SiC devices: Physics and numerical simulation,”
IEEE Trans. Electron Devices, vol. 41, p. 1040, June 1993.
[14] R. Singh, D. C. Cpaell, Mirinal K. Das, L. A. lipkin, and John W. Palmour“Development of high-current 4H-SiC ACCUFET ” IEEE Trans. Electron Devices, vol. 50, p. 471, Feb 2003.
[15] M. Hasanuzzaman, S. K. Islam, L.M. Tolbert, B.Ozpinect, “Model simulation and verification of a vertical double implanted (DIMOS) transistor in 4H-SiC ”.
[16] A. K. Agrarwal, J. B. Casady, L. B. Rowland, W. F. valek, M. H. White, and C. D.
Brandt, “1.1kV 4H-SiC power UMOSFET’s”, IEEE Elect. Dev. Lett, vol. 18, p.
586,1997.
[17] M.Bhatnagar and B. J. Baliga, “Comparsion of 6H-SiC, 3C-SiC, and Si for power devices”, IEEE Elect. Dev. Lett. , vol.p18, p. 586,1997.
[18] R.P.Joshi, “ Monte Carlo caluations of the temperature-and field- dependent electron transport parameters for 4H-SiC ”, J. Appl. Phys., vol.78, p.5518,1995.
[19] R. Mickevius, and J. H. Zhao, “ Monte Carlo study of electron transport in SiC ”, Appl.
Phys., vol. 83, p. 3161, 1998
[20] W. Fulop, “ Caluation of avalanche breakdown of silicon p-n junctions ”, Solid-State Elect., vol.10, p.39, 1937.
[21] C. E. Weitzel, J. W. Plamour, C. H. Carter, K. Moore, K. J. Nordquist, S. Allen, C. Thero,
“ silicon carbide High-Power Devices”IEEE Trans. Electron Devices, vol. 43, p. 1732, Oct 1996.
[22] E. Arnold and D.Alok, “ Effect of the surface states on electron transport in 4H-SiC inversion layers ”, IEEE Trans. Electron Devices, vol. 48, p. 1870, 2001.
[23] C. Jacoboni, C. Canali, G. Ottaviani, and A. A. Quaranta, “A review of some charge transport properties of silicon ”, Solid-State Elect., vol.20, p. 77, 1977.
[24] H.Linewih, S.Dimitrijev, C. E. Weitzel, and H. B. Harrison., “ Novel
Accumulation-mode power MOSFET ”, IEEE Trans. Electron Devices, vol. 48, p. 1171,
2001.
[25] M. R. Roschke and F. schwierz, “Electron mobility models for 4h, 6H, and 3C SiC ”, IEEE Trans. Electron Devices, vol. 48, p. 1442, 2001.
[26] I. A. Khan and j. A. Cooper, J. A. Cooper, Jr., “Measurement of high-field electron transport in silicon carbide”, IEEE Trans. Electron Devices, vol. 47, p. 269, 2000.
[27] Handoko Linewih and Sima Dimitrijev., “ Channel-Carrier Mobility Parameters for 4H SiCMOSFETs ” , INTERNATIONAL CONFERENCE ON MICROELECTRONICS , VOL 2,YUGOSLAVIA, 12-15 MAY, 2002
[28] S. Onda,R.Kumar, and K.Hara, “SiC integrated MOSFETs ” Phys. Stat. Sol. Vol.162, p.369,1997.
Fig.1.1 Applications for power devices in relation to their voltage and current ratings
Fig.1.2 Lateral n-channel MOSFETs cross section.
Fig. 1.3 The cross section of various power MOSFET structure
Fig.1.4 The operation of power DMOS
Fig. 2.1 Low-field electron mobility as a function of doping concentration in 4H-SiC (perpendicular to the c-axis, T = 300 K).
Fig. 2.2 Drift velocity of electron in 4H-SiC as functions of the applied
Fig. 2.2 Drift velocity of electron in 4H-SiC as functions of the applied