The planar ACCUFET

In silicon, a double-diffused MOSFET (DMOSFET) is the most common structure used for fabricating power MOSFETs [12].The DIMOS/DMOS structure offers high reliability, ease of integration with ICs and simplicity of fabrication because the gate oxide is shielded from the high electric fields by the adjacent p-type base regions. The cross section of the ACCUFET structure is shown in Fig. 4.2 the n-drift region doping and thickness have been designed to support a high voltage, the entire device is expected to have a high blocking voltage, and since the ACCUFET is a planar device, it does not suffer from any enhanced electric fields, unlike the UMOSFET. In this structure, a thin n-type region is formed below the MOS gate by using a buried p implanted layer. The thickness and doping of this n layer is carefully chosen such that it is completely depleted by the built in potentials of the p /n junction and the MOS gate at zero bias, resulting in a normally-off To obtain reasonable reliability for a device, the electric field in the SiC must be restricted to below 3 MV/cm. The ACCUFET achieves this by suppressing the peak electric field from the surface between SiC and SiO2, to below the p base region [5].

Two different P-base region spacing LP designs were fabricated with different lengths observe the effect of this parameter on the performance of this device. From the simulations, it was found that the electric field near the interface of SiO2 and SiC can be controlled by adjusting When LP was reduced, When LP was reduced, the region above it gets shielded from the high drain voltage thereby reducing the electric field near the oxide. The relationship between P-base spacing (LP) and Ron also be simulated by MEDICI simulator. The dominant sources of on-resistance in an ACCUFET are [14]: the channel resistance of the accumulation layer; the “JFET resistance” between the adjacent P-base regions; and the drift resistance of

the low doped, voltage-blocking layer. The simulation results of Fig. 4.3 show that a distinct minimum exists for specific on-resistance as is changed from 1 μm to 6 μm. This is because a trade-off exists between the JFET region resistance and the channel resistance. An increase in results in an increase in unit cell pitch, which increases the channel resistance per unit area. On the other hand, as is reduced below 2.5 μm, a dramatic increase in the JFET region resistance occurs because of a reduced current carrying width between adjacent P-base regions [15].

4-3 The innovative SiC ACCUFET

The cross section of the proposed structure is shown in Fig. 4.4 In this structure, a thin N-type region is formed below the MOS gate by using a buried P implanted layer. The thickness and doping of this N-layer is carefully chosen such that it is completely depleted by the built-in potentials of the P+/ N- junction and the MOS gate at zero gate bias, resulting in a normally-off device with the entire drain voltage supported by the P+/N-drift junction. Since this P+/ N- junction can support high voltages. When a positive gate bias is applied, an accumulation channel (of electrons) is created at the interface between SiO2 and SiC. This results in a low resistance path for the electron current flow from the source through the channel, then down to the drain through the drift region to the drain. Assuming that the higher accumulation layer mobility (as compared to the inversion layer mobility) observed in silicon applies to silicon carbide also, a lower on-resistance is expected for the device, which will be referred to as the planar ACCUFET. The main feature of this accumulation type MOSFET is the N-type channel, epitaxially grown on P-base region. Two-dimensional numerical simulations were done using MEDICI with parameters taken from [28] for the ACCUFET structure.

4-4 Analysis and optimization of device parameters

In the following, we will discuss the relationship blocking and driving capability of this structure upon these parameters including, the doping concentration and thickness of P-base layer, and the peak doping concentration of ion-implanted trench region. Two-dimensional numerical simulation structure (including the mesh, the boundaries, and the impurity profiles) for the device was generated in MEDICI. Due to the symmetry of the devices, only half of the device structure was simulated. The structure has a fixed 10μm N-drift region at 1x10¹⁷cm^-3, an N⁺ type polysilicon gate electrode with an 100nm thick oxide(QF=1.0x10¹¹cm^-2) , a channel length of 2.0μm. The simulation results were used to calculate Baliga’s Figure of Merit (BFOM) as the criterion for structure optimization and comparison.

Peak trench region concentration

We choose the peak concentration of ion-implanted trench region has to be set higher than the P-base concentration (NA). The two P-base concentration 1.1x10¹⁷ cm^-3, 1.6x10¹⁷ cm^-3of 2μm thick p-base thick epilayer, were selected. The peak trench concentration of ion-implanted region was varied from 1.15x10¹⁷ cm^-3 to 1.6x10¹⁷ cm^-3 for

N

_A

=

1.1x10¹⁷cm^-3, from 1.65x10¹⁷cm^-3 to 2.1x10¹⁷ cm^-3 for

N

_A

=

1.6x10¹⁷ cm^-3.

The simulation results were shown in Fig. 4.5, Fig. 4.6 the maximum blocking voltage was 1780V with NA =1.1x10¹⁷ cm^-3 with a slightly higher peak trench region concentration of 1.15x10¹⁷ cm^-3. The maximum operating voltage in this region is determined by the dielectric breakdown before the semiconductor breakdown. When NA =1.6x10¹⁷ cm^-3, avalanche breakdown occurring in the trench region determines the blocking capability of the device.

From the results, to obtain the maximum operating voltage of the device, also thinking about figure of merit for power devices that is used to optimize the considered parameters. The best trade-off between the breakdown voltage and on-resistance in terms of BFOM is achieved with peak trench region concentration 1.45x10¹⁷cm^-3for NA =1.1x10¹⁷cm^-3

.

P-base layer thickness

The simulation results of p-base thickness upon blocking voltage, on-resistance are shown in Fig. 4.7.In this simulations, the optimum values of the parameter considered in the previous simulation with peak trench region concentration 1.45x10¹⁷cm^-3 for

N

_A

=

1.1x10¹⁷cm^-3. As shown in Fig. 4.7, the P-base thickness play an important role on Blocking voltage. The simulation results shows that the p-base epilayer thickness of 2

μ

m is the optimum value in terms of BFOM. Furthermore, we use the same models and parameters in the MEDICI device simulator to obtain and compare the performance characteristics of the structures mention above with innovative ACCUFET. These structures set to have a drift region thickness and concentration 10μm and 1.1x10¹⁷ cm^-3, respectively, channel length of 2.0μm, an N+-type polysilicon gate electrode over an 100nm thick gate oxide( QF=1.1x10¹¹ cm^-2 ) , an N+ region concentration of 1.0x10¹⁷cm^-3, and a Gaussian doping profile with characteristic width of 0.15μm. The results of simulation are shown as for Table 4.3.The results show clearly that the innovative ACCUFET structure enables a better performance than the trench and planar structure.

4-5 Summary

Power devices made with silicon carbide ( SiC ) are expected show great performance advantages as compared to those made with other semiconductor. Therefore, conventional SiC

MOSFETS suffer high specific on-resistance due to low channel mobility.

The innovative structure of accumulation mode MOSFET for high power applications has been proposed and analyzed in MEDICI. The peak concentration of the ion-implanted trench region strongly influences the breakdown voltage and on-resisitance of the device. To obtain the maximum operating voltage, the peak concentration of the ion-implanted trench region has to be slightly higher than the p-base epilayer. The thickness of p-base epilayer does not play an important role in on-resistance. How ever, it changes the maximum blocking voltage significantly. By using the MEDICI simulator, the best trade off between on-resistance and maximum blocking voltage by setting the thickness of p-base layer precisely. The electrical performances of trench and planar ACCUFET, are mainly limited by the oxide breakdown and p-well spacing.

Chapter 5 Conclusion

The analysis of 4H-SiC as compared to Si as a semiconductor material for power MOSFET has been shown in favor of 4H-SiC due to its superior material properties. An improvement of two-order magnitude in the specific on resistance of ideal 4H-SiC MOSFET over ideal Si MOSFET is projected. However, a review of the state of the art of SiC power MOSFETs indicates that the performance progress of SiC power devices have been hampered by MOS interface related issues which resulted in high channel resistance and oxide breakdown. Numerical device simulation-based optimization efforts for this novel device have been performed which resulted in optimum device with blocking voltage more than 1.2kV.

Parameter extraction for numerical device simulation of 4H-SiC unipolar devices is the first major topic developed in this thesis. Using 2D numerical device simulation MEDICI , in the models describing electronic devices, the material parameters of Si are replaced by respective parameters of 4H-SiC reported in literature. Using the MEDICI two-dimension simulator, with already existing models to design and optimization of 4H-SiC MOSFETs.

As the main objective of the MOS device research is to bring the channel mobilities in SiC MOS devices as high as the bulk mobilities in SiC and improve reliability of SiO2 layer.

The future generation of SiC MOS based devices should the necessary quality dielectric layers and low defect between dielectric and semiconductor interface.

Reference

[1] S. Selberherr, Analysis and Simulation of Semiconductor Devices. New York:

Springer-Verlag, 1984.

[2] Technology Modeling Associates, inc., TMA MEDICI Two-dimensional Devices Simulation Program ver.2. 3., MEDICI user’s Manial, vol. 1, 1997.

[3] B.J. baliga, Modern Power devices, New York: Wiley, 1987.

[4] J. wang, and B. W. Williams, “Evaluation of high-voltage 4H-SiC switching devices,”

IEEE Trans. Elect. Dev., vol.46,p. 589,1999.

[5] P. M. shenoy and B. J. Baliga, “ The planar 6H-SiC ACCUFET: A new high-voltage power MOSFET structure,” IEEE Elect. Dev. Lett ., vol.18, p.589,1997.

[6] S.Harada, S. Suzuki, J. Senzaki, R. kosugi, K. Adachi, K. Fukuda, and K. Arau, “High channel mobility in normally-off 4H-SiC buried channel MOSFETs”, IEEE Elect. Dev.

Lett., vol. 22, p. 272,2001

[7] B. J. Baliga, “Power semiconductor device figure of merit for high-frquency applications ”, IEEE Elect. Dev. Lett., vol.10,p. 455, 1989.

[8] K. G. Pani Dharmawardana and Gehan A. J. Amaratunga, “ Modeling of high current density trench gate MOSFET ”, IEEE Elect. Dev. Lett., vol.47,p. 2420, 2000.

[9] R.Raghunathan and b. J. Baliga, “Temperature dependence of hole impact ionization coefficients in 4H and 6H ”, Solid-State Elect., vol. 43, p.199, 1999.

[10] K.Shenai, “Optimized trench MOSFET technologies for power devices,” IEEE Trans.

Elect. Dev., vol. 39, p. 1435, 1992

[11] C. Lombarbi, S.Mazini, A.Saporito, and M. Vanzi, “ A physical based mobility model for numerical simulation of nonlanar devices” ,IEEE Trans. on Computer-Aided Design, vol. 7, no. 11, p. 1164, 1988.

[12] J. N. Shenoy, J. A. Cooper, Jr, and M. R. Melloch, “High-voltage double-implanted power MOSFET’s in 6H-SiC”, IEEE Elect. Dev. Lett ., vol.18, p.93,1997.

[13] M. Ruff, H. Mitlehner, and R. Helbig, “SiC devices: Physics and numerical simulation,”

IEEE Trans. Electron Devices, vol. 41, p. 1040, June 1993.

[14] R. Singh, D. C. Cpaell, Mirinal K. Das, L. A. lipkin, and John W. Palmour“Development of high-current 4H-SiC ACCUFET ” IEEE Trans. Electron Devices, vol. 50, p. 471, Feb 2003.

[15] M. Hasanuzzaman, S. K. Islam, L.M. Tolbert, B.Ozpinect, “Model simulation and verification of a vertical double implanted (DIMOS) transistor in 4H-SiC ”.

[16] A. K. Agrarwal, J. B. Casady, L. B. Rowland, W. F. valek, M. H. White, and C. D.

Brandt, “1.1kV 4H-SiC power UMOSFET’s”, IEEE Elect. Dev. Lett, vol. 18, p.

586,1997.

[17] M.Bhatnagar and B. J. Baliga, “Comparsion of 6H-SiC, 3C-SiC, and Si for power devices”, IEEE Elect. Dev. Lett. , vol.p18, p. 586,1997.

[18] R.P.Joshi, “ Monte Carlo caluations of the temperature-and field- dependent electron transport parameters for 4H-SiC ”, J. Appl. Phys., vol.78, p.5518,1995.

[19] R. Mickevius, and J. H. Zhao, “ Monte Carlo study of electron transport in SiC ”, Appl.

Phys., vol. 83, p. 3161, 1998

[20] W. Fulop, “ Caluation of avalanche breakdown of silicon p-n junctions ”, Solid-State Elect., vol.10, p.39, 1937.

[21] C. E. Weitzel, J. W. Plamour, C. H. Carter, K. Moore, K. J. Nordquist, S. Allen, C. Thero,

“ silicon carbide High-Power Devices”IEEE Trans. Electron Devices, vol. 43, p. 1732, Oct 1996.

[22] E. Arnold and D.Alok, “ Effect of the surface states on electron transport in 4H-SiC inversion layers ”, IEEE Trans. Electron Devices, vol. 48, p. 1870, 2001.

[23] C. Jacoboni, C. Canali, G. Ottaviani, and A. A. Quaranta, “A review of some charge transport properties of silicon ”, Solid-State Elect., vol.20, p. 77, 1977.

[24] H.Linewih, S.Dimitrijev, C. E. Weitzel, and H. B. Harrison., “ Novel

Accumulation-mode power MOSFET ”, IEEE Trans. Electron Devices, vol. 48, p. 1171,

2001.

[25] M. R. Roschke and F. schwierz, “Electron mobility models for 4h, 6H, and 3C SiC ”, IEEE Trans. Electron Devices, vol. 48, p. 1442, 2001.

[26] I. A. Khan and j. A. Cooper, J. A. Cooper, Jr., “Measurement of high-field electron transport in silicon carbide”, IEEE Trans. Electron Devices, vol. 47, p. 269, 2000.

[27] Handoko Linewih and Sima Dimitrijev., “ Channel-Carrier Mobility Parameters for 4H SiCMOSFETs ” , INTERNATIONAL CONFERENCE ON MICROELECTRONICS , VOL 2,YUGOSLAVIA, 12-15 MAY, 2002

[28] S. Onda,R.Kumar, and K.Hara, “SiC integrated MOSFETs ” Phys. Stat. Sol. Vol.162, p.369,1997.

Fig.1.1 Applications for power devices in relation to their voltage and current ratings

Fig.1.2 Lateral n-channel MOSFETs cross section.

Fig. 1.3 The cross section of various power MOSFET structure

Fig.1.4 The operation of power DMOS

Fig. 2.1 Low-field electron mobility as a function of doping concentration in 4H-SiC (perpendicular to the c-axis, T = 300 K).

Fig. 2.2 Drift velocity of electron in 4H-SiC as functions of the applied field.

Fig. 2.3 Mobility between the experimental data and simulation with the parameter values listed in Table 2-2

Fig. 2.4 Temperature dependence of the coefficients ap and bp for 4H-SiC

R

^N+

Rc R

A

R

J

R

^D

R

^S

Gate

N+

P-base

N-Drift Region

N+ Substrate Source

DRAIN

Fig. 3.1 A cross section of a power DMOS MOSFETs structure

n⁺

Gate

P-well

n-n⁺

Drain Source

Fig. 4.1 The cross section of trench MOSFET

Fig. 4.2 The cross section of accumulation DMOS

0 1 2 3 4 5 6 7 8 6

8 10 12 14 16 18 20

Ron( ohm ic )

P-base spacing(10

^-6

m)

Fig. 4.3 The relationship between P-base spacing (LP) and Ron

Fig. 4.4 The cross section of Innovative SiC ACCUFET

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1000

1100 1200 1300 1400 1500 1600 1700 1800 1900 2000

M a x imum Bloc k ing Volt age(V)

Peak Trench Concentration( 10

¹⁷

cm

^-3

) NA=1.1x10 17 cm -3

Fig. 4.5(a) Effect of peak trench-region concentration on maximum operating voltage.

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2

3 4 5 6 7 8 9 10 11 12

Ron(ohm ic )

Peak Trench Concentration (10

¹⁷

cm

^-3

) N

A

=1.1x10

¹⁷

cm

^-3

Fig. 4.5(b) Effect of peak trench-region concentration on Ron resistance

1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 3.0

3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0

BF OM ( 10

5

V

2

/ohm ic )

Peak Trench Concentration( 10

¹⁷

cm

^-3

) N

A

=1.1x10

¹⁷

cm

^-3

Fig. 4.5(c) Effect of peak trench-region concentration on BFOM

1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 800

900 1000 1100 1200 1300 1400 1500

M ax im un Bl oc k ing Volt age (V)

Peak trench concentration ( 10

¹⁷

cm

^-3

) NA=1.6x10 17

cm -3

Fig. 4.6(a) Effect of peak trench-region concentration on maximum operating voltage.

1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.0

2.5 3.0 3.5 4.0 4.5 5.0

Ron( ohm ic )

Peak Trench Concentration( 10

¹⁷

cm

^-3

) N

_A

=1.6x10

¹⁷

cm

^-3

Fig. 4.6(b) Effect of peak trench-region concentration on Ron resistance.

1.6 1.7 1.8 1.9 2.0 2.1 4.0

4.4 4.8 5.2 5.6 6.0 6.4 6.8

BFOM( 105 V2 /ohmic )

Peak trench concentration( 10

¹⁷

cm

^-3

)

NA=1.6x10

¹⁷

cm

^-3

Fig. 4.6(c) Effect of peak trench-region concentration on BFOM.

1.2 1.4 1.6 1.8 2.0 2.2 2.4 800

1000 1200 1400 1600 1800

M ax im um Blo c k ing Vol tag e(V)

P-base Thickness (10

^-6

m)

Fig. 4.7(a) Effects of P-base thickness on blocking voltage.

1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.5

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Ron( ohm ic )

P-base Thickness (10

^-6

m)

Fig. 4.7(b) Effects of P-base thickness on Ron resistance.

1.2 1.5 1.8 2.1 2.4 3.0

3.5 4.0 4.5 5.0 5.5 6.0

BF OM ( 10

5

V

2

/ohm ic )

P-base Thickness(10

^-6

m)

Fig. 4.7(c) Effects of P-base thickness on Ron resistance.

Table 1.1 Comparison of Si and SiC material properties

Table 2.1 Parameter of low field model for 4H-SiC at 300K

Parameter 4H-SiC

MUN.MIN 40cm

²

/Vs

MUN.MAX 950 cm

²

/Vs

NRFEN 2x10

¹⁷

cm

^-3

ALPHAN 0.76

Table 2.2 Parameters for 4H-SiC MOSFET mobility models.

parameter Unit 4H-SiC

μmin

cm

²

/Vs 40

μ_max

cm

²

/Vs 950 N

_ref

cm

^-3

2x10

¹⁷

α

0.76

B

1.0x10

⁶

C

1.74x10

⁵

α

l 0.0516

D

V/s 5.82x10

¹⁴

Table 3.1 Values of doping concentration, electron mobility, drift layer thickness, and specific on-resistance as a function of breakdown voltage for ideal 4H-SiC and Si power MOSFET at room temperature condition.

Breakdown

Table 4.1 Oxide electric field in the trench corner as a functions of trench width, for rectangular and round corner.

Trench width(μm) 4 8 12

Oxide electric field (

10 ⁶

^V/cm)

Rectangular corner

7.8 7.1 6.4

Oxide electric field (

10 ⁶

V/cm) Rounded corner

6.9 6.3 5.8

Table 4.2 The dependence of the oxide electric field at the trench corner of the oxide

thickness.

Oxide thickness(μm) 0.1 0.2 0.3

E oxide

(

10 ⁶

^V/cm)

Trench width

(8

^μm

)

6.3 5.7 4.9

E _oxide

(

10 ⁶

V/cm)

Trench width (12

^μm

)

5.8 5.1 4.3

Table 4.3 Comparison of ACCUFET structure

Structure MAX.Blocking Voltage（V）

On-resistance (Ω)

BFOM (V

²

/Ω)

Trench 980 3.87 2.48x10

⁵

DIMOS 1150 7.9 1.67x10

⁵

Innovative 1535 4.01 5.88x10

⁵

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