A Modified Model for the Variation of the Capacitance above 1 MHz

Chapter 1 Introduction

1.4 A Modified Model for the Variation of the Capacitance above 1 MHz

Although the free carrier injection model [1.27]-[1.28] describes the voltage-dependence of normalized capacitance variation (∆C/C) for high-κ MIM capacitors, the reduction of ∆C/C at GHz frequencies does not agree with the

assumption of a constant relaxation time, τ. This may be due to the dipole effects. We propose a modified free-carrier injection model having a frequency dependent

[1+(f/f0)²]^-1/2 pre-factor for τ , to model the ∆C/C vs. V for high-κ MIM capacitors.

The agreement between measured and modeled ∆C/C-V data suggests that the

effective relaxation time (which dipole effects were considered) is feasible for modification of the free-carrier injection model.

The small ∆C/C variation at RF frequencies is highly desirable for high speed analog and RF circuit, while the high capacitance density for the high-κ MIM

capacitors permit further scaling down of chip sizes and reducing the cost.

Chapter 2 Research of High-κ Dielectrics

2.1 The Overview of High-κ Dielectrics Research 2.1.1 Introduction

Research activities in alternative high-κ gate dielectrics for CMOS devices have

greatly intensified in the past few years. This is due in large part to the 1997 ITRS document that projected the requirement of gate oxide thicknesses below 1 nm by the year 2012 and for 50nm device gate lengths. While considerable progress has been made, much work still remains in finding a replacement high-κ gate stack.

The replacement of SiO2 by alternative dielectrics is a formidable task and we must consider the task as an integrated task involving not only the gate dielectric but the equally important fields of interface between gate dielectric and silicon, the gate contact material and the gate dielectric. Especially important is the dielectric – silicon interface because it has very essential influences on the MOS channel mobility and driving current of MOS devices. The interfaces of the gate dielectric – silicon and gate material - gate dielectric will form interfacial layers as shown in Fig. 2-1. It will degrade the characteristics far away form the expected.

2.1.2 Motivation

The primary motivation of high-κ gate dielectrics for CMOS is the potential for

reducing the gate-to-channel tunneling current while maintaining the same induced channel conductive layer. A high-κ gate dielectric can be made physically thicker

than SiO2 for the same gate capacitance. In terms of reducing quantum tunneling current, the important material’s parameter combination is the square root of the procedure of dielectric effective mass and the barrier height and the direct product of the dielectric constant. While the barrier heights of alternative dielectrics tend to be lower than SiO2, this is more than compensated by the increased dielectric constant and thickness. At this time a wide range of alternative dielectrics have been shown to result in reduced tunneling currents for the same “equivalent” oxide thickness (EOT) and several have shown leakage current of below 1A/cm² at the 1 nm EOT value. The most promising high-κ dielectrics so far evaluated in capacitor form include the Group ⅢB oxides HfO2 and ZrO2 and Group ⅣB oxides La2O3 and Y2O3. The

aluminates and silicates of these dielectrics are also of interest, because they have higher crystallization temperature than the pure oxides and it may also be easier to obtain a good dielectric – silicon interface with these compounds. Extensive research on these dielectrics has demonstrated the promising properties of these materials with regard to near ideal C-V characteristics and low gate leakage. Several deposition methods are being pursued and have demonstrated good capacitor results including (a)

reactive ion sputtering [2.1]-[2.2], (b) physical deposition and oxidation [2.3], (c) Molecular Beam Epitaxy (MBE) [2.4], (d) Metal Organic Chemical Vapor Deposition (MOCVD) [2.5]-[2.6], (e) Low Pressure CVD (LPCVD), (f) Plasma Enhanced CVD (PECVD) [2.7]-[2.8], and (g) rapid thermal CVD. Atomic layer deposition (ALD) is also a potential long term manufacturing technique for achieving very uniform films over large areas as will be required in manufacturing.

2.1.3 Introduction of Metal Gate

Improved gate electrode materials are also essential to push to the limits of CMOS technology, because of finite depletion layer width encountered in a poly-silicon gate named poly depletion. Thus a major part of the gate stack research involves compatible gate electrode materials for the various high-κ gate dielectrics.

These problems as well as the interface problems must be researched as a combined problem to meet the ITRS CMOS requirements. Metal gate electrodes are highly desirable to eliminate poly depletion problems, however to meet threshold voltage requirements, two metals are required to replace both n⁺ and p⁺ polysilicon. While potential metals are available with appropriate work functions, most elemental metals are highly reactive not only on the potential high-κ dielectrics, but also on SiO2 as

well. However, potential metal gate materials have been identified and studied and at

present the most promising have been Ta, TaNx, and TaSixNy for an n⁺ replacement and Ru and RuO2 for a p⁺ replacement. These have been studied not only in capacitor structures, but in FET structures.

2.1.4 Effect of Interface

Another field of great importance is the electrical properties of high-κ - silicon

interface. The key parameters degrading surface mobility such as interface charges and surface roughness can not be adequately determined from capacitor structures.

The amount of interface charge which is needed to significantly degrade the surface mobility will cause a very small shift in flat band voltage as observed on capacitor structures. Now many people have a major effort in fabricating and characterizing n - channel and p – channel FETs in order to evaluate these key interface parameters.

Several device runs have shown very promising results with mobility vs. field curves approaching the values achieved with good thermal oxides. In other case, however, significant degradation in mobility has been observed due to either interface charges and/or surface roughness. By appropriately modeling the interface mobility, we can determine the major physical effects resulting in the mobility degradation.

A final field of great importance in the high-κ gate stack field is the reliability of

the gate stack under voltage and temperature stress. Since good stack results have

only recently begun to be obtained, only preliminary results are available on the potential reliability of complete high-κ gate stacks.

2.2 The Characteristics of High-κ Dielectrics 2.2.1 Introduction

Many materials systems are currently under consideration as potential

replacements for SiO2 as the gate dielectric material for sub-0.1 µm CMOS technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines foe selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these fields, but very few materials are promising with respect to all of these guidelines,

In general, high-κ dielectrics often exhibit smaller band gap, weaker bond, and

higher defect density than SiO2. Fig. 2-2 shows the comparison of relevant properties for high-κ candidates. The high-κ dielectric with the same effective oxide thickness

(EOT) with SiO2 still shows lower leakage current than SiO2 by several orders [2.9].

That is why high-κ dielectrics have drawn much attention for future technology.

Recently, some high-κ dielectrics have been widely studied and the characteristics and issues of those materials have also been reported. The high-κ

dielectrics show good performances are always accompanied by another drawbacks.

Issues to be discussed include processing, dielectric constant, capacitance, band gap, tunneling current, and reliability. Finding out the most suitable high-κ dielectrics for

the use of device and altering the device structure or process to meet the requirement of the high-speed device are significant tasks to implant high k dielectrics to the next VLSI generation.

2.2.2 Processing and Thermal Budgets of high-κ material

An ideal gate dielectric would be formed directly on silicon without reacting with the silicon and metal electrode during deposition or subsequent processing at elevated temperatures in a standard CMOS fabrication process. The reaction of the dielectric with silicon during temperature cycles subsequent to deposition is governed by thermodynamics. Hubbard and Schlom performed an extensive theoretical study of thermodynamic stability of binary oxides in contact with silicon [2.10].

Binary oxides that were shown to be thermodynamically stable on silicon included Y2O3, ZrO2, HfO2 and Al2O3. Dielectrics such as TiO2 and Ta2O5 are not thermodynamically stable on silicon and thus form an interfacial layer [2.10]-[2.11].

Interaction of the dielectric with the polysilicon or metal gate electrode is also a large

11 concern.

Although a dielectric may be thermodynamically stable in contact with silicon, an interfacial layer can still form during its deposition. Many materials that are stable on silicon, such as HfO2 and ZrO2, are efficient diffusers of oxygen so that post-deposition annealing in an oxidizing ambient can also cause the formation of an interfacial layer [2.12]. Such an interfacial layer has been identified as a silicon oxide or a silicate. It has been reported that NH3-based interfacial layer can be effective in suppressing the diffusion of O2 and the subsequent growth of silicon oxide [2.13]. In some studies it has been shown that a silicate interfacial layer can be beneficial in reducing interface trap density and improving reliability [2.14].

The formation of an interfacial oxide layer during deposition is dependent on kinetics and the relative reaction rates between the oxidation of silicon and the deposition of high-κ material, which is extremely dependent on the type of deposition

process used. Another issue with high temperature annealing is crystallization.

Although polysilicon materials may have undesired effects such as grain boundaries and roughness that impact on properties such as leakage current, it has been suggested that materials deposited in a perfectly crystalline form may be desirable [2.15].

2.2.3 Dielectric constant and capacitance

Approximate κ values for some representative gate dielectrics are shown in Fig.

2-2. These values of κ are very approximate because of the stacked nature of many of the films and of the close relationship of κ to properties such as crystallite and composition that are difficult to measure accurately. Many times, the κ of a bulk crystal is measured and used for the κ of a thin amorphous film of the material.

The capacitance density of a film depends not only on the κ and thickness of the

material but also on that of an interfacial oxide layer. Fig. 2-3 shows equivalent oxide

thickness for a stacked dielectric comprised of a layer of SiO2 and a layer of a high- κ dielectric. EOT is the equivalent thickness of SiO2 that would produce the same capacitance-voltage curve as that obtained from an alternate dielectric system.

Dielectrics having EOTs as small as 1.0 nm have been developed. In order to achieve small EOTs, the interfacial oxide thickness must be controlled. The κ of the interfacial

layer present in many dielectrics has been determined to be higher than that of pure SiO2, presumably due to the presence of metal in the interfacial layer [2.11] or silicate formation [2.3].

2.2.4 Bandgap and Tunneling Current

Approximate bandgaps for some of the candidate high-κ gate dielectrics are also

shown in Fig.2-2. Although bandgap is sometimes determined using optical

measurements, the bandgap measured electrically may be different than that measured optically because optical transitions are almost exclusively direct. The electron tunneling current flowing through a dielectric depends not only on bandgap but on barrier height. Although a material may have a large bandgap, the conduction band offset between materials may be small [2.16]. Electrical bandgap tends to decrease with increasing κ resulting in tradeoffs associated with the tunnel current [2.16].

Results also suggest that it is more beneficial to have a material with a lower κ

and a barrier height slightly larger than the expected supply voltage, than to have a material with a larger κ and a lower barrier height. This is due to the tunneling current

being proportional to the area of the tunnel barrier which depends on the thickness of the material and its barrier height.

For gate dielectric stacks, modeling results indicate that the tunnel current depends strongly on injection polarity due to the asymmetry of the band diagram.

Also, an interfacial oxide layer can significantly increase the tunneling current if the electrons tunnel through the oxide layer first [2.17].

Although much of the modeling of current through high-κ dielectrics assumed

pure tunneling as the mechanism, most dielectrics exhibit some form of trap-assisted current [2.18]. As an example, Fig. 2-4 shows the temperature dependence of leakage current for a PECVD nitride film. The nitride film exhibits the temperature

dependence stronger than that expected for pure tunneling, but weaker than the expected for Frenkel-Poole transport, which may suggest the trap-assisted phenomena.

2.3 The Choice of High-κ Dielectrics 2.3.1 Introduction

New high-κ materials that have been extensively discussed range from simple

metal oxides like TaOx and TiOx that benefit from ease of processing to more complex materials such as (Ba,Sr)TiO3 that have a higher dielectric constant but also present greater processing challenges. Here we extend the scope of materials considered to include new classes of mixed metal oxides that combine the improved dielectric properties of binary and ternary systems with the ease of processing of simple metal oxides. Some of the most exciting materials we have discovered include Ta-Al-O alloys for gate oxides, and we also use it for metal-insulator-metal capacitors.

Amorphous TaOx has been used previously [2.19] to extend the scaling of SiO2, but been found to crystallize during the rapid thermal anneals (RTA) used for dopant activation and interface state passivation in Si. The crystallites have lateral dimensions comparable to the gate length which can result in excessive surface roughness and fluctuations in threshold voltage. This crystallization transition also

results in excessive growth of SiO2 at the a-TaOx/Si (a-TaOx: amorphous TiOx) and the a-TaOx/poly-Si interface (Fig. 2-5) and can lead to deterioration of the gate capacitance (Fig. 2-6).

We have found that the crystallization transition can be suppressed by adding Al or Si to the a-TaOx film, as shown in Fig. 2-7. The electrical properties of Ta1-yAlyOx

for 0.1 < y < 0.4 are superior to those of undoped TaOx (Fig. 2-8) although the dielectric constant is can be reduced (Fig. 2-9). The concentrations of Al required to improve the thermal stability and electrical properties should not significantly effect the dielectric constant.

Fig. 2-1. Schematic of important regions of a field effect transistor gate

stack [2.20].

Fig. 2-2. Comparison of relevant properties for high-κ candidates [2.20].

Fig. 2-3. EOT for a stacked dielectric comprised of a high-κ dielectric

and SiO

[2.21].

Fig. 2-4. Gate current density for a film at several measurement

temperatures [2.21].

Fig. 2-5. TEM cross section of 7 nm Ta

₂

O

₅

on silicon. The 2.0 nm film is

a SiTa

O

interfacial region [2.22].

Fig. 2-6. Reduction of gate capacitance due to formation of SiO

₂

interfacial layer after 800

C crystallization [2.22].

Fig. 2-7. Crystallization temperature of Ta-M-O as a function of Al, Si, or

Ge content. A very strong increase in T

with Al content is

observed [2.22].

Fig. 2-8. Current-voltage relations for Ta-Al-O showing the improvement

of electrical properties of Ta

O

with addition of Al [2.22].

Fig. 2-9. Dielectric constant of Ta-Al-O as a function of Al concentration

in the sputtered films [2.22].

Chapter 3 Experimental Procedure of High-κ MIM Capacitor with Al doped TaO

Dielectrics

3.0 Microwave Layout Rules for On-wafer Measurement

Mechanical

1. GSG Configuration

Metal pads must be laid out with ground-signal-ground (GSG) probe configuration as shown in Fig. 3-1.

2. Pad Pitch：

All pads contacted by an individual probe must be collinear with a constant center-to-center pad pitch of 150 µm as shown in Fig. 3-2.

3. Pad Size

The minimum pad size is 50µm × 50 µm as shown in Fig. 3-2.

4. Passivation Window

The minimum passivation window size is 96µm × 96 µm. The passivation window

must be larger than the probe contact. If the pad metalization is above the final passivation layer, this rule does not apply.

5. Parallel-Row Pad Spacing

The minimum center-to-center pad spacing between facing probes is 150 µm as shown in Fig. 3-2. Note that this spacing is based on the assumption of 750 µm of

probe vertical overtravel.

6. Pad Height Variation

The minimum pad height variation in a row of pads contacted by one probe is 0.5 µm.

7. Planarity Requirements

The maximum overall planar deviation of a row of pads contacted by one probe, with respect to the backside of the substrate is 2/1000.

Electrical

Maximum Rated Current

The maximum dc current in port 1 is 0.1 ampere while that in port 2 is 0.5 ampere and the maximum dc current per contact is 0.5 ampere.

3.1 The Fabrication Process Flow of Al doped TaO

MIM Capacitors

The MIM capacitors were fabricated using 4-in p-type or n-type Si wafers. To integrate the high-κ capacitors into VLSI backend process, we started with 500 nm

isolation oxide deposition on Si wafers by Wet Oxide furnace. The bottom electrode of MIM capacitor was formed by Electron-gun (E-gun) on the isolation oxide using Pt/Ti (Pt/Ti = 90nm/10nm) bi-layer metals as shown in Fig. 3-3. The bottom electrode

was also patterned using Lift-off technology to form the coplanar transmission line for RF measurement. A plasma-enhanced chemical vapor deposition (PECVD) passivation oxide was deposited for isolation and followed by patterning the active capacitor region as shown in Fig. 3-4. Then high-κ Al doped TaOx was formed by

depositing Al and Ta (Al:Ta = 1:8) metals on Pt electrode followed by oxidation at 400 ^oC [3.1] for 45 min and subsequent annealing for 15 min. The above process fits well the low thermal budget requirement of current VLSI backend integration.

Various different thicknesses from 11.5 to 25.5 nm are formed and confirmed by ellipsometer measurement. The reason for doping AlOy into TaOz is to preserve the merit of good MIM capacitor integrity by adding Al2O3 dielectric. Addition of Al2O3

[3.2]to Ta2O5 reduces the leakage current, although this results in a slightly lower κ-value [3.3]-[3.4]. Then via hole was patterned shown in Fig. 3-5. Finally, Al metal was deposited on high-κ dielectrics followed by patterning to form the top electrode

of MIM capacitor and coplanar transmission line for RF measurements shown in Fig.

3-6. The typical MIM capacitor area is 50 µm × 50 µm. Fig. 3-7 and Fig. 3-8 show the

MIM capacitor cross-section view and layout view, respectively.

The detailed fabrication process flow is listed as follows：

1. (100) orientation n-type or p-type Si wafer.

2. Initial cleaning (RCA clean).

3. Thermal wet oxidation at 1036 ^oC to grow 500 nm thermal SiO2 in furnace.

4. Depositing Pt/Ti (Pt/Ti = 90nm/10nm) bi-layer metals, Ti first, by E-gun, then employing Lift-off technology.

5. A PECVD passivation oxide 100nm was deposited for isolation and followed by patterning the active capacitor region.

6. Then high-κ Al doped TaOx was formed by depositing Al and Ta (Al:Ta = 1:8)

metals on Pt electrode.

7. Following by oxidation at 400 ^oC for 45 min and subsequent annealing for 15 min in furnace.

8. Then via hole was patterned.

9. Finally, Al metal was deposited on high-κ dielectrics by thermal coater followed by

patterning to form the top electrode of MIM capacitor and coplanar transmission line.

3.2 The Measurement of Al doped TaO

MIM Capacitors

The high-κ MIM capacitors were characterized using an HP4284A precision

LCR meter from 10 KHz to 1 MHz. Above 1 MHz the S-parameters (Fig. 3-9) were measured using an HP8510C network analyzer (from 200 MHz to 20 GHz).

Additional “OPEN” dummy device [3.5] shown in Fig. 3-10 were measured to

de-embed the parasitic capacitance in the RF layout of the MIM capacitor. A similar method was used for RF noise analysis in 0.18 to 0.13 µm MOSFETs [3.6]. So the

measured S-parameters were de-embedded from a dummy device and the RF frequency capacitance plus parasitic parameters were extracted using an equivalent circuit model shown in Fig. 3-11. The parasitic pad, series inductor and resistor in transmission line are de-embedded from a same line length through transmission line [3.7]-[3.8].

3.3 De-embedding Theory

When circuits or devices work at high frequencies, many parasitic effects will happen. For example, a signal applied on one metal line, the potential of this metal line at any point is equal if the wavelength of signal is long enough, compared with metal line. But the potential of the metal line at any potential will be different when the wavelength of signal can compare with the metal line or shorter, i.e. high frequency signal. Hence, a metal line was regarded as a resistor at low frequency or resistor plus parasitic inductance and capacitance parameters at high frequency in an equivalent circuit model. In order to measure this MIM capacitance, we must layout additional probe pads and signal lines for measurement. However, these added potions will generate additional parasitic effects. So we must de-embed these parasitic

parameters to get the intrinsic high frequency capacitance. Fig. 3-12 shows the equivalent circuit of a RF MIM capacitor device at high frequency.

As devices were measured approach microwave frequency, we can not directly measure the lump circuit components, like RLC (resistance, inductance and capacitance), because of parasitic effects. Scattering-parameters (S-parameters) were

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