The Characteristics of High-κ Dielectrics

Many materials systems are currently under consideration as potential

replacements for SiO2 as the gate dielectric material for sub-0.1 µm CMOS technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines foe selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these fields, but very few materials are promising with respect to all of these guidelines,

In general, high-κ dielectrics often exhibit smaller band gap, weaker bond, and

higher defect density than SiO2. Fig. 2-2 shows the comparison of relevant properties for high-κ candidates. The high-κ dielectric with the same effective oxide thickness

(EOT) with SiO2 still shows lower leakage current than SiO2 by several orders [2.9].

That is why high-κ dielectrics have drawn much attention for future technology.

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Recently, some high-κ dielectrics have been widely studied and the characteristics and issues of those materials have also been reported. The high-κ

dielectrics show good performances are always accompanied by another drawbacks.

Issues to be discussed include processing, dielectric constant, capacitance, band gap, tunneling current, and reliability. Finding out the most suitable high-κ dielectrics for

the use of device and altering the device structure or process to meet the requirement of the high-speed device are significant tasks to implant high k dielectrics to the next VLSI generation.

2.2.2 Processing and Thermal Budgets of high-κ material

An ideal gate dielectric would be formed directly on silicon without reacting with the silicon and metal electrode during deposition or subsequent processing at elevated temperatures in a standard CMOS fabrication process. The reaction of the dielectric with silicon during temperature cycles subsequent to deposition is governed by thermodynamics. Hubbard and Schlom performed an extensive theoretical study of thermodynamic stability of binary oxides in contact with silicon [2.10].

Binary oxides that were shown to be thermodynamically stable on silicon included Y2O3, ZrO2, HfO2 and Al2O3. Dielectrics such as TiO2 and Ta2O5 are not thermodynamically stable on silicon and thus form an interfacial layer [2.10]-[2.11].

Interaction of the dielectric with the polysilicon or metal gate electrode is also a large

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Although a dielectric may be thermodynamically stable in contact with silicon, an interfacial layer can still form during its deposition. Many materials that are stable on silicon, such as HfO2 and ZrO2, are efficient diffusers of oxygen so that post-deposition annealing in an oxidizing ambient can also cause the formation of an interfacial layer [2.12]. Such an interfacial layer has been identified as a silicon oxide or a silicate. It has been reported that NH3-based interfacial layer can be effective in suppressing the diffusion of O2 and the subsequent growth of silicon oxide [2.13]. In some studies it has been shown that a silicate interfacial layer can be beneficial in reducing interface trap density and improving reliability [2.14].

The formation of an interfacial oxide layer during deposition is dependent on kinetics and the relative reaction rates between the oxidation of silicon and the deposition of high-κ material, which is extremely dependent on the type of deposition

process used. Another issue with high temperature annealing is crystallization.

Although polysilicon materials may have undesired effects such as grain boundaries and roughness that impact on properties such as leakage current, it has been suggested that materials deposited in a perfectly crystalline form may be desirable [2.15].

2.2.3 Dielectric constant and capacitance

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Approximate κ values for some representative gate dielectrics are shown in Fig.

2-2. These values of κ are very approximate because of the stacked nature of many of the films and of the close relationship of κ to properties such as crystallite and composition that are difficult to measure accurately. Many times, the κ of a bulk crystal is measured and used for the κ of a thin amorphous film of the material.

The capacitance density of a film depends not only on the κ and thickness of the

material but also on that of an interfacial oxide layer. Fig. 2-3 shows equivalent oxide

thickness for a stacked dielectric comprised of a layer of SiO2 and a layer of a high- κ dielectric. EOT is the equivalent thickness of SiO2 that would produce the same capacitance-voltage curve as that obtained from an alternate dielectric system.

Dielectrics having EOTs as small as 1.0 nm have been developed. In order to achieve small EOTs, the interfacial oxide thickness must be controlled. The κ of the interfacial

layer present in many dielectrics has been determined to be higher than that of pure SiO2, presumably due to the presence of metal in the interfacial layer [2.11] or silicate formation [2.3].

2.2.4 Bandgap and Tunneling Current

Approximate bandgaps for some of the candidate high-κ gate dielectrics are also

shown in Fig.2-2. Although bandgap is sometimes determined using optical

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measurements, the bandgap measured electrically may be different than that measured optically because optical transitions are almost exclusively direct. The electron tunneling current flowing through a dielectric depends not only on bandgap but on barrier height. Although a material may have a large bandgap, the conduction band offset between materials may be small [2.16]. Electrical bandgap tends to decrease with increasing κ resulting in tradeoffs associated with the tunnel current [2.16].

Results also suggest that it is more beneficial to have a material with a lower κ

and a barrier height slightly larger than the expected supply voltage, than to have a material with a larger κ and a lower barrier height. This is due to the tunneling current

being proportional to the area of the tunnel barrier which depends on the thickness of the material and its barrier height.

For gate dielectric stacks, modeling results indicate that the tunnel current depends strongly on injection polarity due to the asymmetry of the band diagram.

Also, an interfacial oxide layer can significantly increase the tunneling current if the electrons tunnel through the oxide layer first [2.17].

Although much of the modeling of current through high-κ dielectrics assumed

pure tunneling as the mechanism, most dielectrics exhibit some form of trap-assisted current [2.18]. As an example, Fig. 2-4 shows the temperature dependence of leakage current for a PECVD nitride film. The nitride film exhibits the temperature

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dependence stronger than that expected for pure tunneling, but weaker than the expected for Frenkel-Poole transport, which may suggest the trap-assisted phenomena.

2.3 The Choice of High-κ Dielectrics