Chapter 5 A PVT Robust Dual-Edged Triggered Explicit-Pulsed Level Converting
5.3 Performance Comparisons
5.3.4 Monte Carlo Simulation- Data Error Rate
Fig. 5.23 presents 5000-point Monte Carlo simulations of the data error rate with different input voltage. Monte Carlo simulation demonstrates how the process variations affect the LCFF characteristics. For the flip-flops, storing the right input
99
data is very critical. From the simulation result, our work has a data error rate of zero when the input voltage is above 0.4V. It is proven that the proposed DETEP-LCFF is more stable than other three DETEP-LCFFs when operated in a input voltage as low as the near-threshold region. The other three LCFFs is suitable for the super-threshold region operation.
0.3 0.4 0.5 0.6 0.7 0.8 0.0
0.2 0.4 0.6 0.8
1.0 This work
[5.8]
[5.9]
[5.10]
D a ta e rr o r ra te ( % )
VDDL (V)
Figure 5.23. Monte Carlo simulation of data error rate
5.4 Conclusions
A power-delay-product optimized and robust dual-edged triggered explicit-pulsed level converting flip-flop is presented. By combining energy-efficient techniques, the power dissipation of this work is decreased by 52%. The clock pulse generator has a symmetric clock pulses at both of the clock edge and provides a sharing technique. The performance summary of the proposed dual-edged triggered explicit-pulsed level converting flip-flop is given in Table 5.2. The performance comparisons with [5.8]-[5.9] are listed in Table I. This work provides a wide operation range, from 0.4V to 1V across five process corners. When the input voltage is 0.4V, it can achieve a minimum D-Q delay of 781ps, a setup time of -610ps and consume only
100
2.3μW. It is suitable to be the interface of two different voltage domains in emerging dynamic voltage frequency scaling wireless applications.
15 um
5.1 um
Clock pulse generator DCVSPG latch
Figure 5.24 Layout view of the proposed DETEP LCFF.
Table 5.2. Performance summary of the proposed DETEP-LCFF
VDDL Setup time (ps) Hold time (ns) Min. D-Q delay (ps)
Power (μW) PDP (fJ)
0.4V -610 1.1 781 2.30 1.80
0.5V -140 0.34 424 2.80 1.19
0.6V -70 0.18 393 3.58 1.41
0.7V -40 0.12 407 4.68 1.91
101
Chapter 6
Conclusion and Future Work
6.1 Conclusion
A wide range DLL-based multiphase clock generator is proposed. The operating range is from 80 MHz to 500MHz. With the proposed harmonic detection circuit, the proposed multiphase clock generator is free from the harmonic problem. The delay block controller has the dual modes- SAR mode and counter mode. The SAR mode helps to accelerate the lock in speed and the counter mode keeps the proposed work tacking the environmental variations when finishing the SAR search. When the input voltage and frequency are 1.0V and 500MHz, the power consumption is 0.29mW.
With the proposed duty cycle corrector, the clock signal has a 50% duty cycle. The proposed duty cycle can be operated as low as 0.5V. The correction range is from 25%
to 75%. The operation range is 100MHz to 500MHz. With the PVT detection, the output duty cycle error can be reduced up to 17%. When the input voltage and frequency are 0.5V and 167MHz, the power consumption is 26.30 μW.
A power-delay-product optimized and robust level converter is presented for sub-threshold to super-threshold signal converting. By combining energy-efficient techniques, PDP value of this work is decreased by 23%. Temperature induced variation on propagation delay is reduced up to 99%. This work provides a wide operation range, from 150mV to 1V across five process corners. When the input voltage is 150mV, it can achieve a propagation delay of 52ns and consume only 21nW.
102
A PVT robust dual-edged triggered explicit-pulsed level converting flip-flop is presented. By combining energy-efficient techniques, the power dissipation of this work is decreased by 52%. The clock pulse generator has a symmetric clock pulses at both of the clock edge and provides a sharing technique. When the input voltage is 0.4V, it can achieve a minimum D-Q delay of 781ps, a setup time of -610ps and consume only 2.3μW. It is suitable to be the interface of two different voltage domains in emerging dynamic voltage frequency scaling wireless applications.
6.2 Future Work
System heterogeneity offered by 3D integration usually requires different supply voltages for different function blocks, ranging from high (3.3V or higher) to ultra-low (sub-threshold operation) voltages. The multiple voltages requirement can be achieved by adopting the proposed DVFS system, shown in Fig. 6.1. The first layer signal TSVs are connected to clock source. The clock signal passes through TSVs to the different layers. In each layer, the proposed DLL-based clock generator produces the multiple frequency to meet each layer requirement. The clock drivers are followed by the proposed duty cycle corrector. The proposed level converters or level converting flip-flops are inserted between the different voltage domain.
103
DLL
ref-clk CDR CDR
DLL-based clock generator
DVFS system Level converter/
Level converting flip-flop
V1
V2
Duty cycle corrector
Figure 6.1. 3DIC application.
104
Bibliography
Chapter 1.
[1.1] S. K. Gupta, A. Raychowdhury, and K. Roy, “Digital computation in subthreshold region for ultralow-power operation: a device-circuit-architecture codesign perspective,” Proceeding of the IEEE, vol.98, no.2, pp.160-190, Feb.
2010.
[1.2] J.-C. Chi, H.-H. Lee, S.-H. Tsai, and M.-C. Chi, “Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint” IEEE Transactions on Very Large Scale Integration Systems, Vol.
15, No. 6, pp.637-648, June 2007.
[1.3] M. E. Salehi, M. Samadi, M. Najibi, A. Afzali-Kusha, M. Pedram, and S.M.
Fakhraie, “Dynamic Voltage and Frequency Scheduling for Embedded Processors Considering Power/Performance Tradeoffs, ” IEEE Transactions on Very Large Scale Integration Systems, vol.19, no.10, pp.1931-1935, Oct.
2011.
105
Chapter 2.
[2.1] J. Masuch and M. Delgado-Restituto, “A 350 µW 2.3 GHz integer-N frequency synthesizer for body area network applications, ” IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp.105-108, Jan. 2011.
[2.2] K.-H. Cheng, Y.-C. Tsai, Y.-L. Lo, and J.-S. Huang , “A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip, ” IEEE Transactions on Circuits and Systems I: Regular Papers , vol.58, no.5, pp.849-859, May 2011.
[2.3] D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori, and A. L. Lacaita,
“A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560fsrms Integrated Jitter at 4.5-mW Power, ” IEEE Journal of Solid-State Circuits, , vol.46, no.12, pp.1-14, Dec. 2011.
[2.4] C. Jaehyouk, S. T. Kim, W. Kim, K.-W. Kim, K. Lim, and J. Laskar , “A Low Power and Wide Range Programmable Clock Generator With a High Multiplication Factor, ” IEEE Transactions on Very Large Scale Integration Systems, vol.19, no.4, pp.701-705, April 2011.
[2.5] J. Moon and H.-Y. Lee, “A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs, ” IEEE International Symposium on Circuits and Systems, pp.313-316, May 2011.
[2.6] J. Sungchun, H. Song, S. Ye, and D.-K. Jeong, “A 13.8mW 3.0Gb/s clock-embedded video interface with DLL-based data-recovery circuit, ” IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp.450-452, Feb. 2011.
[2.7] Chaodong Ling, Miaoyi Luo, and Mengzhang Cheng, “A Low Noise CMOS Phase Locked Loop,” IEEE International Conference of Anti-counterfeiting, Security, and Identification In Communication, pp.343-346, Aug. 2009.
[2.8] Jiwie Huang, Liang Tao, and Zhengpin Li, “A Low-Jitter and Low-Power Clock Generator,” IEEE International Coneference on Solid-State and Integrated Circuit Technology, pp. 385-387, Nov. 2010.
[2.9] D. J. Foley and M. P. Flynm, “CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator, ” IEEE Journal of Solid-State Circuits, vol.36, no.3, pp.417-423, March 2001.
106
[2.10] G. Chien and P. R. Gray, “A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications, ” IEEE Journal of Solid-State Circuits, vol.35, no.12, pp.1996-1999, Dec 2000.
[2.11] W.-M. Lin, C.-C. Chen, and S.-I. Liu, “An all-digital clock generator for dynamic frequency scaling, ” International Symposium on VLSI Design, Automation and Test, pp.251-254, April 2009.
[2.12] C.-K. Liang, R.-J. Yang, and S.-I. Liu, “An All-Digital Fast-Locking Programmable DLL-Based Clock Generator, ” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55, no.1, pp.361-369, Feb. 2008.
[2.13] M. Faisal, and M. A. Bayoumi, “A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers, ” IEEE International Symposium on Circuits and Systems, pp.1460-1463, May 2008.
[2.14] J. Koo, S. Ok, and C. Kim, “A Low-Power Programmable DLL-Based Clock Generator With Wide-Range Antiharmonic Lock, ” IEEE Transactions on Circuits and Systems II: Express Briefs, vol.56, no.1, pp.21-25, Jan. 2009.
[2.15] P.-C. Huang, C.-J. Shih, Y.-C. Tsai, and K.-H. Cheng, “A phase error calibration DLL with edge combiner for wide-range operation, ” IEEE International New Circuits and Systems Conference, pp.1-4, June 2011.
[2.16] C.-S. Hwang, P. Chen, and H.-W. Tsao, “A wide-range and fast-locking clock synthesizer IP based on delay-locked loop, ” IEEE Proceedings of the International Symposium on Circuits and Systems , pp. 785-7888, May 2004.
[2.17] G.-Y. Wei, J. T. Stonick, D. Weinlader, J. Sonntag, and S. Searles, “A 500MHz MP/DLL clock generator for a 5Gb/s backplane transceiver in 0.25μm CMOS, ” IEEE International Digest of Technical Papers Solid-State Circuits Conference, vol.1, pp. 464- 465, 2003.////////////////////////////////////
[2.18] R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, and J. Poulton, “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips, ” IEEE Journal of Solid-State Circuits, vol.37, no.12, pp. 1804- 1812, Dec 2008.
[2.19] M. Combes, K. Dioury, and A. Greiner, “A portable clock multiplier generator using digital CMOS standard cells, ” IEEE Journal of Solid-State Circuits, vol.31, no.7, pp.958-965, July 1996.
107 Deskew Buffer With Duty-Cycle Correction, ” IEEE Transactions on Very Large Scale Integration Systems, no.99, pp.1-11, Feb. 2012.
[2.23] J.-W. Ke, S.-Y. Huang, and D.-M. Kwai, “A high-resolution all-digital duty-cycle corrector with a new pulse-width detector, ” IEEE International Conference of Electron Devices and Solid-State Circuits, pp.1-4, Dec. 2010.
[2.24] S.-K. Kao and S.-I. Liu, “A Wide-Range All-Digital Duty Cycle Corrector with a Period Monitor, ” IEEE Conference on Electron Devices and Solid-State Circuits, pp.349-352, Dec. 2007.
[2.25] Y.-M. Wang, J.-T. Yu; Y. Surya, and C.-H. Huang, “A compact delay-recycled clock skew-compensation and/or duty-cycle-correction circuit, ” IEEE International SOC Conference, pp.42-47, Sept. 2011.
[2.26] J. Gu, J. Wu, D. Gu, M. Zhang, and L. Shi, “All-Digital Wide Range Precharge Logic 50% Duty Cycle Corrector, ” IEEE Transactions on Very Large Scale Integration Systems, vol.20, no.4, pp.760-764, April 2012
[2.27] D. Shin, J. Song, H. Chae, K.-W. Kim, Y.-J. Choi, and C. Kim, “A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC, ” IEEE Journal of Solid-State Circuits, vol.44, no.9, Corrector, ” International Symposium on VLSI Design, Automation and Test, pp.1-4, April 2006.
108
[2.30] Y.-J. Min, C.-H. Jeong, K.-Y. Kim, W.- H. Choi, J.-P. Son, C. Kim, and S.-W.
Kim, “A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications, ” IEEE Transactions on Very Large Scale Integration Systems, , vol.20, no.8, pp.1524-1528, Aug.
2012.
[2.31] K.-S. Song, C.-H. Koo, N.-K. Park, K.-W. Kim, Y.-J. Choi, J.-H. Ahn, and B.-T. Chung, “A single-loop DLL using an OR-AND duty-cycle correction technique, ” IEEE Asian Solid-State Circuits Conference, pp.245-248, Nov.
2008.
[2.32] P. Chen, S.-W. Chen, and J.-S. Lai, “A low power wide range duty cycle corrector based on pulse shrinking/stretching mechanism, ” IEEE Asian Solid-State Circuits Conference, pp.460-463, Nov. 2007.
[2.33] K.-H. Cheng, C.-W. Su, and K.-F. Chang, “A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation, ” IEEE Journal of Solid-State Circuits, vol.43, no.2, pp.399-413, Feb. 2008.
[2.34] H. Soeleman and K. Roy, “Ultra-low power digital subthreshold logic circuits, ” Proceeding of International Symposium on Low Power Electronics
and Design, pp. 94-96, 1999.
[2.35] M. Hamada, M. Takahashi, H. Arakida, A. Chiba, T. Terazawa, T. Ishikawa, M.
Kanazawa, M. Igarashi, K. Usami, and T. Kuroda, “A Top-Down Low Power Design Technique Using Clustered Voltage Scaling With Variable Supply-Voltage Scheme,” Proceeding of IEEE Custom Integrated Circuits Conference, pp. 495-498, May 1998.
[2.36] A .Chavan and E. MacDonald, “Ultra Low Voltage Level Shifters to Interface Sub and Super Threshold Reconfigurable Logic Cells, ” IEEE Aerospace Conference, pp.1-6, March 2008.
[2.37] B. Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M.
Minuth, R. Helfand, T. Austin, D. Sylvester, and D. Blaauw,
“Energy-Efficient Subthreshold Processor Design, ” IEEE Transactions on Very Large Scale Integration Systems, vol.17, no.8, pp.1127-1137, Aug. 2009.
109
[2.38] I.- J. Chang, J.-J. Kim, and K. Roy, “Robust Level Converter Design for Sub-threshold Logic, ” Proceedings of the 2006 International Symposium on Low Power Electronics and Design, pp.14-19, Oct. 2006 .
[2.39] H. Shao and C.-Y. Tsui , “A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic, ” European Solid State Circuits Conference, pp.312-315, Sept. 2007. voltage level shifter with built-in short circuit current reduction, ” European Conference on Circuit Theory and Design, pp.142-145, Aug. 2011.
[2.42] A. Hasanbegovic and S. Aunet, “Low-power subthreshold to above threshold level shifter in 90 nm process, ” NORCHIP, pp.1-4, Nov. 2009.
[2.43] S. L tkemeier and . R ckert, “A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror, ” IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, no.9, pp.721-724, Sept. 2010.
[2.44] M. Ashouei, H. Luijmes, J. Stuijt, and J. Huisken, “Novel wide voltage range level shifter for near-threshold designs, ” IEEE International Conference on Electronics, Circuits, and Systems , pp.285-288, Dec. 2010.
[2.45] I-. J. Chang, J.-J. Kim, K.-J. Kim and K. Roy, “Robust Level Converter for Sub-Threshold/Super-Threshold Operation:100 mV to 2.5 V, ” IEEE Transactions on Very Large Scale Integration Systems, vol.19, no.8, pp.1429-1437, Aug. 2011.
[2.46] B. Zhang, L. Liang, and X. Wang, “A New Level Shifter with Low Power in Multi-Voltage System, ” International Conference on Solid-State and Integrated Circuit Technology, pp.1857-1859, 2006.
[2.47] K.-H. Koo, J.-H. Seo, M.-L. Ko, and J.-W. Kim, “A new level-up shifter for high speed and wide range interface in ultra deep sub-micron, ” IEEE International Symposium on Circuits and Systems, vol.2, pp. 1063- 1065, May 2005.
110
[2.48] Y.-S. Lin and D.M. Sylvester, “Single stage static level shifter design for subthreshold to I/O voltage conversion, ” IEEE International Symposium on Low Power Electronics and Design, pp.197-200, 11-13 Aug. 2008.
[2.49] A. Chandrakasan, S. Sheng, and R.W. Brodersen, “Low-Power CMOS Digital Design,” IEEE Journal of Solid-State Circuits, vol. 27, pp.473-484, Apr. 1992.
[2.50] F. Ishihara, F. Sheikh, and B. Nikolic, “Level Conversion for Dual-Supply Systems,” IEEE Transactions on Very Large Scale Integration Systems, vol.12, no.2, pp. 185-195, Feb. 2004.
[2.51] M. M. Hamid and K. Roy, “Self-Precharging Flip-Flop: A New Level Converting Flip-Flop,” Proceedings of European Slid-State Circuits Conference, pp. 407-410, Sept. 2002.
[2.52] B.-S. Kong, S.-S. Kim, and Y.-H. Jun, “Conditional-Capture Flip-Flop for Statistical Power Reduction,” IEEE Journal of Solid-Sate Circuits, vol.36, no.8, pp. 1263-1271, Aug. 2001.
[2.53] N. Nedovic and V. G. Oklobdzija, “Dual-Edged Triggered Storage Elements and Clocking Strategy for Low-Power Systems, ” IEEE Transactions on Very Large Scale Integration Systems, vol.13, no.5, pp. 577-590, May 2005.
[2.54] H. S. Park, H. B. Che, W. Kim, and Y. H. Kim, “High Performance Level-Converting Flip-Flop with a Simple Pulse Generator and a Fast Latch,”International Technical Conference on Circuits/Systems, Computer and Communications, pp. 561-564, 2008.
[2.55] P. Zhao, G. P. Kumar, C. Archana, and M. Bayoumi, “A Double-Edge Implicit-Pulsed Level Convert Flip-Flop, ” Proceedings of IEEE Symposium on Computer society Annual, pp. 141- 144, Feb. 2004.
[2.56] P. Zhao, J.B. McNeely, P.K. Golconda, S. Venigalla, N. Wang, M.A. Bayoumi, W. Kuang, and L. Downey, “Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems, ” IEEE Transactions on Very Large Scale Integration Systems, , vol.17, no.9, pp.1196-1202, Sept. 2009 [2.57] L.-Y. Chiou and S.-C. Lou, “An Energy-Efficient Dual-Edge Triggered
Level-Converting Flip-Flop, ” IEEE International Symposium on Circuits and Systems, pp.1157-1160, May 2007.
[2.58] L.-Y. Chiou and S.-C. Luo, “Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to
111
Output Parasitics,” IEEE Transactions on Very Large Scale Integration Systems, , vol.17, no.11, pp.1659-1663, Nov. 2009.
[2.59] H. Mahmoodi-Meimand and K. Roy, “Dual-edge triggered level converting flip-flops, ” Proceedings of International Symposium on Circuits and Systems , vol.2, pp. 661-664 , May 2004.
[2.60] A.-S. Seyedi and A. Afzali-Kusha, “Double-edge Triggered Level Converter Flip-Flop with Feedback, ” International Conference on Microelectronics, pp.44-47, Dec. 2006.
[2.61] Q.-X. Wang, Y.-S. Xia, and L.-Y. Wang, “Dual-Vth based double-edge explicit-pulsed level-converting flip-flops, ” International Conference on Electronics, Communications and Control , pp.837-840, Sept. 2011.
112
Chapter 3.
[3.1] A. Shibayama, K. Nose, Sunao Torii, M. mizuno, and M. Edahiro,
“Skew-Tolerant global synchronization based on periodically al-in-phase clocking for Multi-Core SOC platforms,” IEEE Symposium on VLSI Circuits, pp.158-159, June 2007.
[3.2] J.-H. Kim, Y.-H. Kwak, M.-Y. Kim, S.-W. Kim, and C. Kim, “A 120MHz-1.8GHz CMOS DLL-Based clock generator for dynamic frequency scaling,” IEEE Journal of Solid-State Circuits, vol.41, no.9, pp.2077-2082, Sept. 2006.
[3.3] W.-M. Lin, C.-C. Chen, and S.-I. Liu, “An All-Digital Clock Generator for Dynamic Frequency Scaling,” International Symposium on VLSI Design, Automation and Test, pp.251-254, April 2009.
[3.4] Sunghwa Ok, Kyunghoon Chung, Jabeom Koo, and Chulwoo Kim, “An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling, ” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, no.7, pp.1130-1134, July 2010.
[3.5] P.-K. Hanumolu, G.-Y. Wei, and U.-K. Moon, “A Wide-Tracking Range Clock and Data Recovery Circuit, ” IEEE Journal of Solid-State Circuits, vol.43, no.2, pp.425-439, Feb. 2008.
[3.6] C.-C. Chung, P.-L. Chen, and C.-Y. Lee, “An All-Digital Delay-Locked Loop for DDR SDRAM Controller Applications,” International Symposium on VLSI Design, Automation and Test, pp.1-4, April 2006.
[3.7] R.-J.Yang and S.-I. Liu, “A 40–550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm, ” IEEE Journal of Solid-State Circuits, vol.42, no.2, pp.361-373, Feb. 2007.
[3.8] Y.-J. Jeon, J.-H. Lee, H.-C. Lee, K.-W. Jin, K.-S. Min, J.-Y. Chung, H.-J. Park,
113
“A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs, ” IEEE Journal of Solid-State Circuits, vol.39, no.11, pp. 2087- 2092, Nov. 2004.
[3.9] H. Sutoh, K. Yamakoshi, M. Ino, “Circuit technique for skew-free clock distribution, ” Proceedings of the IEEE Custom Integrated Circuits Conference, pp.163-166, May 1995.
[3.10] C.-C. Chung and C.-Y. Lee, “A New DLL-Based Approach for All-Digital Multiphase Clock Generation,” IEEE Journal of Solid-State Circuits, vol. 39, no.3, pp. 469–475, March 2004.
[3.11] G.-K. Dehng, J.-M. Hsu, C.-Y. Yang, and S.-I. Liu, “Clock-deskew buffer using a SAR-controlled delay-locked loop, ” IEEE Journal of Solid-State Circuits,vol.35, no.8, pp.1128-1136, Aug. 2000
[3.12] C.-K. Liang, R.-J. Yang, and S.-I. Liu, “An All-Digital Fast-Locking Programmable DLL-Based Clock Generator, ” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.55, no.1, pp.361-369, Feb. 2008.
[3.13] s.-K. Kao and S.-I. Liu, “All-Digital Fast-Locked Synchronous Duty-Cycle Corrector, ” IEEE Transactions on Circuits and Systems II: Express Briefs, vol.53, no.12, pp.1363-1367, Dec. 2006.
[3.14] D. Shin, J. Song, H. Chae, and C. Kim, “A 7 ps jitter 0.053 mm fast lock all-digital DLL with a wide range and high resolution DCC,” IEEE Journal of Solid-State Circuits, vol.44, no.9, pp.2437-2451, Sept. 2009.
114
Chapter 4.
[4.1] J.-C. Chi, H.-H. Lee, S.-H. Tsai, and M.-C. Chi, “Gate Level Multiple Supply Voltage Assignment Algorithm for Power Optimization Under Timing Constraint” IEEE Transactions on Very Large Scale Integration Systems, Vol.
15, No. 6, pp.637-648, June 2007.
[4.2] Hui Shao and Chi-Ying Tsui, “A Robust, Input Voltage Adaptive and Low Energy Consumption Level Converter for Sub-threshold Logic,” European Solid State Circuits Conference, pp.312-315, Sept. 2007.
[4.3] S. Ali, S. Tanner, and P.A. Farine, “A Robust, Low Power, High Speed Voltage Level Shifter with Built-in Short Circuit Current Reduction,” IEEE European Conference on Circuit Theory and Design, pp. 142-145, Aug. 2004.
[4.4] S.N. Wooters, B.H. Calhoun, and T.N. Blalock, “An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.57, No. 4, pp. 290-294, April 2010.
[4.5] S. L tkemeier and . R ckert, “A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 57, No. 9, pp.721-724, Sept. 2010.
[4.6] A. Hasanbegovic and S. Aunnet, “Low-Power Subthreshold to Above Threshold Level Shifter in 90 nm Process,” NORCHIP, pp.1-4, Nov. 2009.
[4.7] I.-J. Chang; J.-J. Kim; K. Kim, and K. Roy, “Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V,” IEEE Transactions on Very Large Scale Integration Systems, Vol.19, No.8, pp.1429-1437, Aug. 2011.
[4.8] Y.-S. Lin and D. Sylvester, “Single Stage Static Level Shifter Design for Subthreshold to I/O Voltage Conversion,” IEEE International Symposium on
115
Low Power Electronics and Design, pp. 197-2000, Aug. 2008.
[4.9] Y. Chavan and E. MacDonald, “Ultra Low Voltage Level Shifter to Interface Sub and Super Threshold Reconfigurable Logic Cells,” IEEE Aerospace Conference, pp. 1-6, March 2008.
[4.10] K.-H. Koo, J.-H. Seo, M.-L. Ko, and J.-W. Kim, “A New Level-Up Shifter for High Speed and Wide Range Interface in Ultra Deep Sub-Micron,” IEEE International Symposium on Circuits and Systems, Vol. 2, pp. 1063-1065, May 2005.
[4.11] K. Agarwal, V. Venkateswarlu, and D. Anvekar, “A Level Shifter Deep-Submicron node using Multi-Threshold Technique,” IEEE Recent Advances in Intelligent Computational Systems, pp. 925-929, Spet. 2011.
[4.12] Fang-Shi Lai and Wei Hwang, “Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems,” IEEE Journal of Solid-State Circuits, Vol. 32, No. 4, pp.
563-573, Apr. 1997.
[4.13] T.-H. Kim, H. Eom, J. Keane, and C. Kim, “Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Desing,” IEEE International Symposium on Low Power Electronics and Design, pp. 127-130, Oct. 2006.
116
Chapter 5.
[5.1] M. Hamada, M. Takahashi, H. Arakida, A. Chiba, T. Terazawa, T. Ishikawa, M.
Kanazawa, M. Igarashi, K. Usami, and T. Kuroda, “A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme, ” Proceedings of the IEEE Custom Integrated Circuits Conference, pp.495-498, May 1998.
[5.2] B. Amelifard, A. Afzali-Kusha, and A. Khadernzadeh, “Enhancing the efficiency of cluster voltage scaling technique for low-power
[5.2] B. Amelifard, A. Afzali-Kusha, and A. Khadernzadeh, “Enhancing the efficiency of cluster voltage scaling technique for low-power