OFDM part simulation results

AWGN, multipath, CFO, SCO and path loss effects are simulated in our system.

The simulation environment has AWGN, CFO, multipath and path loss. Simulation results are simulated with 1000 packets, 1000 bytes, rms 50ns, CFO 50 ppm, and SCO 50 ppm and path loss 25 dB. Figure 4.8 shows the PER of 36 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. Figure 4.9 shows the BER of 36 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. We can observe that the performance loss is about 1dB under the SCO effect.

Figure 4.8 PER of 36Mbps

Figure 4.9 BER of 36 Mbps

Simulation results are simulated with 1000 packets, 1000 bytes, AWGN from 18 dB

to 24 dB, rms 50 ns, CFO 50 ppm, SCO 50ppm and path loss -25 dB. Figure 4.10 shows the PER of 54 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. Figure 4.11 shows the BER of 54 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. The performance loss is about 1dB. The per curve will meet the standard at SNR22.

Figure 4.10 PER of 54 Mbps

Figure 4.11 BER of 54 Mbps

Figure 4.12 shows the SCO range that synchronization algorithm can tolerate under datarate is 36M. Simulation results are simulated with 1000 packets, 1000 bytes.

Simulation environment is IEEE Multiath RMS 50ns,CFO 50 ppm and pathloss -25dB Simulated SCO range are -800 -400 -200 -50 50 200 400 800. In our system, the tolerate range is from 400 to – 400.

Figure 4.12 SCO range that synchronization algorithm can tolerate

Figure 4.13 shows the SCO range that synchronization algorithm can tolerate under datarate in 54M. Simulation results are simulated with 500 packets, 1000 bytes.

Simulation environment is IEEE Multiath RMS 50ns,CFO 50 ppm and pathloss -25dB Simulated SCO range are -800 -400 -200 -50 50 200 400 800. In our system, the tolerate range is from 400 to – 400.

Figure 4.13 SCO range that synchronization algorithm can tolerate

CHAPTER 5

Proposed Hardware

5.1Matlab to Verilog Design Flow

Figure 5-1 shows the proposed platform design flow from Matlab simulation to hardware implementation. The first step of system design is chosen the suitable algorithm to avoid the channel effect. The second step is measured the proposed algorithm work well, then design architecture. System specifications need to check and performance should be maintained. Hence change the high level function description block to low level architecture hardware model one by one. The Matlab hardware models are built and system simulation is performed to keep the performance. After deciding the architecture, we have to perform the fixed point simulation, then design the HDL code that match the matlab code. And I use the same test bench as the matlab code to simulate HDL code. If the result does not match the match matlab result, we will modify the code and check the float-point simulation.

This is a trade-off between the hardware cost and system performance.

Figure 5-1 Matlab simulation to Hardware implement flow

5.2 Design Architecture

Figure 5-2 illustrates the block diagram of dynamic sampling. The clock source is the DLL output. Different from the usual, the proposed DLL is implemented with all-digital circuits, and replaced by all-digital delay lock loop (ADDLL) [10] which has the same function and similar architecture as DLL. ADDLL would adjust the sampling clock frequency and phase directly once the timing error is estimated.

Figure 5-2 the block diagram of dynamic sampling

The timing synchronization has two parts in DSSS system. The one is timing acquisition, another one is timing tracking algorithm. In OFDM system, the timing synchronization has timing acquisition only. The timing tracking part replaces by the AFC. The whole system of the proposed algorithm can be divided three parts, the OFDM timing acquisition, DSSS timing tracking and CCK timing tracking. At first, the data are saved into 16-element shift registers. The timing algorithm for DSSS, the timing algorithm for OFDM and timing algorithm for CCK share the shift registers.

Figure 5-3 the block diagram of DSSS/OFDM/CCK timing synchronization

5.3 Proposed hardware component

Figure5.4 shows the Architecture of timing tracking algorithm for DSSS modulation. The architecture of timing tracking algorithm for DSSS can be implemented with the formula (3.7).In the proposed architecture, we use the 2 adder and 2 multiplier, and a lot of the registers. The data that samples by the ADC were saved in the DATA_FIFO. The 11 XORs are used to achieve that receive data multiplied by the barker code. The square part can be implementing with Look-up Table(LUT) rather than multiplier to reduce hardware cost. Then the FIFO_1 and FIFO_2 are use to save peak powers, and I use the two adders, two multipliers to calculate the Current peak power Refpow. Here I use the 3 inputs adder rather than the 32 inputs adder to reduce the hardware cost. Like the accumulator, we add the new coming power, and we minus the 32 power to achieve the function of 32 inputs adder. Finally use the one comparator to calculate the final results, and then transmit the result to the ADDLL to sampling the optimum location.

Figure 5.4 Architecture of timing algorithm for DSSS modulation

Figure5.5 shows the Architecture of timing tracking algorithm for CCK modulation. The architecture of timing tracking algorithm for CCK can be implemented with the formula (3.8).And the architecture of timing tracking algorithm for CCK is almost the same as the Figure 5.3.In the proposed architecture, we use the 2 adder and 2 multiplier. Unlike the DSSS algorithm, we need on e buffer to save the input Data only.Then the FIFO_1 and FIFO_2 are use to save the max power of FWT, and I use the two adders, two multipliers to calculate the Current peak power Ref_pow. The same idea as the Architecture for DSSS, we use the 3 inputs adder to reduce the hardware cost. Finally use the one comparator to calculate the final results.

ADC_in

ADC_in

Figure 5.5 Architecture of timing algorithm for CCK modulation

Figure5.5 shows the Architecture of timing tracking algorithm for OFDM. The architecture of timing tracking algorithm for CCK can be implemented with the formula (3.15).In order to reduce the hardware cost, we change the formula to

*

Because the is the fix value, then we can reduce one multiplier. In the proposed architecture, we use the 1 adder, 1 multiplier and 3 comparator. Finally transmit the comparator result to ADDLL to sample the optimum location

( _k) norm S

ADC_in

Figure 5.6 Architecture of timing acquisition for OFDM modulation

Chapter 6

Conclusion and Future Work

6.1 Conclusion

In this thesis, we propose a timing synchronization algorithm that can handle successful both OFDM and DSSS packets and dynamically controlling the sampling frequency. So the 802.11g system is used to combine with the proposed systems.

Another contribution of mine is that my timing synchronization algorithm work under the lower sampling rate. This is the main different point from the traditional timing synchronization algorithm. And the proposed timing algorithm can resist the multipath fading, SCO, CFO, AWGN and pathloss effect. The Timing acquisition algorithm for DSSS can converge the sampling phase between plus 4 and minus 4.

The Timing acquisition algorithm for OFDM can converge the sampling phase between plus 6 and 0.The tracking algorithm for DSSS/CCK keep the optimum sampling phase within 6. Here I improve the AGC that proposed by the shih-Lin Hsu.

I propose the new AGC algorithm to fit the CCK modulation, and solve the control issues for AGC, and the other issues due to AGC. The most important issue is normalized problem for tracking algorithm. I was solve this problem successfully.

Finally I proposed the hardware architecture for my proposed system.

6.2 Future Work

There are some possible improvements in the future works. The ADDLL is the must of my system. So the design of ADDLL is the important part of my future work.

And the tracking algorithm is not better enough; I will try to design the better timing

synchronization algorithm. For implementing a chip finally, the fixed-point simulation is needed. So, the current floating-point (algorithm level) platform must been changed to fixed-point platform. The wordlength of my proposed system must be considered carefully. Construct the HDL platform is a bog work for me to do in the future. I will complete the HDL simulation in the future work.

References

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