Chapter 2 OFDM/DSSS System and Channel Model
3.3 Tracking algorithm for DSSS/CCK system
3.3.2 Tracking algorithm for CCK
In the802.11b\g system, CCK modulation is used under the datarate 5.5M and 11M.Unlike the daterate1M and 2M, CCK modulation is not robust to multipath. So the simulation environment does not include the multipath. This part describes the tracking algorithm for the CCK modulation. CCK modulation does not the same as the Dbpsk modulation has the PN-code property. The tracking algorithm for the CCK takes the MAX power of Fast Walsh Transform (FWT). After the preamble, we collect the 16 symbol’s max power of FWT. And we take the current 8 max power of FWT to compare with the RefCCKpow. The error function formula is:
………... (3.9)
Where RefCCKpow is the reference power for our algorithm and G is the current VGA Gain We will discuss the effect of AGC later. The best sample timing is located at where . We can know that the sampling clock phase approach the optimum sampling clock phase when the error function value is bigger than zero. When we take the RefCCKpow as the reference power to adjust the phase, We need to use the RefCCKpow carefully. If we take the RefCCKpow directly, we will find that the tacking speed will too fast. In order to solve this problem, we need to take the RefCCKpow*0.9 as the new RefCCKpow. And then we can find that ( )eτ > is meaning that the current 0 8 FWT max power is bigger than the RefCCKpow. If the sampling clock phase is not in the optimum sampling clock phase, the correlator output will degrade quickly. Hence we will adjust the phase when error function smaller than zero. The Figure 3.11 shows the situation after timing tracking. The x axis represents time and y axis represents sampling location. The time that between 0 to 160 is Bpsk modulation and 161 to the end is CCK modulation. In the beginning, we use the 3.3.1 algorithm until the preamble is over. When the preamble is over, we will check the modulation type and do the relative algorithm. The 64 means the best sampling clock phase location. We can observe that the sampling clock phase keep within 4.
( ) 0 eτ >
Figure 3.11 sampling clock phases with tracking algorithm
3.3.3 AGC for DSSS/CCK
In this section, i will introduce the AGC in the DSSS/CCK system. First I will describe the algorithm that proposed by the Shih-Lin Lo. Then I will explain the new algorithm that proposed by me.
3.3.3.1AGC for DSSS
This part is proposed by Shih-Lin Lo. In the real world, we don’t know how much the effect of path loss is. No matter the received signals are noise or data, we will set the AGC (auto gain control) gain to maximum in the beginning.
' 10 log (10 M )
G G
= − i D ………...(3.11)
Where G means the VGA gain and G’ is the next VGA gain. M is the estimated barker correlator power and D is the expected barker correlator power. There are two methods for getting barker correlator power. One is measuring the peak power
10
, the other is measuring the mean power.
10
Where k is the number of chips in one symbol. D_peak and D_avg are the expected peak power and mean power respectively. Unlike the DSSS system, the CCK system does not have the PN property. Therefore, the algorithm proposed by Shih-Lin Lo is not suitable for the CCK modulation. I will propose the new algorithm suitable for the CCK modulation.
3.3.3.2AGC for CCK
I will use the concept form the Shih-Lin Lo. Although CCK modulation does not have the PN property, we can use the FWT. The FWT function was used to construct the CCK demodulation. I will use the FWT to make AGC work correctly under CCK modulation. In this method, we get max power of FWT, and take it to do the AGC tracking. First I collect the 4 max power of FWT. Then I compare this value to the D_PFWT .D_PFWT is 95% of max power after FWT in perfect channel. We can use the formula 3.18 to adjust the VGA gain. In the formula 3.18 G’ is the next VGA gain, G
is the current VGA gain.
After the introduction of AGC in DSSS and CCK, I want to talk something about the design issues. The problem is when to control the AGC. In DSSS system, data is multiplied by the barker code. If we does not adjust the VGA gain on the symbol boundary. It will make the peak power hard to believe. Then the other function that use the PN property, can’t work correctly. The figure 3.12 and figure 3.13 show the two situations to control the AGC. The figure 3.12 controls the AGC on the symbol boundary. The figure 3.13 does not control the AGC with the wrong location.
Figure 3.12 AGC control with fine location
Figure 3.13 AGC control with the wrong location
In order to check the influence of when to adjust VGA gain, I do the two simulations under the effect of pathloss is constant. The figure 3.14 shows the variations of VGA gain with the fine location. It can observe easily that the pathloss is 25dB. If we adjust the VGA gain with the wrong location, it will make the figure 3.15. We can compare the figure3.15 with the figure3.14, and we can observe that the variations of VGA GAIN in the figure3.15 are serious more. This is the serious problem in our system.
When the VGA gain does not work correctly, functions followed by the AGC does not work correctly, too. Therefore we will check the symbol boundary before AGC acquisition and after timing acquisition. In the figure 3.16 we can see AGC acquisition follow by the packet coming. Timing acquisition is followed by the AGC acquisition. And AGC will suspend during timing acquisition. After the timing acquisition, I will do symbol boundary check again. Then AGC tracking can work correctly. Figure 3.16 show the state diagram of AGC. It describe the state of AGC and which formula to use when AGC work. The main difference between the AGC algorithms proposed by Shih-Lin Lo and the AGC algorithms proposed by me is that
the AGC algorithms proposed by Shih-Lin Lo are not suitable for CCK modulation.
Therefore, I will check the modulation type after the preamble is over. Depend on modulation type to choose suitable formula for AGC.
Figure 3.14 Coherent with symbol bound
Figure 3.15 NonCoherent with symbol bound
Figure 3.16state diagram of AGC
Another important issue is parameter G in the proposed tracking algorithm. We need to consider the AGC When we compare the latest correlator output with Refpow.
If the correlator outputs degrade, the AGC will adjust the VGA gain to high. Because the AGC will adjust the VGA gain, we don’t adjust the phase even if the sampling clock phase is not near the optimum sampling clock phase. Figure 3.17 show the timing synchronization without AGC gain normalization. Figure 3.18 show the timing synchronization with AGC gain normalization. From these two figures, we can observe that when the correlator powers degrade, the AGC will adjust the VGA gain to high in figure 3.17. The data in figure 3.18 is the same as figure 3.17.But the data in figure 3.19 was normalized by the parameter G. Hence we don’t do the gain normalization; we have no idea to know when the sampling clock phase is not near optimum sampling clock phase. So we use the parameter G to solve this problem.
When we use the parameter G in the proposed timing tracking system, I can find out the timing error easily. Figure 3.19 show the effect of timing synchronization without AGC gain normalization. It will make the timing synchronization hard to work
correctly. In the figure 3.19 the location 128 is the best location to sample the clock.
WE can see the timing error is serious with the time going. Figure 3.20 show the timing synchronization with AGC gain normalization. Then we can see the sampling clock phase within the optimum location.
Figure 3.17 timing synchronization without AGC gain normalization
Figure 3.18timing synchronization with AGC gain normalization
Figure 3.19 timing synchronization without AGC gain normalization
Figure 3.20 timing synchronization with AGC gain normalization
3.4 TIMING SYNCHRONIZATION for OFDM system
Frame detection Timing acquisition Auto frequency
control FFT
Channel
estimation Qam demapping De - interleaver Viterbi decoder Receive Data in
decode Data out AGC
Figure 3.21 Block diagram of 11a/g PHY system
Figure 3.21show the black diagram of 11a/g system. In the OFDM system, the timing synchronization needs to be completed during short preamble. Unlike the 802.11b/g, the 802.11a/g has 10 short preambles only. We need to use fewer preambles to achieve the timing acquisition. Here we use the property of PN code, the correlator output would be max when two PN code in phase only .Hence I will use normalized cross correlation to do timing synchronization in OFDM system. Like the figure3.22, we take the short preamble data to multiply the receive data, and calculate norm of short preamble and receive data, then C divided by the N equals P. And P is the normalized power.
……….…....(3.15)
(4 arg( ( )))*( 90 )
iPhase = − Max P −
………....(3.16) Where Pi is the normalized cross correlator power. The formula (3.16) is used to calculate the timing error, then use it to compensate the timing error.S hort T raining S equence
S hort T raining S equence
S hort T raining S equence S hort p ream b le
C orrelate
Figure 3.22 Relation between short preamble and short training sequence
Figure 3.23 sampling phase diagram
The figure 3.26 shows the all steps of the proposed timing synchronization algorithm.
After the packet is detected, we can collect the normalized power of the first short preamble, then shift the 90 degree each short preamble and save the normalized power of the short preamble each short preamble. Here I take the sampling phase as a circle.
Like the figure3.23, this is meaning that we can coarse estimate the normalized power of each phase. When preamble_count is equal to 3, we will check the normalized
power of the four short preambles, then choose the best one and adjust the sampling clock phase location.
We get another problem here, if we enable the AFC directly after the timing acquisition, the AFC will get the two preambles that preamble_count is equal to 2 and 3. But short preamble 2 and 3 are the measure data in the timing acquisition.
Therefore we need two short preambles that in the optimum sampling phase for AFC to estimate the CFO and phase error. In order to make sure that AFC can use two optimum sampling phase preambles to do the auto-correlation, we will wait two preambles for AFC. Figure 3.22 shows the sample clock phase error after this timing synchronization method. Simulation situation:
SNR = 17, Data rate =36, Packet NO = 100, PSDU length =1000 bytes CFO = 50 ppm, path loss = -25 dB, IEEE multipath RMS = 50 tap = 6
Figure 3.24 the sample clock phase error after this timing synchronization method Simulation situation:
SNR = 20, Data rate =54, Packet NO = 100, PSDU length =1000 bytes CFO = 50 ppm, path loss = -25 dB, IEEE multipath RMS = 100 tap = 6
Figure 3.25 the sample clock phase error after this timing synchronization method The Figure 3.22and Figure 3.23 show the phase error after our timing synchronization algorithm. We can observe that the max phase error is 6. Because the upsampling rate is 22, and the 22 divided by 4 equals 6.And 360 degree divided by the 90 degree equals 4. Hence we can evaluate the timing error is 6. Then the simulation results are matching my idea.
Table 5.1 Comparison state-of-the-art timing synchronization You-Hsien Lin[10] traditional[12][13] This work
Method Dual correlator
differential based interpolator Dynamic sampling
Sampling Rate 2 times 2 times 1 times
Modulation DSSS OFDM DSSS/CCK/OFDM
SCO tolerance
range SCO from 25 to - 25 N/A SCO from 400 to - 400 From the table 5.1 we can observe that the main advantage of the proposed algorithm is the sampling rate, and SCO tolerance range. The main reason of the proposed algorithm tolerate the SCO range from 400 to – 400 is that the proposed algorithm not only has the acquisition but also tracking mechanism.
S t a r t
Figure 3.26 state diagram of timing synchronization
N O
CHAPTER 4
SIMULATION RESULTS
4.1 Simulation tool
First we need to choose a suitable tool. Two languages, C/C++ and Matlab are the nice choices, because these two languages have a lot of advantages during the process of constructing platform. These advantages are listed below
a. Complete standard library and document of help b. Easy to learn programming style
c. High simulation speed
d. Quickly algorithm verification e. Co-simulate with Verilog f. Easily porting to HDL
Matlab is chosen as the suitable tool to construct the system platform for the reason of powerful matrix and mathematic functions, friendly Graphical User Interface (GUI), simple debugging tool and many different kinds of figure plotting functions. Although C/C++ has the highest simulation speed, but lack of mathematical functions and less friendly GUI cause us give up it to choose Matlab as the tool.
Figure 5-1 shows the block diagram of whole system. All important system parameters could be seeing in this figure. There three components in this system, transmitter, channel and receiver, and a top file is used to control these three components and call them. The top file controls a parameter-packet number, that parameter defines how many packets the system will execute at the same conditions with increasing SNR.
Figure 4.1 System block diagram 4.2 Simulation results
4.2 simulation results
4.2.1 DSSS/CCK part simulation results
In order to know the performance and tolerate range of my algorithm, I will simulate 2Mbps for DSSS part and 11Mbps for CCK part. AWGN, multipath, CFO, SCO and path loss effects are simulated in our system. For the DSSS part, the simulation environment has AWGN, CFO, multipath and path loss. Simulation results are simulated with 100 packets, 1000 bytes, IEEE multipath rms 50ns, CFO 50 ppm, and SCO 50 ppm and pathloss 25 dB. Figure 4.2 shows the PER of 2 Mbps with perfect synchronization, 1x acquisition with tracking and 1x acquisition without tracking. The performance loss is almost 1dB under the SCO effect.
Figure 4.2 PER of 2Mbps
Figure 4.3 shows the BER of 2 Mbps with perfect synchronization, 1x acquisition with tracking and 1x acquisition without tracking.
Figure 4.3 BER of 2Mbps
AWGN, CFO, SCO and path loss effects are simulated in our system. For the CCK part, the simulation environment has AWGN, CFO and path loss. Simulation results are simulated with 500 packets, 1000 bytes, CFO 50 ppm, and SCO 50 ppm and pathloss 25 dB. Figure 4.4 shows the PER of 11 Mbps with perfect synchronization, 1x acquisition with tracking and 1x acquisition without tracking. The performance loss is almost 1dB under the SCO effect. Figure 4.5 shows the BER of 11 Mbps with perfect synchronization, 1x acquisition with tracking and 1x acquisition without tracking.
Figure 4.4 PER of 11Mbps
Figure 4.5 BER of 11Mbps
Figure 4.6 and Figure 4.7 show the SCO range that synchronization algorithm for DSSS/CCK can tolerate. The tolerate range is almost in the 400 to -400. From Figure 4.6 and 4.7, our system will meet the requirement that per is smaller than 1/10 under SCO 50 ppm.
Figure 4.6 SCO range that synchronization algorithm can tolerate
Figure 4.7 SCO range that synchronization algorithm can tolerate
4.2.2 OFDM part simulation results
AWGN, multipath, CFO, SCO and path loss effects are simulated in our system.
The simulation environment has AWGN, CFO, multipath and path loss. Simulation results are simulated with 1000 packets, 1000 bytes, rms 50ns, CFO 50 ppm, and SCO 50 ppm and path loss 25 dB. Figure 4.8 shows the PER of 36 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. Figure 4.9 shows the BER of 36 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. We can observe that the performance loss is about 1dB under the SCO effect.
Figure 4.8 PER of 36Mbps
Figure 4.9 BER of 36 Mbps
Simulation results are simulated with 1000 packets, 1000 bytes, AWGN from 18 dB
to 24 dB, rms 50 ns, CFO 50 ppm, SCO 50ppm and path loss -25 dB. Figure 4.10 shows the PER of 54 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. Figure 4.11 shows the BER of 54 Mbps with perfect acquisition, 1x acquisition and random initial phase without acquisition. The performance loss is about 1dB. The per curve will meet the standard at SNR22.
Figure 4.10 PER of 54 Mbps
Figure 4.11 BER of 54 Mbps
Figure 4.12 shows the SCO range that synchronization algorithm can tolerate under datarate is 36M. Simulation results are simulated with 1000 packets, 1000 bytes.
Simulation environment is IEEE Multiath RMS 50ns,CFO 50 ppm and pathloss -25dB Simulated SCO range are -800 -400 -200 -50 50 200 400 800. In our system, the tolerate range is from 400 to – 400.
Figure 4.12 SCO range that synchronization algorithm can tolerate
Figure 4.13 shows the SCO range that synchronization algorithm can tolerate under datarate in 54M. Simulation results are simulated with 500 packets, 1000 bytes.
Simulation environment is IEEE Multiath RMS 50ns,CFO 50 ppm and pathloss -25dB Simulated SCO range are -800 -400 -200 -50 50 200 400 800. In our system, the tolerate range is from 400 to – 400.
Figure 4.13 SCO range that synchronization algorithm can tolerate
CHAPTER 5
Proposed Hardware
5.1Matlab to Verilog Design Flow
Figure 5-1 shows the proposed platform design flow from Matlab simulation to hardware implementation. The first step of system design is chosen the suitable algorithm to avoid the channel effect. The second step is measured the proposed algorithm work well, then design architecture. System specifications need to check and performance should be maintained. Hence change the high level function description block to low level architecture hardware model one by one. The Matlab hardware models are built and system simulation is performed to keep the performance. After deciding the architecture, we have to perform the fixed point simulation, then design the HDL code that match the matlab code. And I use the same test bench as the matlab code to simulate HDL code. If the result does not match the match matlab result, we will modify the code and check the float-point simulation.
This is a trade-off between the hardware cost and system performance.
Figure 5-1 Matlab simulation to Hardware implement flow
5.2 Design Architecture
Figure 5-2 illustrates the block diagram of dynamic sampling. The clock source is the DLL output. Different from the usual, the proposed DLL is implemented with all-digital circuits, and replaced by all-digital delay lock loop (ADDLL) [10] which has the same function and similar architecture as DLL. ADDLL would adjust the sampling clock frequency and phase directly once the timing error is estimated.
Figure 5-2 the block diagram of dynamic sampling
The timing synchronization has two parts in DSSS system. The one is timing acquisition, another one is timing tracking algorithm. In OFDM system, the timing synchronization has timing acquisition only. The timing tracking part replaces by the AFC. The whole system of the proposed algorithm can be divided three parts, the OFDM timing acquisition, DSSS timing tracking and CCK timing tracking. At first, the data are saved into 16-element shift registers. The timing algorithm for DSSS, the timing algorithm for OFDM and timing algorithm for CCK share the shift registers.
Figure 5-3 the block diagram of DSSS/OFDM/CCK timing synchronization
5.3 Proposed hardware component
Figure5.4 shows the Architecture of timing tracking algorithm for DSSS modulation. The architecture of timing tracking algorithm for DSSS can be implemented with the formula (3.7).In the proposed architecture, we use the 2 adder and 2 multiplier, and a lot of the registers. The data that samples by the ADC were
Figure5.4 shows the Architecture of timing tracking algorithm for DSSS modulation. The architecture of timing tracking algorithm for DSSS can be implemented with the formula (3.7).In the proposed architecture, we use the 2 adder and 2 multiplier, and a lot of the registers. The data that samples by the ADC were