Chapter 5 Proposed Hardware
5.3 Proposed hardware component
Figure 5-3 the block diagram of DSSS/OFDM/CCK timing synchronization
5.3 Proposed hardware component
Figure5.4 shows the Architecture of timing tracking algorithm for DSSS modulation. The architecture of timing tracking algorithm for DSSS can be implemented with the formula (3.7).In the proposed architecture, we use the 2 adder and 2 multiplier, and a lot of the registers. The data that samples by the ADC were saved in the DATA_FIFO. The 11 XORs are used to achieve that receive data multiplied by the barker code. The square part can be implementing with Look-up Table(LUT) rather than multiplier to reduce hardware cost. Then the FIFO_1 and FIFO_2 are use to save peak powers, and I use the two adders, two multipliers to calculate the Current peak power Refpow. Here I use the 3 inputs adder rather than the 32 inputs adder to reduce the hardware cost. Like the accumulator, we add the new coming power, and we minus the 32 power to achieve the function of 32 inputs adder. Finally use the one comparator to calculate the final results, and then transmit the result to the ADDLL to sampling the optimum location.
Figure 5.4 Architecture of timing algorithm for DSSS modulation
Figure5.5 shows the Architecture of timing tracking algorithm for CCK modulation. The architecture of timing tracking algorithm for CCK can be implemented with the formula (3.8).And the architecture of timing tracking algorithm for CCK is almost the same as the Figure 5.3.In the proposed architecture, we use the 2 adder and 2 multiplier. Unlike the DSSS algorithm, we need on e buffer to save the input Data only.Then the FIFO_1 and FIFO_2 are use to save the max power of FWT, and I use the two adders, two multipliers to calculate the Current peak power Refpow. The same idea as the Architecture for DSSS, we use the 3 inputs adder to reduce the hardware cost. Finally use the one comparator to calculate the final results.
ADC_in
ADC_in
Figure 5.5 Architecture of timing algorithm for CCK modulation
Figure5.5 shows the Architecture of timing tracking algorithm for OFDM. The architecture of timing tracking algorithm for CCK can be implemented with the formula (3.15).In order to reduce the hardware cost, we change the formula to
*
Because the is the fix value, then we can reduce one multiplier. In the proposed architecture, we use the 1 adder, 1 multiplier and 3 comparator. Finally transmit the comparator result to ADDLL to sample the optimum location
( k) norm S
ADC_in
Figure 5.6 Architecture of timing acquisition for OFDM modulation
Chapter 6
Conclusion and Future Work
6.1 Conclusion
In this thesis, we propose a timing synchronization algorithm that can handle successful both OFDM and DSSS packets and dynamically controlling the sampling frequency. So the 802.11g system is used to combine with the proposed systems.
Another contribution of mine is that my timing synchronization algorithm work under the lower sampling rate. This is the main different point from the traditional timing synchronization algorithm. And the proposed timing algorithm can resist the multipath fading, SCO, CFO, AWGN and pathloss effect. The Timing acquisition algorithm for DSSS can converge the sampling phase between plus 4 and minus 4.
The Timing acquisition algorithm for OFDM can converge the sampling phase between plus 6 and 0.The tracking algorithm for DSSS/CCK keep the optimum sampling phase within 6. Here I improve the AGC that proposed by the shih-Lin Hsu.
I propose the new AGC algorithm to fit the CCK modulation, and solve the control issues for AGC, and the other issues due to AGC. The most important issue is normalized problem for tracking algorithm. I was solve this problem successfully.
Finally I proposed the hardware architecture for my proposed system.
6.2 Future Work
There are some possible improvements in the future works. The ADDLL is the must of my system. So the design of ADDLL is the important part of my future work.
And the tracking algorithm is not better enough; I will try to design the better timing
synchronization algorithm. For implementing a chip finally, the fixed-point simulation is needed. So, the current floating-point (algorithm level) platform must been changed to fixed-point platform. The wordlength of my proposed system must be considered carefully. Construct the HDL platform is a bog work for me to do in the future. I will complete the HDL simulation in the future work.
References
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