Three-Dimensional Integrated Circuits (3D-ICs), i.e. electronic chips in which active layers of transistors are stacked one above the others, separated by insulation oxides and connected to each otherby interconnectwiresmay bethebestway to continueMoore’sLaw even in the absence of device scaling [7].
3D-IC would be a great benefit in cost reduction, higher performance, area of cell shrinking, high-level integration, etc. For the traditional 2D-IC, the interconnects between the transistors were connected on the same plane, and went by a devious route. From Pdyn~ CV2f, more than 50% of dynamic power consumption was wasted on the interconnects.
Consequently, the total interconnect lengths in stacked-IC were shortened by utilizing the vertical interconnects to connected the heterogeneous devices each other, and attracted much attention due to its advantages such as lowering the crosstalk and RC delay, high-speed operation, and low-power consumption.
With the initial attempts of 3D-ICs starting in 1980s, a number of techniques have been developed. Generally, either sequential process or wafer bonding process were used to fabricate 3D-ICs and suffered many challenges due to some limitations in terms of process complexity.
1.2.1 Sequential Process
One approach to fabricate 3D-ICs is the sequential process, which involved in laser annealing [8, 9], laser crystallization [10], Metal Induced Lateral Crystallization (MILC) [11]
and Laser-induced Epitaxial Growth (LEG) [12], etc.
With the laser annealing process, one concern in this approach is that high thermal budget
requirements in fabricating the devices on the top layer can affect the dopant distribution in the lower layers as well as affect the reliability of the metal wires below the top layer. The most important of the high thermal budget processes involved in transistors fabrication is the high temperature anneal step to activate the dopants in the channel and source drain regions [8].
Pulsed laser annealing is a very promising technology for dopant activation [13].
Ultra-short, high intensity laser pulses can melt the silicon substrate containing dopants.
During the subsequent recrystallization, the dopants move to substitutional sites in the lattice, thereby becoming electrically activated. However, undesirable heating of lower metal and device layers may occur during this process [8].
With laser crystallization process, the 3-D device obtained high quality with Silicon on Insulator (SOI) layers and stack them repeatedly. It has been already confirmed experimentally that the homogeneous re-crystallization all over the wafer is possible for the silicon island structure by using Dual Laser Beam re-crystallization method [14]. The seedless silicon island structure is very convenient to stack the SO1 layers [15]. Moreover, there is very little degradation of crystalline quality due to the strain in the silicon island.
Then, the CMOS SOI transistors were fabricated in the re-crystallized silicon island array, and TiSix was employed for the thermally stable interconnection on the 1st and 2nd layers because of its good adhesion to SiO2and relatively low sheet resistance (0.8Ω/□)[10].
With MILC process, the fabricated process started with SOI wafers and standard CMOS process such as threshold channel implant, gate oxide growth, the formation of poly-silicon gate electrode, source/drain implantation and dopant activation annealing were performed.
The first layer of devices was constructed [11]. Then low temperature oxide was deposited, and planarized by chemical and mechanical polish (CMP) and etch-back. The final interlayer
The amorphous silicon was then deposited and re-crystallized by MILC. The trace nickel (Ni) was deposited on the amorphous silicon film at the appropriate seeding window. The film was then annealed laterally and crystallized. When the nickel was removed, the film was re-crystallized. Finally, contact and interconnect process were performed to complete the 3-D structure [11].
Very recently, LEG (Laser-induced Epitaxial Growth) [12] process has been proposed to obtain the single c-Si layer over oxide and successfully demonstrated with cell-stacked high density SRAM [12]. With LEG process, a-Si molten by laser irradiation is changed into c-Si (i.e., LEG Si film) via lateral epitaxial growth from the seed to obtain the perfect c-Si on oxide layer. Therefore, the energy density of laser beam and the seed formation are the key factors to determine the crystal quality of Si layer on oxide. CMOSFETs on Si film prepared by LEG process have excellent behaviors in terms of both performance and its variations [12].
In totality, the sequential processes have many advantages on the device performance but also suffer many kinds of challenges, such as the quality of re-crystallized silicon by laser crystallization or MILC, interconnection implementation, via-holes forming, etc. The high thermal budgets during laser annealing or laser crystallization also attracted much attention due to it may be destroy the device characteristics.
1.2.2 Wafer Bonding Process
The wafer bonding process, i.e. bonding two fully processed wafers together, which the inter level interconnect density of 3D-ICs obtained by aligned bonding of pre-fabricated circuit levels and suffered from various technological challenges involved in the wafer
(1) Wafer bonding with alignment accuracy: it depends on different bonding technique, (I) face-to-face or face-to-back, (II) bonding with glue or direct bonding, (III) die-to-wafer or wafer-to-wafer. It also depends on wafer flatness, wafer co-planarity and heat uniformity during bonding with alignment.
(2) Bonding quality: the good bonding quality with some limitation of process requirements such as low temperature process compatible with BEOL (T＜400OC), low interface defects and high adhesion strength.
(3) Substrate thining: with multi-layer stacking, the substrate thining was compatibility with BEOL interconnect, 3D integration and improved wafer edge quality and surface quality (roughness and contamination). [16]