The Structure for Thermal Accumulation Improvement in LEG Process for 3D-ICs

Consider the thermal accumulated effect during laser irradiation may cause the damage to 1^st layer devices and maintain the excellent crystal quality of Si layer. The structure we proposed for improvement of thermal accumulation for laser irradiation as shown in Figure 3-1. The LEG process sequence that started with 1^st layer of device, and we use the typical n-MOSFET structure in simulation. First, the 10nm thick of gate oxide layer and 190nm thick

of poly-Si were deposited on silicon substrate in sequence. Next, one masking step is used to define the poly gate as well as to etch off the unmasked poly-Si layer. After the gate pattern is defined, the gate oxide layer was later etched off. The nitride (Si3N4) spacers were adding to protect poly gate and the constant doping profile as shown in Table 3-1.

When the 1^stlayer of MOSFET structure is finished, the insulator layer (SiO2) and thermal conduction layer such as Cu are deposited. After Via hole etching, the single crystal Si was selective epitaxy growth (SEG) as seed for lateral epitaxial growth, then LPCVD amorphous Si deposition process is accomplished. The single crystal Si was formation from the seed and lateral growth by laser irradiation.

Fig. 3-1 Schematic diagram of structure with thermal conduction layer for LEG process.

Tab. 3-1 Constant doping profile of the MOSFET.

3.2 Device Modeling and Results

Figure 3-2 shows the structure for thermal accumulation improvement, which is established by TCAD tools including 1^stlayer of n-MOSFET, Via interconnect and thermal conduction layer such as Cu in ILD oxide layer. When laser irradiated at the surface of a-Si, absorption coefficient of a-Si would be considered [39]. The Figure 3-3 is a graph showing a relation between optic wavelength and absorption coefficient for amorphous silicon and crystallized silicon [40]. There is a higher absorption coefficient about 10⁶cm^-1of amorphous silicon film at optic wavelength of 308nm. Regardless of the quality of a silicon film to be irradiated, energy of laser is absorbed on the surface and causes large temperature gradient in the film thickness direction. Thermal properties for crystallized silicon, amorphous silicon, silicon dioxide and copper we used in simulation as shown in Table 3-2 [41]. Note that value of thermal conductivity for a-Si independent temperature in our work is 1.5x10^-2 W/K-cm.

Figure 3-4 shows the local temperature distribution of the structure with amorphous Si / ILD (50 nm / 500 nm) on 1^st layer devices, and Via during laser irradiation by TCAD simulation.

The excimer laser beam with a wavelength of 308 nm and the energy density is preferably set to 300mJ/cm². The duration time is 20 ns and the irradiated window on surface of a-Si is from -1.5 μmto 0 μmat x-coordinate. The thick oxide has much lower thermal conductivity can prevent the heat dissipation to 1^stlayer and protect MOSFET device at room temperature (300K). The temperature of a-Si layer is much more than 1418K which is the melting point of a-Si to mean that a-Si layer can be sufficiently melted. However, the temperature of bottom of Via hole is too low to re-crystallization and form single crystal Si completely.

Fig. 3-2 Schematic diagram of structure with thermal conduction layer for LEG process by TCAD simulation

Fig. 3-3 Diagram of relation between optic wavelength and absorption coefficient for amorphous silicon and crystallized silicon.

Tab. 3-2 Thermal properties for materials we used in simulation.

Fig. 3-4 The temperature distribution of the structure with amorphous Si / ILD (50 nm / 500 nm) on 1^stlayer devices, and Via during laser irradiation by TCAD simulation.

(Unit:m and K)

In order to maintain the re-crystallization quality, the Via depth and ILD thickness decreased are necessary. Figure 3-5 shows the temperature distribution with the same laser energy for decreased ILD thickness (200 nm). Heat generated in the a-Si layer by the irradiation of the laser beam conducts toward the substrate. For the maximum temperature (t=20ns), the temperature at the top of the poly gate is attained to 420K, and about 464K at the top of the source/drain region may cause the source/drain doping diffusion and destruction the junction profile. Therefore, we propose a thermal conduction layer, which has higher thermal conductivity such as Cu, in ILD oxide to help the heat dissipation during laser irradiation. The temperature distribution was shown in Figure 3-6, in which the thickness of Cu is 10nm. Since the metal layer having high thermal conductivity is provided between the ILD oxide layer, heat stored in the a-Si layer and ILD oxide dissipates through the metal layer. From Figure 3-5 and Figure 3-6, the temperature at the top of the poly gate and source/drain region has been improved 93K and 102K, respectively, since the Cu layer assists the amount of heat to dissipate along lateral direction. There is no significant temperature difference of Via hole and Si layer between with and without Cu layer. This indicates that the addition thermal conduction layer would not degrade the re-crystallization quality of the Si layer.

Figure 3-7 (a) shows the temperature profile of the structure with Cu and without Cu slices a dotted line “a”in Figure 3-5 and Figure 3-6. The thickness of SiO2is 200 nm and Cu is 10 nm. Figure 3-7 (b) shows the temperature profile of the structure with Cu and without Cu slices a dotted line “a’”in Figure 3-5 and Figure 3-6. The maximum temperature at device region was improved more than 90K by thermal conduction layer to dissipate extra heat.

With the conduction Cu layer, the Via depth can reduce to 200 nm, and the maximum temperature of the 1^st layer at poly gate and source/drain maintains as low as ~320K and

Figure 3-8 (a) and (b) shows the Cu thickness and location effect, respectively. Figure 3-8 (a) shows temperature difference (-ΔT)atpoly gateand source/drain region ofthestructure withoutCu and with Cu fordifferentthicknessalong “a”and “a’”.Thedistancebetween Cu and upperSilayerisfixed for0.1 μm.ThethickerCu hasmoreimprovementforthickness 0.3μm. Figure 3-8 (b) shows temperature difference (-ΔT) at poly gate and source/drain region of the structure with Cu=10nm for different distance between Cu and upper Si layer along “a”and “a’”.Alltemperaturecan beimproved morethan 90 K atdifferent distance between Cu and upper Si layer.

Fig. 3-5 The temperature distribution with laser energy (300 mJ/cm²) for decreased ILD thickness (200 nm). (Unit:m and K)

Fig. 3-6 The temperature distribution with laser energy (300 mJ/cm²) for ILD thickness (200 nm) and a thermal conduction layer (10nm). (Unit:m and K)

-0.2 -0.1 0.0 0.1

Fig. 3-7 The temperature profile with and without thermal conduction Cu layer along the direction (a) poly gate region “a”in Figure 3-5 and Figure 3-6, and (b) source/drain region “a’”in Figure 3-5 and Figure 3-6.

0.010 0.015 0.020 0.025 0.030

Fig. 3-8 The temperature difference at the poly gate and source/drain region for (a) different thickness of Cu, and (b) difference distance between Cu to upper Si layer.

0.02 0.04 0.06 0.08 0.10 85

3.3 Summary

In 3D-IC architecture by LEG process, ILD oxide which is low-k dielectrics with poor thermal conductivity, will not only lead to lower Via temperature but also impact the device temperature in 1^stlayer. Therefore, we propose one structure which has a thermal conduction layer such as Cu in ILD oxide layer with LEG technology for 3D-ICs manufacturing. To reduce the Via depth and ILD oxide thickness can improve the re-crystallization quality for upper Si layer. The thermal conduction layer, which has higher thermal conductivity can efficient to dissipate the accumulated heat during laser irradiation. With the conduction Cu layer, the Via depth can reduce to 200 nm, and the maximum temperature of the 1^stlayer poly gate and source/drain maintains as low as ~320K and ~350K, respectively, for laser re-crystallization annealing. The heat due to laser irradiation also dissipate through the Via and the temperature of Via hole is sufficient to form good quality upper Si layer.

Chapter 4 Fabrication Process of One Mask MOSFET and Via