下世代軟性薄膜電晶體與積體電路之熱傳模擬及其製程研究

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(1)國立台灣師範大學光電科技研究所碩士班碩士論文. 下世代軟性薄膜電晶體與積體電路之熱傳模擬及其製程研究 The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation. 研究生 : 劉永宗指導教授 : 李敏鴻博士. 中華民國. 九十七年七月.

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(3) Related Publications (相關論文發表) A. Refereed International Conference Papers (國際學術會議論文) 1.. M. H. Lee, S. T. Chang, Y.-T. Liu, C.-F. Huang, K.-Y. Ho, P.-C. Chen, R.–S. Syu, and K.-W. Shen, “ TheOpe r a t i onofa -Si:H TFTs Flexible Electronics on Plastic Substrate, ” International Semiconductor Device Research Symposium (ISDRS), pp. 1-2, Washington D.C., 12-14 Dec., 2007.. 2.. Y.-T. Liu, S. T. Chang, R.-S. Syu, K.-W. Shen and M. H. Lee, “ TheThe r ma l Accumulated Improvement of a-Si:H Flexible Electronics for AMOLED Application, ” IEEE International Conference on Electron Devices and Solid-State Circuit (EDSSC), vol. I, pp. 523-526, Tainan, Taiwan, 20-22 Dec., 2007.. 3.. Y.-T. Liu, M. H. Lee, H. T. Chen, C.-F. Huang, C.-Y. Peng, L.-S. Lee, M.-J. Kao, “ Thermal Accumulation Improvement for Fabrication Manufacturing of Monolithic 3D Integrated Circuits,”accepted by The 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), Beijing, China, 20-23 Oct., 2008.. B. Refereed Conference Papers (國內學術會議論文) 1.. M. H. Lee, H. T. Chen, C.-H. Lee, G.-L. Luo, J. Shieh, Y.-T. Liu, R.-S. Syu, and K.-W. Shen, “ TheLoc a l i z a t i on Se l f -Assembled Ge Islands by Excimer Laser Annealing th without Prepatterned, ”15 Symposium on Nano Device Technology (SNDT), Hsinchu Taiwan, 2008. (功能性奈米材料技術學生論文優選獎). 2.. Y.-T. Liu, S. T. Chang, R.-S. Syu, K.-W. Shen and M. H. Lee, “ THE THERMAL CONTROLWITH DISSIPATION LAYER OF A-SI:H FLEXIBLE ELECTRONICS FOR AMOLED APPLICATION, ”2007 Optics and Photonics in Taiwan (OPT), 30 Nov.- 1 Dec., 2007, Taichung, Taiwan.. i.

(4) 下世代軟性薄膜電晶體與積體電路之熱傳模擬及其製程研究學生: 劉永宗. 指導教授: 李敏鴻博士國立台灣師範大學. 光電科技研究所碩士班摘要在本世紀中，薄膜電晶體(TFT)和積體電路(IC)已被廣泛地研發，以不同的結構應用在電子相關設計方面。在這些研究之中，熱管理技術在元件的製程及在驅動時必須被列入考慮並且是影響元件特性的關鍵點。熱累積效應將會導致元件製程的失敗及元件特性下降。因此我們提出熱效應改善方法並且利用 ISE TCAD 半導體模擬軟體得到相關溫度分布圖形來驗證。第一章我們先簡介非晶矽軟性薄膜電晶體的發展變化沿革以及近年來 3D 立體積體電路(3D-ICs)的不同製程，並進一步探討研究動機和論文架構。第二章利用 ISE TCAD 模擬來驗證非晶矽軟性薄膜電晶體結構中夾一層熱傳導層，如銅、鋁、鉬，在偏壓驅動時可有效的逸散熱並且降低元件的溫度。第三章我們首先提出在 3D-IC 的不同層元件之間的隔絕氧化層中加入一層銅作為熱傳導層的結構，接著再利用 ISE TCAD 模擬 2D 模型在雷射誘發磊晶成長(LEG)製程時的溫度分布圖形。第四章我們將提出金氧半場效電晶體(MOSFET)的製程研究，在此製程步驟中，微影技術(Lithography) 僅定義一道光罩。最後介紹元件製作的相關儀器操作流程與原理說明，以及 Via 陣列光罩圖形的設計。第五章對本論文之研究做結論並且探討未來研究工作目標與展望。. ii.

(5) The Thermal Simulation and Process of the Flexible TFTs and Integrated Circuit for Next-Generation Student: Yung-Tsung Liu. Advisor: Dr. Min-Hung Lee. Institute of Electro-Optical Science and Technology National Taiwan Normal University Abstract In this century, thin film transistors (TFTs) and integrated circuits (ICs) have been developed extensively and used in many electronics applications and designs with a range of different structures. Among these research, thermal management would be considered and played a critical role when devices during operation or in fabrication process. Thermal accumulation effects may lead to failure in manufacturing process and devices performance degradation. Therefore, we propose thermal improvement for these conditions and utilize ISE TCAD simulation to obtain the temperature distribution and profile. In chapter 1, we first introduce the course of change and development for flexible a-Si:H thin-film transistor and recent three-dimensional integrated circuits (3D-ICs) fabrication. Furthermore, motivation and organization of thesis will be explored. In chapter 2, we utilize TCAD simulation to verify that flexible a-Si:H TFT with thermal conduction layer such as copper (Cu), aluminum (Al), molybdenum (Mo) can efficient to dissipate more heat and lower device temperature during bias stress operation. In chapter 3, we first propose one structure, which has a thermal conduction layer such as Cu in ILD oxide layer for monolithic 3D-ICs. Then TCAD simulation was performed by solving the temperature distribution for 2D model during laser-induced epitaxial growth (LEG) process. In chapter 4, we make a description of fabrication process for Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) by lithography technique with only one mask definition. The operating instructions, principle of related instruments and design of mask pattern for Via arrays also be later summarized. In chapter 5, at the end of this thesis, we will make conclusions and future works.. iii.

(6) 致謝兩年碩士班研究生的生活，即將在今年夏天畫下句點，接下來準備要邁入人生的另一個階段。在這兩年中，不論是光電科技的相關專業知識或是在待人處事上，都有豐富的收穫。然而，能夠完成碩士的學業，當中得到許多人的鼎力相助，在此謹以此文表達我最深摯的謝意。首先最要感謝的人就是我的指導教授李敏鴻老師。回想剛進實驗室時，在態度上是個讓老師頭痛的學生，但感謝老師的包容與悉心指導，讓我在軟體模擬、半導體製程和相關應用方面學到不少技能，才能有一些研究成果發表。同時也要感謝老師常會提供一些寶貴的經驗傳授給我們，像是在實驗技巧，或是遇到的難題討論，甚至工作經驗分享等等，都讓我受益匪淺。在此由衷感謝老師這兩年來的照顧與教導。再來要感謝中興大學電機工程學系張書通老師，提供半導體模擬軟體讓我們學習使用，並且在模擬遇到困難時給予指導與協助；在模擬方面還要感謝王維敬學長、林文凱學長和大學同學宗諭，當我遇到問題時總能不辭辛勞地幫助我解決問題。在半導體製程學習上，要感謝國家奈米元件實驗室的各位工程師以及李承翰學長和指導我機台操作的各位學長學姐們，在實驗上的幫忙。另外要特別感謝工業技術研究院電光所李隆盛副理，在製程研究和專利分析上給予我的指導與協助；以及感謝台灣師範大學物理學系胡淑芬老師、中興大學電機工程學系裴靜偉老師和中央大學材料科學與工程研究所李勝偉老師於口試時給予我的指導與建議，讓我的論文更加完整。接著還要感謝和我一起度過兩年的實驗室同學裴帥坤葦和光電所傳奇人物睿翔，在這兩年的實驗室生活中一起學習，互相扶持，常開彼此的玩笑來減輕研究上的壓力，在你們身上我學到很多東西。還有搞笑的學弟們:冠任常一起去健身，韋宏常分享一些生活的經驗，偲傑常一起開玩笑或是去看棒球等等，有了你們，讓實驗室的生活變得很快樂。以及師大乙組棒球隊的各位隊友，曾經一起在球場上努力奮戰，每一場比賽都讓我留下美好的回憶。最後，要感謝我的父親劉子臣、母親張景賢和弟弟劉永康的支持，特別是感謝母親對我無微不致的照顧和包容，讓我能無後顧之憂的致力於我的碩士學業。在此，把本論文獻給我的家人. 劉永宗于台北台灣師大 iv.

(7) Contents Related Publications…………………………………………………………………………i Abstract (Chinese)………………………………………………………………………….. ii Abstrac t ………………………………………………………………………………………i i i Ac knowl e dge( Chi ne s e ) ……………………………………………………………………...iv Cont e nt s ….................................................................................................................................v Chapt e r1I nt r oduc t i on…........................................................................................................1 1.1 Overview of a-Si:H Thin-Film Transistor (a-Si:H TFT) on Flexible Substrate……...1 1.2 Recent Three-Dimensional Integrated Circuits (3D-ICs) Fabrication……………….3 1.2.1 Sequential Process……………………………………………………………….3 1.2.2 Wafer Bonding Process………………………………………………….............5 1.3 Motivation……………………………………………………………………………6 1.4 Or g a ni z a t i onofThe s i s ……………………………………………………………….7 Chapter 2 Simulation of Thermal Improvement for a-Si:H TFTs on Flexible Substrate……………………………………………………………………...……………….9 2.1 Thermal Conduc t i vi t y …………….………………………………………………….9 2.2 The Structure of a-Si:H TFTs with Thermal Improvement on Flexible Substrate…12 2.3 Device Simulation …………………………………………………….....................15 2.3.1 DOS Model for the a-Si:H……………………………………………………...15 2.3.2 Thermodynamic Model for the Device Simulation…………………………….17 2.3.3 Major Physical Model………………………………………………………….18 2.4 Device Modeling and Results……………………………………………………….21 2.4.1 a-Si:H TFT with Different Substrates………………………………………….21 2.4.2 a-Si:H TFT with Thermal Conduction Layer on Flexible Substrate………..….31 2.5 Summary……………………………………………………………………………42 Chapter 3 Simulation of Thermal Accumulation Improvement for Fabrication Manufacturing of Monolithic 3D Integrated Circuits……………………………………43 3.1 The Structure for Thermal Accumulation Improvement in LEG Process for 3D-ICs …………………………………………………………………………………………..43 3.2 Device Modeling and Results……………………………………………………….46 3.3 Summary……………………………………………………………………………56 Chapter 4 Fabrication Process of One Mask MOSFET and Via Hole Design for 3D-IC Applications..………………………………………………………………………………..57 4.1 One Mask MOSFET Fa br i c a t i onFl ow……………………………………………..57 v.

(8) 4.2 Process Principles…………………………………………………………………...60 4.2.1 Wafer Cleaning and Wet Etching………………………………………………60 4.2.2 Deposition Process and Thermal Annealing…………………………………...63 4.2.3 Lithography Process……………………………………………………………65 4.3 Design of Via Interconnect for 3D-IC Applications……………………..…………68 Chapter 5 Conclusions and Future Works………………………………………………..70 5.1 Summary…………………………………………………………………………70 References…………………………………………………………………………………...71. vi.

(9) Chapter 1. Introduction. 1.1 Overview of a-Si:H Thin-Film Transistor (a-Si:H TFT) on Flexible Substrate Since hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) were described by LeComber et al. in 1979 [1], they have been widely used as switching devices in active-matrix liquid crystal displays (AMLCDs) [2]. Therefore, many researches devoted themselves on how to improve the performance of TFT has been started at that time. Currently, the TFT LCD is the preferred display in almost all kinds of products that require displays. For example, TFT LCDs are exclusively used in mobile phones, digital cameras, camcorders, game machines, PC monitors, TVs, global position systems (GPS), automobile panels, industry and medical instruments, entertainment equipments, transportation, military systems, etc. For the skills in the prior art in TFTs, it is well known that hydrogenated amorphous silicon had been a popular material to be used to fabricated on TFTs in AMLCDs, due to its compatibility with low processing temperature on large-area glass substrate. However, the rigid TFT LCDs (flat panel displays, FPD) already can not satisfy the requirement for people in the present day. The flexible a-Si:H thin-film transistor liquid crystal displays, which have many primary advantages of plastic substrates with respect to glass, such as a reduction in the weight of the display and an alleviation of the problem of display breakage [3], both during fabrication and use. Additionally, plastic substrates offer the possibility of significant reductions in cost over the types of glass currently used in displays. Plastic substrates are also an ideal platform for the development of ultra-large displays, such as those used in advertising and other large-scale information systems, due to their compatibility with roll-to1.

(10) roll processing [4]. These advantages of plastic substrates as well as arbitrary sharpness and unrestrained design, make many applications like portable instruments, e-paper, RFID, and PDA. However, the choice of flexible substrates, such as polyimide (PI), polyetheretherketone (PEEK), polyethersulphone (PES), polyetherimide (PEI), polyethylenenapthalate (PEN), polyester (PET), etc, were restricted by material characteristics themselves as shown in Table.1-1(a)(b) and un-adapted to the process for the glass substrates presently. Many process applied to the flexible substrates has been started to develop. For example, Seiko Epson has already to develop the SUFTLA (Surface Free Technology by Laser Annealing/Ablation) technique and successful to exploit the full color active-matrix organic light emitting diode (AMOLED). The Samsung Company also fabricated the 7 inch flexible LCD in 2006 successfully. Bad thermal properties, such as high CTE (Coefficient of Thermal Expansion, 20 ppm/°C), high moisture absorption and low Tg (glass transition temperature, ~350°C) of polyimide (PI), which is often used for the flexible substrate, make the fabrication process complicated and devices performance degradation during the operation, due to damage the plastic substrate [5,6]. Moreover, lower thermal conductivity of PI (Kapton, κ=1.7x10-3W/K-cm) makes the heat accumulated easily during operation and lead to device temperature increasing may induce plastic substrate deformation or distortion due to lower Tg of PI. Therefore, thermal accumulated problem of the plastic substrate during device operation must be considered and to improve while to preserve good electronic performance of the flexible a-Si:H TFT .. 2.

(11) 1.2 Recent Three-Dimensional Integrated Circuits (3D-ICs) Fabrication Three-Dimensional Integrated Circuits (3D-ICs), i.e. electronic chips in which active layers of transistors are stacked one above the others, separated by insulation oxides and connected to each ot he rbyi nt e r c onne c twi r e sma ybet hebe s twa yt oc ont i nueMoor e ’ sLaw even in the absence of device scaling [7]. 3D-IC would be a great benefit in cost reduction, higher performance, area of cell shrinking, high-level integration, etc. For the traditional 2D-IC, the interconnects between the transistors were connected on the same plane, and went by a devious route. From Pdyn ~ CV2f, more than 50% of dynamic power consumption was wasted on the interconnects. Consequently, the total interconnect lengths in stacked-IC were shortened by utilizing the vertical interconnects to connected the heterogeneous devices each other, and attracted much attention due to its advantages such as lowering the crosstalk and RC delay, high-speed operation, and low-power consumption. With the initial attempts of 3D-ICs starting in 1980s, a number of techniques have been developed. Generally, either sequential process or wafer bonding process were used to fabricate 3D-ICs and suffered many challenges due to some limitations in terms of process complexity.. 1.2.1. Sequential Process. One approach to fabricate 3D-ICs is the sequential process, which involved in laser annealing [8, 9], laser crystallization [10], Metal Induced Lateral Crystallization (MILC) [11] and Laser-induced Epitaxial Growth (LEG) [12], etc. With the laser annealing process, one concern in this approach is that high thermal budget 3.

(12) requirements in fabricating the devices on the top layer can affect the dopant distribution in the lower layers as well as affect the reliability of the metal wires below the top layer. The most important of the high thermal budget processes involved in transistors fabrication is the high temperature anneal step to activate the dopants in the channel and source drain regions [8]. Pulsed laser annealing is a very promising technology for dopant activation [13]. Ultra-short, high intensity laser pulses can melt the silicon substrate containing dopants. During the subsequent recrystallization, the dopants move to substitutional sites in the lattice, thereby becoming electrically activated. However, undesirable heating of lower metal and device layers may occur during this process [8]. With laser crystallization process, the 3-D device obtained high quality with Silicon on Insulator (SOI) layers and stack them repeatedly. It has been already confirmed experimentally that the homogeneous re-crystallization all over the wafer is possible for the silicon island structure by using Dual Laser Beam re-crystallization method [14]. The seedless silicon island structure is very convenient to stack the SO1 layers [15]. Moreover, there is very little degradation of crystalline quality due to the strain in the silicon island. Then, the CMOS SOI transistors were fabricated in the re-crystallized silicon island array, and TiSix was employed for the thermally stable interconnection on the 1st and 2nd layers because of its good adhesion to SiO2 and relatively low sheet resistance ( 0. 8Ω/ □)[10]. With MILC process, the fabricated process started with SOI wafers and standard CMOS process such as threshold channel implant, gate oxide growth, the formation of poly-silicon gate electrode, source/drain implantation and dopant activation annealing were performed. The first layer of devices was constructed [11]. Then low temperature oxide was deposited, and planarized by chemical and mechanical polish (CMP) and etch-back. The final interlayer oxide was about 5000Å thick. The second layer of devices was built on the top of this oxide.. 4.

(13) The amorphous silicon was then deposited and re-crystallized by MILC. The trace nickel (Ni) was deposited on the amorphous silicon film at the appropriate seeding window. The film was then annealed laterally and crystallized. When the nickel was removed, the film was re-crystallized. Finally, contact and interconnect process were performed to complete the 3-D structure [11]. Very recently, LEG (Laser-induced Epitaxial Growth) [12] process has been proposed to obtain the single c-Si layer over oxide and successfully demonstrated with cell-stacked high density SRAM [12]. With LEG process, a-Si molten by laser irradiation is changed into c-Si (i.e., LEG Si film) via lateral epitaxial growth from the seed to obtain the perfect c-Si on oxide layer. Therefore, the energy density of laser beam and the seed formation are the key factors to determine the crystal quality of Si layer on oxide. CMOSFETs on Si film prepared by LEG process have excellent behaviors in terms of both performance and its variations [12]. In totality, the sequential processes have many advantages on the device performance but also suffer many kinds of challenges, such as the quality of re-crystallized silicon by laser crystallization or MILC, interconnection implementation, via-holes forming, etc. The high thermal budgets during laser annealing or laser crystallization also attracted much attention due to it may be destroy the device characteristics.. 1.2.2 Wafer Bonding Process The wafer bonding process, i.e. bonding two fully processed wafers together, which the inter level interconnect density of 3D-ICs obtained by aligned bonding of pre-fabricated circuit levels and suffered from various technological challenges involved in the wafer bonding process [16]: 5.

(14) (1) Wafer bonding with alignment accuracy: it depends on different bonding technique, (I) face-to-face or face-to-back, (II) bonding with glue or direct bonding, (III) die-to-wafer or wafer-to-wafer. It also depends on wafer flatness, wafer co-planarity and heat uniformity during bonding with alignment. (2) Bonding quality: the good bonding quality with some limitation of process requirements such as low temperature process compatible with BEOL (T＜400OC), low interface defects and high adhesion strength. (3) Substrate thining: with multi-layer stacking, the substrate thining was compatibility with BEOL interconnect, 3D integration and improved wafer edge quality and surface quality (roughness and contamination). [16]. 1.3 Motivation To conclude and combine the advantages and issue above described, we seek only the thermal accumulated improvement for the flexible a-Si:H TFT and 3D-IC with LEG process, respectively. During flexible a-Si:H TFT operation, the heat by operation will accumulate and dissipate from top layer to the below layer, and destroy the plastic substrate due to its high CTE and low Tg. Therefore, the heat transfer problem may be solved by the method that we proposed in the chapter 2. With LEG process, the heat produced during laser irradiation also caused damage to the 1st layer of device. We proposed one structure that can improve the thermal problem during laser irradiation in chapter 3.. 6.

(15) 1.4 Organization of Thesis In this section, I will show our research efforts. This thesis is organized as follow: In chapter 1, the overview of flexible a-Si:H TFTs, plastic substrates, recent 3D-ICs technology and finally motivation are described in this section. In chapter 2, we propose several kinds of materials which have different thermal conductivity be the thermal conduction layers between the buffer oxide and substrate of a-Si:H TFT device. To understand the transient thermal profile and temperature distribution, we performed by solving the temperature distribution and heat diffusion for a 2-D a-Si:H TFT model with constant current stress for heating source, which is following bias condition for AMOLED application. In chapter 3, we emphasized the LEG process in 3D-IC and also proposed one structure with thermal conduction layer such as Cu to improve heat accumulation may lead to the dopant diffusion in the 1st layer of device. In chapter 4, the experimental process flows for MOSFET by lithography technique with only one mask definition are demonstrated. We also design different size and spacing of Via hole for 3D IC applications. Finally in chapter 5, we will make conclusions and future works.. 7.

(16) Tab. 1-1. Material characteristics of flexible substrates.. (a). (b). 8.

(17) Chapter 2. Simulation of Thermal Improvement for a-Si:H. TFTs on Flexible Substrate. In this chapter, we will discuss about the thermal simulation for a-Si:H TFT on different substrate with current stress operation. The thermal improvement by properly interposing a thermal conduction layer between the PI substrate and the buffer oxide layer in flexible a-Si:H TFT. The proposed method has improved the heat accumulated problem during device operation obtained by TCAD simulation.. 2.1 Thermal Conductivity To investigate the heat dissipation of the a-Si:H TFT during operation, the thermal conductivity (κ) of materials may play a key role for the heat propagation during operation. For steady-state heat flow, it is the proportionality constant between the heat flux and the temperature gradient. In metals, thermal conductivity approximately tracks electrical conductivity, as freely moving valence electrons transfer not only electric current but also heat energy. However, the general correlation between electrical and thermal conductance does not hold for other materials, due to the increased importance of phonon carriers for heat in non-metals. For a-Si:H, thermal energy may be transported by two modes: phonons propagation through lattice vibration and free electrons displacement [17]. The contribution of the latter mode is generally low in amorphous semiconductors, since the presence of a large density of gap states reduces the mobility and the lifetime of free electrons leading to a weaker electrical conductivity than in crystalline material. On the other hand, the presence of dangling bonds, rich hydrogen concentration and highly disorder in the film network reduces thermal conduction due to the deposition method. The a-Si:H film prepared by physical vapor 9.

(18) deposition (PVD) exhibit microheterogeneity, large defect density and high disorder than material prepared by chemical vapor deposition (CVD) [17]. Therefore, the thermal conductivity of a-Si:H films is lower than in the well organized single-crystalline silicon material, where the thermal conductivity is in the order of (κ=1. 5W/ K-cm) at room temperature. The ratio of thermal conductivity in a-Si:H to thermal conductivity in singlecrystalline silicon is in the order of 10-4 ~ 10-2 [17]. The value of thermal conductivity for a-Si:H independent temperature in our work is 1.5x10-2 W/K-cm. Table 2-1 shows the thermal conductivity of several materials we used in this work. Generally, thermal conductivity of the metal conductors is much higher than that of non-metals, such as insulators or amorphous semiconductors. In this simulation, we also consider the specific heat of different materials [18].. 10.

(19) Tab. 2-1. The material thermal conductivity in this work.. Material. κ[ W/ ( K-cm)]. Single-crystalline silicon (c-Si). 1.5. Hydrogenated amorphous silicon (a-Si:H). 1.5x10-2. Polyimide (PI). 1.7x10-3. Silicon dioxide (SiO2). 1.4x10-2. Boron silicon glass (BSG). 1.4x10-2. Silicon nitride (Si3N4). 1.85x10-1. Molybdenum (Mo). 1.32. Aluminum (Al). 2.38. Copper (Cu). 3.85. 11.

(20) 2.2 The Structure of a-Si:H TFTs with Thermal Improvement on Flexible Substrate Before we proposed the structure of thermal conduction layer with flexible a-Si:H TFT, we need to discuss the structure about the TFTs first. There is a great flexibility on the deposition sequence of various films and three electrodes being a TFT, which prepared by a thin film deposition method. Therefore, there is a large degree of freedom in preparing TFTs. In general, there are three basic types of TFT structures [19]: (1) Staggered, which is also known as the top gate. (2) Inverted, staggered, which is also known as the bottom gate. This category contains two types: bi-layer and tri-layer. (3) Coplanar. In our work, we use the inverted, staggered and bi-layer structure which is commonly used in a-Si:H TFT, as shown in Figure 2-1 [20]. The process needs three masking steps for gate, a-Si:H island and source/drain, respectively. After the gate pattern is defined, three film layers, gate dielectric (silicon nitride, Si3N4), a-Si:H and n+ a-Si:H are deposited in one pump-down. Then the second mask define the a-Si:H island containing the n+ film, and the source/drain mask is used to define the source/drain metal as well as to etch off the unmasked n+ layer. One of the key points for the structure of a-Si:H TFT is the overlap between the source/drain metal and bottom metal, and applying a redundant dielectric layer structure to avoid the crossover shortage problem. In general, the inverted, staggered a-Si:H TFT has better device characteristics than the staggered a-Si:H TFT because of the superior a-Si:H/Si3N4 interface properties due to a lower interface density of states [19]. From the Table 2-1, the materials are common in semiconductor or LCD process. The thermal conductivity of metal (Cu, Al and Mo) is higher than that of non-metal (Si3N4, glass. 12.

(21) and PI). The a-Si:H TFTs on PI substrate is relatively lower thermal conductivity as compared with single-crystal silicon wafer substrate and glass substrate, and is easy to accumulated heat during operation. Adding a thermal conduction layer, in which is used to assist the heat dissipation and to lower the highest temperature of the device and substrate. Figure 2-2 shows the schematic diagram of the flexible a-Si:H TFT structure to add a thermal conduction layer, such as Cu, Al, Mo and Si3N4, between the buffer oxide and PI substrate.. 13.

(22) Fig. 2-1. Fig. 2-2. The structure of a-Si:H TFT in this work.. The structure of a-Si:H TFT with thermal conduction layer on flexible. substrate.. 14.

(23) 2.3 Device Simulation We used ISE TCAD to carry out the process simulation and device simulation for a-Si:H TFT. Many models are including in this devices simulation, such as device physics, boundary conditions, numerical technology and analyses.. 2.3.1 DOS Model for the a-Si:H With a-Si:H model, the band gap is about 1.7 eV, and the density of states (DOS) in the mobility gap is a key issue for this simulation and has been extensively studied using different experimental techniques [19]. Based on these experimental studies, it is demonstrated that the distribution of the localized states in a-Si:H mobility gap may be modeled by exponential distributions of deep and tail states for both acceptor-like and donor-like states, as shown in Figure 2-3 [21]. The density of defect states (DOS) is composed of four bands: (1) donor-like tail state (2) acceptor-like tail state (3) donor-like deep level state (4) acceptor-like deep level state; The densities of the acceptor-like states gA(E) and donor-like states gD(E) as a function of energy E may be written as follows respectively:. E - E C  E - E C    g A (E) g tc exp   g exp dc E  E  …………………………………...(Eq 2-1)  tc   dc  E V - E  E V - E    g D (E) g tv exp  E g dv exp  E …………………………………..(Eq 2-2)  tv   dv . 15.

(24) where EC and EV are the conduction band edge and valence band edge, gtc and gdc the densities of states at the conduction band edge for the tail and deep acceptor-like states, respectively, and Etc and Edc the associated slope of the exponential distribution of the tail and deep acceptor-like states, respectively. gtv, gdv, Etv and Edv are similarly defined for the exponential distribution of the tail and deep donor-like states.. Fig. 2-3. Illustration of the density of states (DOS) in intrinsic a-Si:H [20].. 16.

(25) 2.3.2 Thermodynamic Model for the Device Simulation For device simulation, we simulated self-heating effects by using the thermodynamic model. The thermodynamic model [22] extends the drift-diffusion approach to account for electro-thermal effects. To simulate self-heating effects on the temperature distribution, the physical background of the thermodynamic model and its formulation (differential equations, boundary conditions, parameters) is described as below: The three governing equations for charge transport in semiconductor devices are the Poisson equation and the electron and hole continuity equations. The Poisson equation is:.   - q (p - n N D - N A- ) …………………………………………..(Eq 2-3) where εi st hee l e c t r i c a lpe r mi t t i vi t y ,qis the elementary electronic charge, n and p are the electron and hole densities, and ND+ is the number of ionized donors, and NA_ is the number of ionized acceptors. The electron and hole continuity equations are written as:.  J n qR q. n t. -  J p qR q.  p  t …………………………………………………………….(Eq 2-5). ……………………………………………………………..(Eq 2-4). where R is the net electron–hole recombination rate, Jn is the electron current density, and Jp is the hole current density. The thermodynamic model is defined by the basic set of Eq.2-3 ~ Eq.2-5. The drift-diffusion model which widely used for the simulation of carrier transport in semiconductors can generalized to include the temperature gradient as a driving term: 17.

(26) J n - nqn (n Pn T) …………………………………………………….(Eq 2-6) J p - pqp (p P p T). ……………………………………………………..(Eq 2-7). Where μn and μp are the electron and hole mobilities, φn and φp are the electron and hole quasi-Fermi potentials, and Pn and Pp are the absolute thermoelectric powers [23]. To calculate the temperature distribution in the device due to self-heating, the following equation is solved:. c. . .  T 3   -  T -  Pn T n  J n (Pp T p )J p - E C  k B T  Jn  t 2  . 3   - E V - k BT   Jp 2  . qR  E C - E V 3k B T  ………………………………………………………………………………………… (Eq 2-8). Where κi st het he r ma lc onduc t i vi t yand c is the lattice heat capacity. Ec and Ev are the conduction and valence band energies, respectively, and R is the recombination rate.. 2.3.3 Major Physical Model In this section, we describe the major set of physical models, which are used to demonstrate the simulation of our device. The model selection commands in the physics section that we use as follows: (1) Van Dort quantum correction model: This model takes the quantum mechanical band gap widening into account only for electrons (holes) in channels. The van Dort model recognizes all semiconductor–insulator 18.

(27) interfaces regardless of their orientation. (2) Band-gap model: In this model, the command “ ba nd-g a pna r r owi ng ”and the correction in simulations using Fermi statistics can be switched off. (3) Mobility models: The carrier mobility that we used in this model is a function of the lattice temperature. The temperature-dependent constant mobility model is including doping dependence, normal field effects, and carrier–carrier scattering. With the constant mobility model [24], the carrier mobility is dependent only on the lattice temperature as well as affected by phonon scattering. The constant carrier mobility can be written as a function with the lattice temperature as follow [24]:. -. const. T  L  T   …………………………………………………………………...(Eq 2-9) 0 . where μL is the mobility due to bulk phonon scattering, T is the lattice temperature, and T0 = 300K. The values of μL a ndt hee xpone ntζthat we use for a-Si:H are listed in Table 2-2. In our a-Si:H TFT model, source/drain region with doped arsenic which make scattering of the carriers by charged impurity ions leads to degradation of the carrier mobility. Thus we also take the doping dependence model into account. Otherwise, in the channel region of a-Si:H TFT, the high transverse electric field forces carriers to interact strongly with the semiconductor–insulator interface. Carriers are subjected to scattering by acoustic surface phonons and surface roughness. The model that activated by normal field effects describes mobility degradation caused by these effects at interface. (4) Recombination model: Recombination through deep levels in the gap is usually labeled Shockley–Read–Hall 19.

(28) (SRH) recombination. The doping dependence of the SRH lifetimes is modeled with the Scharfetter relation:. dop  Ni  min . max - min. N i 1  N  ref. .    . ………………………………………………..(Eq 2-10). Such this dependence arises from experimental data [25] and the theoretical conclusion that the solubility of a fundamental, acceptor-type defect is strongly correlated to the doping density [26 –28]. Otherwise, the Auger recombination [29 –31] and Phonon-assisted band-to-band tunneling [32] in which we also consider in our device.. Tab. 2-2. Constant mobility model: Coefficients for amorphous silicon.. 20.

(29) 2.4 Device Modeling and Results In this section, we first compared with the difference in temperature profile between the a-Si:H TFTs on different substrates after constant current stress operation. Secondly, the thermal conduction layer, which was several kinds of material with different thickness, adding between the plastic substrate and buffer silicon oxide layer of structure to understand the transient thermal profile and temperature distribution.. 2.4.1 a-Si:H TFT with Different Substrates Figure 2-4 shows the basic 2-D structure of a-Si:H TFT that we simulate by TCAD tools “ Floops”and “ Mdraw” . Note that we only create one device to simulate. In this structure, the substrate we use different materials such as silicon wafer, BSG and PI to compare with the difference of the temperature profile after the same constant current stress condition. The comparison of thermal properties between silicon wafer, BSG and PI are listed in Table 2-3. Among these materials, polyimide is unusual in having a lower working temperature of 250~320 OC but upper compared with another plastic materials as shown in Table 1-1(b), which makes it compatible with both a-Si:H and Si3N4 deposition by PECVD [33 , 34]. When the substrate is defined, the buffer layer (silicon dioxide, SiO2) deposited. After the gate pattern is defined, three film layers, gate dielectric (silicon nitride, Si3N4), a-Si:H and n+ a-Si:H are deposited in one pump-down. Then the second mask define the a-Si:H island containing the n+ film, and the source/drain mask is used to define the source/drain metal as well as to etch off the unmasked n+ layer. The thickness of each layers and gate length that we use in simulation are listed in Table 2-4.. 21.

(30) Fig. 2-4. Schematic diagram of a-Si:H TFT structure created by TCAD tools.. Tab. 2-3. Thermal properties for silicon, BSG and polyimide.. 22.

(31) Tab. 2-4. Each layers thickness and gate length of our device structure.. 23.

(32) We calculate temperature distribution of a-Si:H TFT on different substrates under constant current stress for heating source at bias Vg = 6V & Vd = 30V for 20sec, which is following bias condition for Active Matrix Organic Light Emitting Diode (AMOLED) application as shown in Figure 2-6 ~ 2-9. Figure 2-5 shows the heat flow path of a-Si:H TFT during operation. When electron current flows from source to drain, electrons will impact the lattice of atoms in crystal enormously and the amount of heat generation in the device can be determined. This is so-called self-heating. The heat will accumulate in the adjacent region of drain and dissipate to other layers. Figure 2-6 shows the whole temperature distribution of a-Si:H TFT on PI substrate after bias Vg = 6V & Vd = 30V for 20sec. Note that initial temperature we set a default value at room temperature is 300K. Because of lower thermal conductivity of the PI substrate, notable temperature gradient decay is revealed between the top and bottom of the PI. The final temperature of the bottom of PI still keeps 300K. Figure 2-7 shows localization of the drain region from figure 2-6. The highest temperature has already attained to 472.96 K at the drain and adjacent region, and about 470 K at the interface between the buffer oxide layer and PI substrate. Due to high CTE (20 ppm/°C) and low working temperature of PI characteristics, the high temperature at interface between buffer oxide and PI may cause many thermal effects. The lower thermal conductivity of PI would make the heat accumulated, and the high temperature may damage the PI substrate caused device performance degradation and may be stressed or stripped. Figure 2-8 shows the local temperature distribution of a-Si:H TFT on glass substrate after the same bias stress condition. The highest temperature near the drain region is about 459.22K. Figure 2-9 shows the local temperature distribution of a-Si:H TFT on typical silicon substrate. The highest temperature near the drain region is only about 378.64K, because of the relatively higher thermal conductivity of silicon. For thermal accumulation effect during operation for PI substrate is more serious as. 24.

(33) compared with BSG glass and wafer substrate as shown in Figure 2-10. Note that, the origin of depth in our simulation is at the interface between a-Si:H and Si3N4. Figure 2-11 shows the maximum temperature of device and substrate. The substrates are PI, BSG and silicon wafer. If a-Si:H TFT fabricated on silicon wafer, we have the maximum temperature improvement of 80°C and 130°C as compared with on PI substrate, respectively, due to higher thermal conductivity of silicon wafer to dissipate more heat during operation. But the rigid silicon wafer is not suitable for flexible electronics applications.. Fig. 2-5. The diagram of heat flow path of a-Si:H TFT during operation.. 25.

(34) Fig. 2-6. The whole temperature distribution of a-Si:H TFT on PI substrate after bias. Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 26.

(35) Fig. 2-7. The temperature distribution of the a-Si:H TFT on PI substrate at the drain. and adjacent region after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μmand K). 27.

(36) Fig. 2-8. The temperature distribution of the a-Si:H TFT on glass substrate at the. drain and adjacent region after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 28.

(37) Fig. 2-9. The temperature distribution of the a-Si:H TFT on silicon substrate at the. drain and adjacent region after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 29.

(38) 480. Vg=6V, Vd=30V for 20sec. n+ a-Si:H. a-Si:H. Metal II. 450 420. PI. 390. BSG glass. 330. a-SiNx:H. 0.1. Buffer Oxide. 360. 300. Fig. 2-10. Substrate. Metal I. Temperature (K). a-SiN:H Metal I Buffer Oxide. wafer. Substrate. 1 Depth (m). 10. The temperature profile of vertical direction of a-Si:H TFT with PI, glass,. and wafer substrate.. Fig. 2-11. The device and substrate maximum temperature on different substrates (PI,. glass and wafer) and Vd.. 30.

(39) 2.4.2 a-Si:H TFT with Thermal Conduction Layer on Flexible Substrate From simulation results we have shown in 2.4.1, the flexible a-Si:H TFT on PI substrate which has amount of thermal accumulation during operation more than glass and silicon wafer. In this section, transient thermal profile and temperature distribution of flexible a-Si:H TFT with different thermal conduction layer by simulation would be demonstrated. The basic 2-D structure of flexible a-Si:H TFT with thermal conduction layer that we simulated by TCAD tools “ Floops”and “ Mdraw”as shown in Figure 2-12. Several kinds of thermal conduction layers which have higher thermal conductivity, such as Cu, Al, Mo and Si3N4, adding between the buffer oxide layer and the PI substrate. Note that thickness of every layer except thermal conduction layer is the same with Table 2-4. Figure 2-13 shows the heat flow path of flexible a-Si:H TFT with thermal conduction layer during operation. The thermal conduction layer can effective to dissipate accumulated heat along lateral direction due to higher thermal conductivity more than buffer oxide and PI substrate. Thus, the maximum temperature of flexible a-Si:H TFT with thermal conduction layer after bias stress operation also much lower than that without thermal conduction layer. Figure 2-14 shows the temperature distribution of a-Si:H TFT on PI substrate with 0.1μm-thick Cu for the thermal conduction layer with Vg = 6V & Vd = 30V for 20sec bias stress. The highest temperature near the drain region is about 431.61K, and lower 41.35K than that structure without thermal conduction layer under the same bias condition. Then, we also compare different thickness of Cu with 0.3μm and 0.5μm, and the temperature distribution is shown in Figure 2-15 and Figure 2-16. The highest temperature is 407.85K and 399.35K, respectively. This indicates the temperature improvement with thickness 0.3μm and 0.5μm of Cu is similar and much better than that of 0.1μm. Figure 2-17 shows the temperature profile of different thickness of Cu for thermal conduction layer. For the. 31.

(40) thickness 0.1μm, 0.3μm and 0.5μm of Cu, the temperature difference across the buffer oxide layer are ~13 °C, ~23 °C and ~23 °C, respectively. Therefore, consider the process compatible with 0.3μm of Cu thermal conduction layer is more efficient to heat dissipation. Finally, we compare with heat dissipation by several kinds of materials including Cu, Al, Mo and Si3N4, which using as thermal conduction layer in flexible a-Si:H TFT. Figure 2-18 ~ Figure 2-20 show the temperature distribution of a-Si:H TFT on PI substrate with different material (Al, Mo and Si3N4) as thermal conduction layer and thickness are all the same 0.3μm. The maximum temperature of device after the same bias stress condition is 417.72K, 430.98K and 463.94K, respectively. The temperature profile of vertical direction of a-Si:H TFT on PI with different material (Cu, Al, Mo and Si3N4) as thermal conduction layer are shown in Figure 2-21. Note that all the thickness of thermal conduction layer is 0.3μm. The maximum temperature different of the device with Cu layer and without thermal conduction layer (only PI) is ~65°C at depth = 0μm, and the maximum PI temperature of Cu device (depth = 1.1μm for Cu/PI) is lower ~90°C as compared with that of no thermal conduction layer device (depth = 0.8μm for PI). Note that, the origin of depth in our simulation is at the interface between a-Si:H and a-SiNx:H. The thermal conduction layers have significant effect to heat dissipation due to higher thermal conductivity.. 32.

(41) Fig. 2-12. Illustration of localized a-Si:H TFT on PI substrate with thermal conduction. layer created by TCAD tools.. Fig. 2-13. The diagram of heat flow path of a-Si:H TFT on PI substrate with thermal. conduction layer during operation.. 33.

(42) Fig. 2-14. The temperature distribution of the a-Si:H TFT on PI substrate and with. 0.1μm Cu at the drain and adjacent region after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 34.



(45) Fig. 2-17. The temperature profile of along depth direction with thermal conduction. l aye rCu( 0. 1μm,0. 3μm and0. 5μm)on PI substrate after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 37.

(46) Fig. 2-18. The temperature distribution of the a-Si:H TFT on PI substrate and with. 0.3μm Al at the drain and adjacent region after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 38.

(47) Fig. 2-19. The temperature distribution of the a-Si:H TFT on PI substrate and with. 0.3μm Mo at the drain and adjacent region after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 39.

(48) Fig. 2-20. The temperature distribution of the a-Si:H TFT on PI substrate and with. 0.3μm Si3N4 at the drain and adjacent region after bias Vg = 6V & Vd = 30V for 20sec. (Unit: μm andK). 40.

(49) Fig. 2-21. The temperature profile of vertical direction for Cu/PI, Al/PI, and Mo/PI,. Si3N4/PI, and PI.. 41.

(50) 2.5 Summary In conclusions, this chapter we used TCAD simulation to understand heat accumulation in flexible a-Si:H TFT during bias stress operation and damage to PI substrate. Therefore, we report to design to have a thermal conduction layer between the buffer oxide layer and PI substrate for a-Si:H TFTs to dissipate the accumulated heat during operation and calculate the temperature distribution by TCAD. The materials, such as Cu, Al and Mo have the higher thermal conductivity, and result the significant effect to heat dissipation during the flexible electronics operation for AMOLED or other current stress bias applications.. 42.

(51) Chapter 3 Simulation of Thermal Accumulation Improvement for Fabrication Manufacturing of Monolithic 3D Integrated Circuits In recent years, 3D-ICs have been a notable technology and will apply to many aspects of IC integration extensively in the future [35]. However, to develop the 3-D technology suffered many difficulties in terms of process complexity. One of the challenges is the thermal budget in the fabrication process or during device operation. Therefore, consider that thermal effects may lead to damage to the device performance, many thermal analysis such as under the process during laser annealing [8] and device operation [36 –38] have proposed. In this chapter, the thermal accumulation improvement is based on laser epitaxial growth for monolithic 3D-ICs manufacturing. We propose one optimum structure including 1st layer device, Via interconnect and thermal conduction layer such as Cu in ILD oxide layer to avoid damaging to device and maintain the excellent crystal quality of Via interconnect and single crystal Si layer. With the conduction Cu layer, the Via depth can reduce to 200 nm, and the maximum temperature of the 1st layer poly gate and source/drain maintains as low as ~320K and ~350K, respectively, for laser re-crystallization annealing.. 3.1. The Structure for Thermal Accumulation Improvement in LEG. Process for 3D-ICs Consider the thermal accumulated effect during laser irradiation may cause the damage to 1st layer devices and maintain the excellent crystal quality of Si layer. The structure we proposed for improvement of thermal accumulation for laser irradiation as shown in Figure 3-1. The LEG process sequence that started with 1st layer of device, and we use the typical n-MOSFET structure in simulation. First, the 10nm thick of gate oxide layer and 190nm thick. 43.

(52) of poly-Si were deposited on silicon substrate in sequence. Next, one masking step is used to define the poly gate as well as to etch off the unmasked poly-Si layer. After the gate pattern is defined, the gate oxide layer was later etched off. The nitride (Si3N4) spacers were adding to protect poly gate and the constant doping profile as shown in Table 3-1. When the 1st layer of MOSFET structure is finished, the insulator layer (SiO2) and thermal conduction layer such as Cu are deposited. After Via hole etching, the single crystal Si was selective epitaxy growth (SEG) as seed for lateral epitaxial growth, then LPCVD amorphous Si deposition process is accomplished. The single crystal Si was formation from the seed and lateral growth by laser irradiation.. 44.

(53) Fig. 3-1. Schematic diagram of structure with thermal conduction layer for LEG. process.. Tab. 3-1. Constant doping profile of the MOSFET.. 45.

(54) 3.2 Device Modeling and Results Figure 3-2 shows the structure for thermal accumulation improvement, which is established by TCAD tools including 1st layer of n-MOSFET, Via interconnect and thermal conduction layer such as Cu in ILD oxide layer. When laser irradiated at the surface of a-Si, absorption coefficient of a-Si would be considered [39]. The Figure 3-3 is a graph showing a relation between optic wavelength and absorption coefficient for amorphous silicon and crystallized silicon [40]. There is a higher absorption coefficient about 106 cm-1 of amorphous silicon film at optic wavelength of 308nm. Regardless of the quality of a silicon film to be irradiated, energy of laser is absorbed on the surface and causes large temperature gradient in the film thickness direction. Thermal properties for crystallized silicon, amorphous silicon, silicon dioxide and copper we used in simulation as shown in Table 3-2 [41]. Note that value of thermal conductivity for a-Si independent temperature in our work is 1.5x10-2 W/K-cm. Figure 3-4 shows the local temperature distribution of the structure with amorphous Si / ILD (50 nm / 500 nm) on 1st layer devices, and Via during laser irradiation by TCAD simulation. The excimer laser beam with a wavelength of 308 nm and the energy density is preferably set to 300mJ/cm2. The duration time is 20 ns and the irradiated window on surface of a-Si is from -1.5 μmto 0 μmat x-coordinate. The thick oxide has much lower thermal conductivity can prevent the heat dissipation to 1st layer and protect MOSFET device at room temperature (300K). The temperature of a-Si layer is much more than 1418K which is the melting point of a-Si to mean that a-Si layer can be sufficiently melted. However, the temperature of bottom of Via hole is too low to re-crystallization and form single crystal Si completely.. 46.

(55) Fig. 3-2. Schematic diagram of structure with thermal conduction layer for LEG. process by TCAD simulation. 47.

(56) Fig. 3-3. Diagram of relation between optic wavelength and absorption coefficient for. amorphous silicon and crystallized silicon.. Tab. 3-2. Thermal properties for materials we used in simulation.. 48.

(57) Fig. 3-4. The temperature distribution of the structure with amorphous Si / ILD (50. nm / 500 nm) on 1st layer devices, and Via during laser irradiation by TCAD simulation. (Unit: m and K). 49.

(58) In order to maintain the re-crystallization quality, the Via depth and ILD thickness decreased are necessary. Figure 3-5 shows the temperature distribution with the same laser energy for decreased ILD thickness (200 nm). Heat generated in the a-Si layer by the irradiation of the laser beam conducts toward the substrate. For the maximum temperature (t=20ns), the temperature at the top of the poly gate is attained to 420K, and about 464K at the top of the source/drain region may cause the source/drain doping diffusion and destruction the junction profile. Therefore, we propose a thermal conduction layer, which has higher thermal conductivity such as Cu, in ILD oxide to help the heat dissipation during laser irradiation. The temperature distribution was shown in Figure 3-6, in which the thickness of Cu is 10nm. Since the metal layer having high thermal conductivity is provided between the ILD oxide layer, heat stored in the a-Si layer and ILD oxide dissipates through the metal layer. From Figure 3-5 and Figure 3-6, the temperature at the top of the poly gate and source/drain region has been improved 93K and 102K, respectively, since the Cu layer assists the amount of heat to dissipate along lateral direction. There is no significant temperature difference of Via hole and Si layer between with and without Cu layer. This indicates that the addition thermal conduction layer would not degrade the re-crystallization quality of the Si layer. Figure 3-7 (a) shows the temperature profile of the structure with Cu and without Cu slices a dotted line “ a”in Figure 3-5 and Figure 3-6. The thickness of SiO2 is 200 nm and Cu is 10 nm. Figure 3-7 (b) shows the temperature profile of the structure with Cu and without Cu slices a dotted line “ a’”in Figure 3-5 and Figure 3-6. The maximum temperature at device region was improved more than 90K by thermal conduction layer to dissipate extra heat. With the conduction Cu layer, the Via depth can reduce to 200 nm, and the maximum temperature of the 1st layer at poly gate and source/drain maintains as low as ~320K and ~350K, respectively.. 50.

(59) Figure 3-8 (a) and (b) shows the Cu thickness and location effect, respectively. Figure 3-8 (a) shows temperature difference (-ΔT)a tpol yga t ea nds our c e / dr a i nr e g i onoft hes t r uc t ur e wi t houtCua ndwi t hCuf ordi f f e r e ntt hi c kne s sa l ong“ a ”a nd“ a ’” .Thedi s t a nc ebe t we e nCu a nduppe rSil a y e ri sf i xe df or0. 1μm.Thet hi c ke rCuha smor ei mpr ove me ntf ort hickness 0. 3μm.Figure 3-8 (b) shows temperature difference (-ΔT)a tpol yga t ea nds our c e / dr a i n region of the structure with Cu=10nm for different distance between Cu and upper Si layer a l ong“ a ”a nd“ a ’” .Al lt e mpe r a t ur ec a nbei mpr ove dmor et ha n90K a tdifferent distance between Cu and upper Si layer.. 51.

(60) Fig. 3-5. The temperature distribution with laser energy (300 mJ/cm2) for decreased. ILD thickness (200 nm). (Unit: m and K). 52.

(61) Fig. 3-6. The temperature distribution with laser energy (300 mJ/cm2) for ILD. thickness (200 nm) and a thermal conduction layer (10nm). (Unit: m and K). 53.

(62) 1800. tSiO = 0.2um w/o Cu w/ Cu (0.01um). Temperature (K). 1600. 2. 1400 1200 1000 800 600 400 200. Gate upper layer. Substrate. SiO2. -0.2. -0.1 0.0 Depth (m). 0.1. Temperature (K). (a). 1800 1600 1400 1200 1000 800 600 400 200. tSiO = 0.2um w/o Cu w/ Cu (0.01um) 2. Source/ Drain upper layer. -0.2. Substrate. SiO2. -0.1 0.0 Depth (m). 0.1. (b) Fig. 3-7. The temperature profile with and without thermal conduction Cu layer along. the direction (a) poly gate region “a”in Figure 3-5 and Figure 3-6, and (b) source/drain region “a’”in Figure 3-5 and Figure 3-6.. 54.

(63) -Δ T( K)(Tw/o Cu-Tw/ Cu). 120 115 110. dCu to upper layer = 0.1m Source/Drain Gate , a. 105 100. a. 95 90. 0.010 0.015 0.020 0.025 0.030 Cu thickness ( m) (a). -Δ T( K)(Tw/o Cu-Tw/ Cu). 120 tCu = 0.01m Source/Drain Gate. 115 110 a. 105. ,. 100 95. a. 90 85. 0.02. 0.04 0.06 0.08 dCu to upper layer (m). 0.10. (b) Fig. 3-8. The temperature difference at the poly gate and source/drain region for (a). different thickness of Cu, and (b) difference distance between Cu to upper Si layer.. 55.

(64) 3.3 Summary In 3D-IC architecture by LEG process, ILD oxide which is low-k dielectrics with poor thermal conductivity, will not only lead to lower Via temperature but also impact the device temperature in 1st layer. Therefore, we propose one structure which has a thermal conduction layer such as Cu in ILD oxide layer with LEG technology for 3D-ICs manufacturing. To reduce the Via depth and ILD oxide thickness can improve the re-crystallization quality for upper Si layer. The thermal conduction layer, which has higher thermal conductivity can efficient to dissipate the accumulated heat during laser irradiation. With the conduction Cu layer, the Via depth can reduce to 200 nm, and the maximum temperature of the 1st layer poly gate and source/drain maintains as low as ~320K and ~350K, respectively, for laser re-crystallization annealing. The heat due to laser irradiation also dissipate through the Via and the temperature of Via hole is sufficient to form good quality upper Si layer.. 56.

(65) Chapter 4. Fabrication Process of One Mask MOSFET and Via. Hole Design for 3D-IC Applications. 4.1 One Mask MOSFET Fabrication Flow In this section, we make a description of the whole device manufacturing process flows, which is accomplished in National Nano Device Laboratories (NDL). First, 300nm thick of silicon oxide thin film was deposited on N type and P type silicon wafer respectively by dissociation of TEOS (Tetra-Ethyl-Ortho-Silicate, Si(OC2H5)4) at 700°C in a low-pressure chemical vapor deposition (LPCVD) system. 50nm thick of Al-Si-Cu alloy was subsequently deposited by ULVAC sputter in which used for metal gate. Next, source and drain regions was patterned by lithography technique with one mask definition, then removed metal and oxide in sequence. Note that we used B.O.E (NH4F : HF = 15 : 1) to carry out oxide wet etching. Before started to etch, we must measure the etching rate of B.O.E solution in advance due to different oxide thin films with different porosities may lead to various etching rate. The etching rate of TEOS we estimated is about 1.04nm/sec at room temperature. In addition, wet etching is also isotropic caused pattern profile undercut in oxide layer, as shown in Figure 4-1. After patterning is completed, implantation is proceeded with Arsenic (40k eV at 6 x 1015 cm-2) and BF2 (30k eV at 5 x 1015 cm-2) for NMOS and PMOS, respectively, as shown in Figure 4-2. Finally, dopant activated at 450 °C for 2 hours annealing in a 5% H2 /N2 ambient. The overview of the one mask MOSFET after all process flow was shown in Figure 4-3. The current characteristics of pn junction (B/D junction) of device we measured as shown in Figure 4-4. We can improve the fabrication process of one mask MOSFET with lift-off process in future works.. 57.

(66) Fig. 4-1. The cross section of the one mask process device. The undercut in oxide layer. is due to wet etching.. Fig. 4-2. Process flow –source/drain with Arsenic for NMOS and BF2 for PMOS. implantation, respectively.. 58.

(67) Fig. 4-3. The overview of the one mask MOSFET after all process flow.. 2. 10. r=200 m r=50 m. 1. 2. J (A/cm ). 10. 0. 10. -1. 10. -2. 10. -3. 10. -4. 10 -1.0 Fig. 4-4. -0.5. 0.0 Vd (V). 0.5. 1.0. The current characteristics of pn junction (B/D junction).. 59.

(68) 4.2 Process Principles In this section, the process principles of instruments in our work are made a detailed description as follows.. 4.2.1 Wafer Cleaning and Wet Etching In semiconductor device manufacturing process, the cleanliness and clean technique of wafer played an important role may to influence on yield, quality and reliability of devices. The major purpose of wafer cleaning is to remove all contaminants on wafer surface such as particles, organic matters, inorganic matters and metal-ions. In NDL, the utilized occasion can distinguish from pre-furnace clean, photo-resist remove and metal layer photo-resist strip. As below, we make a description of standard process items that we had used to fabricate our device in NDL class 100. The outward appearance of equipment is shown in Figure 4-4. (a) pre-furnace clean: (1) SPM (H2SO4 : H2O2 = 3 : 1) : 120°C, 600sec. (2) SC-1 (NH4OH : H2O2 : H2O = 1 : 4 : 20) : 75~85°C, 600sec. (3) SC-2 (HCl : H2O2 : H2O = 1 : 1 : 6): 75~85°C, 600sec. (4) DHF (HF : H2O = 1 : 50): room temperature, 60sec. (b) metal layer photo-resist strip: Rize-68: 50°C, 600sec. In addition, silicon oxide wet etching was implemented by back-end wet bench in NDL class 1000. The outward appearance of equipment is shown in Figure 4-5. (c) silicon oxide (contain metal) wet etching: B.O.E (NH4F : HF = 15 : 1, Receipe 3): room temperature, 270sec. The chemical reactive equation is as below: 60.

(69) SiO2 +6HF→ H2SiF6 + 2H2O2 The standard clean steps for different process conditions are as follows: (1) after laser marker cleaning: SC-1 → QDR(Quick Dump Rinse) → SPIN / DRYER (2) standard (STD) clean: SC-1 → QDR→ SC-2 → QDR → SPIN / DRYER (3) pre-metal sputter cleaning: SC-1 → QDR → SC-2 → QDR → DHF → QDR → SPIN / DRYER. 61.

(70) Fig. 4-4. The outward appearance of wet bench in NDL class 100.. Fig. 4-5. The outward appearance of wet bench in NDL class 1000.. 62.

(71) 4.2.2 Deposition Process and Thermal Annealing In this thesis, thin film deposition process of our device involves silicon dioxide (SiO2) and Al-Si-Cu alloy. The silicon dioxide layer deposition we used TEOS by LPCVD system in NDL. Standard process items are illustrated as Table 4-1. The scientific name of TEOS is known as Tetra-Ethyl-Ortho-Silicate, which is an organic silicide in the existence of solution at room temperature and atmospheric pressure. TEOS is deposited extensively applied for spacer in semiconductor process because of its good step coverage, and often used to be Inter-Metal Dielectric (IMD), passivation and Inter-Poly Dielectric (IPD) between poly silicon layers. In our experiment, we used TEOS for buried oxide due to its better flatness of surface and good step coverage. Note when deposition was started, proper heating to reach about 50°C needed to enhance saturated vapor pressure of TEOS. At elevated temperature (700 °C) and low pressure (300 mTorr), TEOS converts to silicon dioxide: Si(OC2H5)4 → Si O2 + 4C2H4 + 2H2O Next, we explain the deposition process of Al-Si-Cu alloy by ULVAC sputter in NDL. Al-Si-Cu is alloy of aluminum with 1% Si and 0.5% Cu, and 50nm thick of Al-Si-Cu alloy was deposited for metal gate in our experiment. Under the DC plasma for sputtering source, Ar plasma hit the metal target and sputtered the metal atom to the substrate. Al-Si-Cu is a suitable IC interconnect material because of its low resistance and compatible to the conventional IC process. It provides a self-protected oxidized layer (Al2O3) to prevent continuing oxidation. Owing to its low resistance and suitable work function, Al-Si-Cu is also applied to be the metal pad in device fabrication. The standard process conditions are shown in Table 4-2. On the other hand, an H2 sinter is generally performed to compensate for a generation recombination center such as an interface state between Si and SiO2 interface region. This H2 sinter is normally performed before an Al film is deposited and after Al 63.

(72) wiring contact hole is formed. [42]. Tab. 4-1. Tab. 4-2. Standard process items of LPCVD system in NDL.. Standard process conditions of ULVAC sputter in NDL.. 64.

(73) 4.2.3 Lithography Process After deposition process completed, lithography technique proceeded with the transfer of a pattern to a photosensitive material (photo-resist) by selective exposure to a radiation source such as light. A photosensitive material is a material that experiences a change in its physical properties when exposed to a radiation source. We selectively expose a photosensitive material to radiation the pattern by only one mask definition. To manufacture the mask, we first designed the layout by draw type layout editor (L-Edit). The smallest critical dimension is 0.4 μm. When drawing is finished, we must transfer the data profile to GDS format. Then we used JEOL e-beam to implement mask manufacturing. The JBX-5DII electron beam lithography system employs high-brightness electron gun of single-crystal LaB6 cathode and an in-lens deflector. This feature allows forming an electron beam spot with a diameter as small as hundreds of angstroms, enabling efficient submicron writing. Clean Track MK8 in NDL carried out the coat of photo-resist and development, and outward appearance of equipment is shown in Figure 4-6. Clean Track MK8 is an automatic photo-resist coating (pre-exposure treatment) and developing (post-exposure treatment) equipment for lithography processes. The standard process flow is HMDS treatment, photo-resist coating, pre-bake, exposure, post-bake, development and hard bake. For completing the processes, there are 1 adhesion unit, 1 coater units, 4 hot-plate units, 2 cooling plate units and 1 developer unit in the system. In our experiment, we used I-line resist coating and I-line resist development. In exposure step, we used I-line stepper (Canon FPA 3000 i5+) as shown in Figure 4-7. The exposure parameters required in order to achieve accurate pattern transfer from the mask to the photosensitive layer depend primarily on the wavelength of the radiation source and the dose required achieving the desired properties change of the photo-resist. We set the dose energy density is 1700 mJ/m2, and one piece of wafer can repeat to expose 32 patterns from 65.

(74) mask to photo-resist layer. After develop inspection (ADI), we used the In-line SEM and optical microscopy (OM) to check the pattern to be measured is presented in a bright high-resolution TV image via the field emission electron gun, allowing quick and highly accurate measurement. The outward appearance of In-line SEM is shown in Figure 4-8.. Fig. 4-6. Front view of Clean Track MK8.. 66.

(75) Fig. 4-7. The outward appearance of I-line stepper.. Fig. 4-8. The outward appearance of In-line SEM.. 67.

(76) 4.3 Design of Via Interconnect for 3D-IC Applications In 3D-IC fabrication process, Via interconnects realization between heterogeneous layers play an important role cause process complicated and affect the characteristics of devices. Several thousands or several tens of thousands of Via holes are present in devices, and many information signals can be transferred from higher to lower layers through them [43]. The size of a Via hole was 1~2 μm square shape with a height of 2~3 μmfor selective growth or deposition of conductive materials and an accurate etching technology in 1980s [44], and the spacing between the holes was3μm [45]. Thus, considered different parameters such as shape, size and spacing of the Via interconnects may affected epitaxial quality of a-Si in LEG process, we have designed a mask pattern with several kinds of Via hole arrays by L-Edit. The shapes of Via holes we used circle, square and regular hexagon. The sizes (diameter for circle, rim for square and regular hexagon) are 0.4, 0.6, 0.8, 1, 2, 5, 10 μm, and spacing are 0.5, 1, 2, 3, 5 μm. Therefore, there are total 105 columns of Via hole arrays drawn in a section of 18000μm x 18000μm range. The layout of mask pattern is shown in Figure 4-9, and an illustration of Via hole arrays is shown in Figure 4-10. This mask will be used for Via interconnect implementation in future works.. 68.

(77) Fig. 4-9. Illustration of layout for Via hole arrays with different parameters.. Fig. 4-10. Illustration of Via hole arrays.. 69.