Effect of growth temperature on APDs formation

As shown in Fig. 5-2, the GaAs crystal is composed of two sublattices, each face centered cubic (FCC) and offset with respect to each other by half the diagonal of the FCC cube. This crystal configuration is known as cubic sphalerite or zinc blende. The two possible sublattice locations of the GaAs epitaxy on Ge are shown in Fig. 5-3. The “GaAs-A” domain corresponds to the first atomic layer on the Ge surface is arsenic (As), while “GaAs-B” means that the first atomic layer on the Ge substrate surface is gallium (Ga). The different between GaAs-A and GaAs-B is the arrangement of their polar [111] axes, that is, a reversal of the location of the As and Ga atoms in sublattices. At a growth temperature that is closer to the interface between GaAs-A and GaAs-B as shown in Fig. 5-4, larger APDs will be formed during the GaAs/Ge heterostructure growth. The transformation of APD-free to APDs to APD-free with increment of growth temperature has been reported [6]. According to the

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experimental results by M. K. Hudait et al. [7], half maximum (FWHM) of GaAs peak of GaAs/Ge heterostructure can be reduced from 50.8 arcsec to 45.5 arcsec when growth temperature is increased from 600°C to 650°C. The narrowness of the FWHM of GaAs epitaxial film indicates the microstructure quality of the film is improved. The influence of the growth temperature on the surface morphology of GaAs/Ge heterostructure can be seen in Fig.

5-5. The two-dimensional (2D) and three-dimensional (3D) AFM topographical images of 3μm×3μm scanning sizes are shown in Fig. 5-5 as a function of growth temperature at 650°C and 750°C, respectively. It can be observed that a much smoother surface is achieved for the sample grown at higher growth temperature. According to the references in [4,6,7], we know that growth temperature is very important issue for GaAs/Ge heterostructure using Metalorganic Chemical Vapor Deposition (MOCVD). More APDs will be generated at the interface between GaAs and Ge epitaxy when inappropriate growth temperature was adopted.

5.1.1.2 Effect of misoriented substrate on APDs formation

Both two orientations (GaAs-A and GaAs-B) of GaAs epitaxy are nucleated on Ge substrate, distinct domains of each sunlattice, separated by anti-phase boundaries (APBs) may propagate well into the GaAs epitaxy. In order to suppress APDs formation the control of the substrate surface is also an efficient way. The surface of non-polar semiconductor materials such Ge and Si is characterized by dimer reconstructed terraces separated by step [9-11].

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Pairing, or dimerization, of adjacent fourfold coordinated Ge atoms exposed on the (100) surface which reduces the number of dangling bonds per atom from two to one. The physical equation describes the relationship of steps density variation as a function of misorientation angles as shown in equation (5-1):

ω= h tan^-1φ (5-1) Where the ω is the density of steps on the surface; h is the height of the step; φ is the misorientation angles. Equation (5-1) shows that higher misorientation angles may promote the generation of steps on the surface to reduce APDs formation. Fig. 5-6 displays TEM images of GaAs grown on Ge substrate with different misorientation angles (6° and 0°). It is observed clearly GaAs grown on 6° off Ge substrate do not have APDs generation around the GaAs/Ge interface; on the contrary, the penetration of APDs from Ge layer to GaAs is also observed when 0° off Ge substrate was adopted [5]. L. Lazzarini et al. [12] also verified that lower misorientation angles (≦4°off) may result in APDs formation during GaAs/Ge

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(b) The nuclei formed on the surface, GaAs-B, have the reversed sublattice location.

For Ge substrate with a larger misorientation angle, of which the surface between the steps are very narrow, the steps are so close that no nucleus can be formed on the surface, as shown in Fig. 5-7(a). The nuclei at the steps can coalesce soon. Overgrowth on such surface may result single domain GaAs with the sublattice orientation being the same as the initially nucleated one, the GaAs-A, and a smooth surface is obtained, as shown in Fig. 5-7(b). For Ge substrate with a small misorientation angle of which the width of the terraces between the steps is larger than that of lager disorientation angle, nuclei formed on the terraces will dominate, as shown in Fig. 5-7(c). The nuclei at the steps will be surrounded by the nuclei on the terrace so that they are not able to connect with each other. Overgrowth on such surface may have the result that initially nucleated GaAs at the steps may become less dominant during further growth and at last will annihilate, as shown in Fig. 5-7(d). According to the growth mechanism mentioned above, the suppression of APDs formation can be achieve using Ge substrate with higher misorientation angles (≧4°off)) during GaAs/Ge heterostructure growth.

5.1.1.3 Effect of high-temperature substrate annealing on APDs formation

High-temperature substrate annealing process carried out prior GaAs epitaxial growth is also another efficient way to suppress APDs formation during GaAs/Ge heterostructure

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growth. This way is related to the transformation of steps states on the Ge surface being similar to the mechanism of misoriented substrates. The difference in surface steps generation between substrate annealing and misoriented substrates is growth-temperature gradient. The step numbers of misoriented Ge surface is stable than substrate annealing technique because we can choose Ge substrate with higher misorientation angles before GaAs/Ge heterostructure growth. If you want to change the configuration of surface steps existed originally on misoriented Ge surface to suppress APDs formation, the substrate annealing process is a good choice. The detailed description of high-temperature substrate annealing will be discussed in the following.

The purpose for high-temperature substrate annealing process can be separated into two parts: (a) it can remove native oxide on the Ge surface before the growth. (b) it can transform the single-step configuration into desired double-step surface state on the Ge substrates. The Ge substrate without substrate annealing may result in APDs formation near the interface of GaAs/Ge heterostructure as shown in Fig. 5-8(a) [14]. On the contrary, no APDs formation is achieved for GaAs epitaxy grown on Ge substrate annealed at 640°C as shown in Fig. 5-8(b).

Here, we know that annealing temperature is key point for substrate annealing process. High temperature annealing induces a favorable surface transition equivalent to the use of misoriented Ge substrates.

The transformation of surface steps for substrate annealing process, illustrated in Fig. 5-9,

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along [110] directions lead to reflection of Ge surface from the original (100) orientation. A single atomic-layer steps, shown in Fig. 5-9(a), feature single or any odd-integer number of steps, such that on alternating terraces, the exposed sublattice domain shifts, rotating the dimer bond by 90°. For S_A (“S” is single-layer steps) steps the dimerization axis on the upper terrace is perpendicular to the step edge, whereas S_B steps means that the dimerization axis on the upper terrace is parallel to step edge. As shown in Fig. 5-9(b), this configuration consist of double atomic-layer steps (D_A and D_B: D is double-layer steps), or even-number layer steps, separating terraces of the same exposed sublattice where all dimmers lie parallel to the step edges. In this case, the configuration of D_B steps is favorable than D_A steps owing to the different in energy as shown in Table 5-2 [15]. On the other hand, the step formation energy of DB is also lower than that of SA＋S_B. It means that high-temperature substrate annealing may transfer single-layer steps into double-layer steps [16].

In general, the abovementioned methods induce atomic surface steps on the Gesubstrate.

The formation of surface steps can boost the single-domain GaAs-A growth, in which the first atomic layer on the surface of Ge layer is arsenic (As) atoms, and promote the self-annihilation of APDs during GaAs/Ge heterostructure growth. Besides, Luo et al. [5] also pointed out that anti-phase boundaries (APBs) in the GaAs/Ge heterostructure were the routes for Ge diffusion into the GaAs layer. They demonstrated that termination of APD formation led to reduction in the interdiffusion in the GaAs/Ge heterostructure.

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5.1.2 Interdiffusion between GaAs and Ge epitaxy

The optimal growth temperature for GaAs epitaxial growth using MOCVD is about 650°C, whereas the growth temperature for Ge epitaxy is about 400°C [17]. The different in optimal growth temperature between GaAs and Ge epitaxy is a stern challenge during GaAs/Ge heterostructure growth. The atoms of Ga and As in GaAs epitaxy will diffuse into Ge layer which forms unwanted P-N junction in Ge epitaxy. Moreover, Ge atoms in Ge layer also diffuse into GaAs layer which forms N-type layer in GaAs epitaxy due to the use of higher growth temperature. The unwanted P-N junction in subcells of III-V multijunction solar cells will seriously cause a short circuit and affect the conversion efficiency. In order to decrease the interdiffusion probability of As and Ge atoms, a low-temperature epitaxial technique and various interfacial layers such as AlAs, Ga, and As [18,19] were used for the GaAs/Ge heterostructure growth.

5.1.2.1 Low-temperature epitaxial technique

The diffusion mechanism of GaAs/Ge heterostructure is well described by Arrhenius equation [20] as shown in equation (5-2).

D=D0 exp(-Ea/kBT) (5-2) Where D0 is pre-exponential factor, Ea is activation energy, kB is Boltzmann’s constant and T is the absolute growth temperature. The equation shows the diffusion probability

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exponentially dependents on growth temperature and thus the use of lower growth temperature can efficiently decrease the interdiffusion probability of Ga, As and Ge atoms during GaAs/Ge heterostructure growth. The diffusion length of As atoms is deeper than Ga atoms for high-temperature GaAs growth [21] as shown in Fig. 5-10 and therefore the suppression of As interdiffusion from GaAs to Ge layer is main challenge than that of Ga and Ge atoms. The concentration of excess As in a GaAs epitaxy grown at the low substrate temperature by Molecular-beam Epitaxy (MBE) is extremely large in comparison with those in the equilibrium phase diagram where the concentration of excess As is only 0.1% at the melting point [22]. However, the low-temperature growth of GaAs on the Ge layer led to the formation of GaAs-B domain, which generated APDs in the GaAs layer, and As-antisite defects on the terraces [4,23]. In this thesis we have to further consider the growth temperature related to the APDs formation and interdiffusion problems during GaAs/Ge heterostructure.

5.1.2.2 The insertion of As, Ga, and AlAs prelayers between GaAs and Ge layers

It is known that the interdiffusion occurs easily at GaAs-Ge heterointerface. To avoid the interdiffusion of As, Ga, Ge atoms during GaAs/Ge heterostructure growth, an alternative to growth of GaAs on Ge layers is to use a prelayer, which creates a near-GaAs lattice constant but has few defects. Recently many materials such as AlAs, Ga and As were used as prelayers

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[18,19,24,25 ]. An AlAs prelayer grown on Ge substrate prior GaAs epitaxy can suppress the interdiffusion because of high bonding energy. If unwanted interdiffusion occurs during GaAs/Ge heterostructure, the atomic bonds in GaAs epitaxy must be broken and then diffused into Ge substrate. The bonding energy of Al-As in the AlAs prelayer is higher than that of Ga-As. Thus, the AlAs prelayer suppresses efficiently the interdiffusion of Ge atoms as shown in Fig. 5-11. On the other hand, Ga and As prelayers are also the candidate for suppressing interdiffusion during GaAs/Ge heterostructure growth. According to the experimental results by B. Galiana et al. [19], the initiation of GaAs with the typical procedure of using a Ga prelayer decreases the As diffusion into Ge substrate as well as the Ge diffusion into the GaAs epitaxy and results in improved solar cell characteristics.

Although a thin AlAs prelayer grown between GaAs and Ge epitaxy suppressed the interdiffusion of Ge atoms, diffusion of Al atoms into the GaAs epitaxy was observed at higher growth temperatures (>540°C) [18]. In contrast, the growth of the Ga prelayer between Ge and GaAs epitaxy decreased the As and Ge interdiffusion as compared to the growth of As prelayer [19], but the APD formation in GaAs/Ge system was difficult to avoid. Since Ga prelayer tends to aggregate easily, As prelayer is preferred to manage uniform coverage on the Ge surface. Therefore, controlling the growth temperature and As flux is a very important concept to realize single-phase GaAs growth. However, arsenic atoms tend to interact with Si or Ge surfaces and change surface reconstructions to reduce the number of dangling bonds

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[26,27].Several researchers have reported As–As dimers form on the Si surface [27-29].Some of these results are, however, contradictory in defining which growth condition produces different orientations of As dimers (perpendicular or parallel to the step edges) on vicinal Si surfaces. Bringans et al. [26] described that As dimers could be added to a Si surface with an orientation that was perpendicular to step edges for substrate temperature in the range 400–600 °C, and the surface had predominantly double-layer steps.

5.2 Experiment

In this part we present the use of an As prelayer grown using graded-temperature technique for the suppression of APD formation. This layer is also found to improve the surface morphology and reduce the interdiffusion during the GaAs/Ge/Si heterostructure growth. All samples in this study were grown by low-pressure metal organic chemical vapor deposition (MOCVD, EMCORE D180) using trimethylgallium (TMG) and arsine (AsH₃) as the source materials. The substrates used were the Ge epitaxy on Si (001) substrate with 4° off misorientation toward the [110] direction. A detailed description of the growth of Ge epitaxy on Si substrate can be found elsewhere [30]. The As prelayer was deposited onto the Ge epitaxy while the substrate temperature was ramped from 300 to 420°C. Then, GaAs layers with different V/III ratios (11~75) were grown on the As/Ge/Si heterostructure by a low-temperature epitaxial technique (450°C). The Ge/Si substrate was annealed at 650 °C to

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generate atomic surface steps before the GaAs/As epitaxial growth [3]. All parameters in this study are shown in Fig. 5-12. The surface morphology of the GaAs/Ge/Si heterostructure with graded-temperature As prelayer was examined using atomic force microscopy (AFM). The threading dislocation density and crystalline quality of the grown sample was estimated using transmission electron microscopy (TEM) and high resolution X-ray diffraction (HRXRD), respectively. Finally, the interdiffusion of Ga, Ge and As atoms in the samples was determined by secondary ion mass spectrometry (SIMS).

5.3 Results and discussion

In this part, all of samples were predeposited on the Ge/Si substrate using graded-temperature As prelayer. To suppress the unwanted interdiffusion while maintaining lower APDs formation, the graded-temperature As prelayer was inserted between GaAs and Ge epitaxy. Besides, the effect of III-V ratio, growth temperature and annealing process on the GaAs/As/Ge/Si heterostructure are also discussed in the following.

5.3.1 Effect of V/III ratios on the surface morphology of GaAs grown on Ge/Si substrate using graded-temperature arsenic prelayer

Figure 5-13 illustrates the AFM images of the GaAs/As epitaxy grown on the Ge/Si heterostructure. The root mean square (RMS) roughness of the samples was about 7.0, 2.3,

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12.1, 15.6, and 21.7nm for the GaAs layers grown with V/III ratios of 11, 20, 30, 50, and 75, respectively. A large variation in the surface roughness with hill-and-valley structures was observed for the samples grown with inappropriate V/III ratios.

At the low V/III ratio of 11 (i.e., lower As flow), the possibility of Ga atoms being incorporated into GaAs epitaxy exceeds that of As atoms, leading to poor surface morphology and APD formation [31,32]. For V/III ratios larger than 30, the surface morphology becomes rougher because of the different growth rates at different growth orientations [33]. The growth rate of GaAs epitaxy in the [110] direction is faster than that in the [-110] direction for higher V/III ratios and at lower growth temperature [33,34]. The arsine dependence of the [110] and [-110] growth rates under constant TMGa partial pressure is represented in Fig. 5-14. The [-110] growth rate as well as the vertical growth rate are almost constant in the [AsH₃] range of 1.1×10^-4 to 3.7×10^-3 atm, corresponding to [AsH3]/[TMG]=1.7-58. The [110] growth rate also remained constant above [AsH3] of 1.8×10-3 atm, but it decreased below this [AsH3]. It is noteworthy that crossing between the [110] and [-110] growth rate occurs around an [AsH₃] of 4×10^-4 atm. The remarkable results obtained in this study are summarized in the following.

(A) The [110] growth rate is higher than [-110] at high V/III ratio and low growth temperature.

(B) The [110] growth rate decreases with decreasing [AsH3] partial pressure, while [-110]

growth rate remains constant.

At high V/III ratio and low growth temperature, a large number of As species impinge

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onto a Ge epitaxial surface and the desorption probability for As species is low. In this condition the Ge epitaxial surface is considered to be covered with As species. Fig. 5-15 shows the cross sections of the [110] and [-110] steps. According to this model, we found that the probability of As incorporation into the step sits is higher than that on flat Ge epitaxial surface, migrating Ga atoms are easily caught at the [110] and [-110] steps. Here, the Ga atom caught at the [110] steps is bound with three bonds; one to step side and two to the step bottom, while the Ga at the [-110] steps is bound with two bonds; both to the step bottom as shown in Fig. 5-15. It is clear from the model shown in Fig. 5-15 that migrating Ga atoms can be easily incorporated into the [110] steps than [-110] steps. Therefore, the [110] growth rate is higher than [-110] at high V/III ratio and low growth temperature.

It is known that a high V/III ratio is required for the growth of the GaAs/Ge/(Si) heterostructure without any interfacial layer [31,35]. The results shown in Fig. 5-13(a)~(e) indicate that the graded-temperature As prelayer sufficiently improves the surface morphology of GaAs epitaxy grown on Ge/Si substrate at a low V/III ratio of 20, even at a growth temperature of 450°C. This growth technology can effectively decrease the cost for GaAs/Ge/Si heterostructure growth.

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5.3.2 Effect of high-temperature substrate annealing on the quality of GaAs grown on Ge/Si substrate using graded-temperature arsenic prelayer

Controlling the surface structure is another efficient way to suppress APD formation prior to the GaAs growth [3]. Figure 5-16 illustrates the cross-sectional TEM images of the GaAs epitaxy (V/III: 20) grown on the Ge/Si heterostructure using a graded-temperature As prelayer.

It can be seen that many APDs were formed in the GaAs layer on the unannealed Ge/Si demonstrated that the smallest RMS roughness of 1.1nm was achieved for the samples grown using the graded-temperature As prelayer with substrate annealing process at 650°C, as shown in Fig. 5-13(f). Experiments confirmed that annealing the Ge/Si substrate at >600°C before dropping to the nucleation temperature is essential for single-domain GaAs growth.

According to the reference [4,23] described before, maybe GaAs-B is the dominant when the growth temperature was reduced from 650°C to 420°C in this study. However, it should be noted that the configuration of double atomic-layersteps as shown in 5-9(b) is favorable than single atomic-layersteps owing to the different in energy as shown in Table 5-2 [15]. On the

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other hand, the step formation energy of double atomic-layer stepsis also lower than that of single atomic-layer steps when high-temperature substrate annealing was adopted. It means that high-temperature substrate annealing may transfer single-layer steps into double-layer steps [16]. Therefore, surface transition kinetics are most likely to be limited upon cooling to high temperature. The temperature-dependent surface transition that normally leads to GaAs-B nucleation elsewhere has been quenched, and that the high temperature preference for GaAs-A has been preserved.

Growth temperature including annealing temperature is very important parameter for GaAs/Ge/Si heterostructure. In normal condition, which means that no As prelayer was used

Growth temperature including annealing temperature is very important parameter for GaAs/Ge/Si heterostructure. In normal condition, which means that no As prelayer was used