Chapter 5 Growth of GaAs Epitaxy on Ge/Si Substrates using
5.3.2 Effect of high-temperature substrate annealing on the quality of GaAs grown
Controlling the surface structure is another efficient way to suppress APD formation prior to the GaAs growth [3]. Figure 5-16 illustrates the cross-sectional TEM images of the GaAs epitaxy (V/III: 20) grown on the Ge/Si heterostructure using a graded-temperature As prelayer.
It can be seen that many APDs were formed in the GaAs layer on the unannealed Ge/Si demonstrated that the smallest RMS roughness of 1.1nm was achieved for the samples grown using the graded-temperature As prelayer with substrate annealing process at 650°C, as shown in Fig. 5-13(f). Experiments confirmed that annealing the Ge/Si substrate at >600°C before dropping to the nucleation temperature is essential for single-domain GaAs growth.
According to the reference [4,23] described before, maybe GaAs-B is the dominant when the growth temperature was reduced from 650°C to 420°C in this study. However, it should be noted that the configuration of double atomic-layersteps as shown in 5-9(b) is favorable than single atomic-layersteps owing to the different in energy as shown in Table 5-2 [15]. On the
72
other hand, the step formation energy of double atomic-layer stepsis also lower than that of single atomic-layer steps when high-temperature substrate annealing was adopted. It means that high-temperature substrate annealing may transfer single-layer steps into double-layer steps [16]. Therefore, surface transition kinetics are most likely to be limited upon cooling to high temperature. The temperature-dependent surface transition that normally leads to GaAs-B nucleation elsewhere has been quenched, and that the high temperature preference for GaAs-A has been preserved.
Growth temperature including annealing temperature is very important parameter for GaAs/Ge/Si heterostructure. In normal condition, which means that no As prelayer was used during material growth, GaAs grown at too low temperature resulted in an excess As point defects, which enhance the nucleation loops. These loops expanded during the subsequent high temperature GaAs growth, which generated high threading dislocation density in the thick GaAs epitaxy [37]. In contrast, GaAs grown on Ge/(Si) substrate without As prelayer at higher growth temperature and low growth rates may result in the formation of an unwanted p-n junction due to simultaneous interdiffusion of Ga and As into Ge epitaxy, which in turn reduces the solar cell efficiency. In my study, the graded-temperature As prelayer was grown on Ge/Si substrate with substrate annealing process prior GaAs epitaxial growth. We fear that the arsenic atoms in the graded-temperature As prelayer interact with Ge atoms and change surface reconstructions and then affect the quality of GaAs epitaxy. In the selective-area
73
diffraction pattern diffracted from the GaAs/As interface area, only the GaAs diffraction spots exist along [110] zone axis as shown in Fig. 5-16(b). Different crystal structure has been not existed from that of GaAs. This observation suggests that the graded-temperature arsenic prelayer enhances the As concentration on the Ge surface, which can be verified by Fig. 5-17, and does not generate different crystal structure in the GaAs/As epitaxy. This implies that As coverage formed on the Ge/Si substrate did not change the structural configuration of GaAs/Ge epitaxy. The As prelayer grown on the Ge/Si substrate annealed at 650°C modifies the surface morphology of the GaAs epitaxy and reduces the APD formation.
Figure 5-18 illustrates the HRXRD results of the GaAs/As epitaxy on both the unannealed Ge/Si substrate and the Ge/Si substrate annealed at 650°C. In regard to the change of GaAs Bragg angle (~45arcsec) for these two samples, we speculated that carbon incorporation may have played a role in the GaAs epitaxy with low V/III ratios. The lattice contraction is attributed to the incorporation of substitutional carbon during the growth of the III-V materials, as discussed in a recent study [36]. The HRXRD and SIMS results show that the substrate annealing process effectively reduced carbon incorporation into the GaAs epitaxy, as shown in Fig. 5-18 and Fig. 5-19. Furthermore, full width at half maximum (FWHM) value of the GaAs peak decreased from 402 to 250 arcsec, which confirms that annealing step improves the GaAs crystal quality.
74
5.3.3 Effect of graded-temperature arsenic prelayer on the interdiffusion of GaAs/Ge/Si heterostructure
The As prelayer was deposited onto the Ge epitaxy while the growth temperature was ramped from 300 to 420°C. It is demonstrated that the graded-temperature arsenic prelayer grown on a Ge/Si substrate annealed at 650°C not only improves the surface morphology (roughness: 1.1nm) but also reduces the anti-phase domains’ (APDs) density in GaAs epitaxy (dislocation density: ~2×107cm-2) as shown in Fig. 5-13, 5-16 and 5-18. High quality GaAs epitaxy can increase III-V solar cell efficiency grown on Si substrate. However, the interdiffusion is another important issue, which forms unwanted P-N junction in the cell, for high efficiency and low cost III-V solar cells. Figure 5-20 illustrates the SIMS depth profiles of Ge, As, and Ga atoms in the GaAs epitaxy grown on the Ge/Si heterostructure using the graded-temperature As prelayer. It is found that the interdiffusion of Ge into GaAs was suppressed for all the samples with ultrathin graded-temperature arsenic prelayer. Because the energy of the As-Ge bond (35.8 kcal/mol) is much lower than that of the Ga-Ge bond (46.7 kcal/mol) as shown in Table 5-3 [38], the Ge atoms segregate at the As prelayer before the deposition of the GaAs layer at low growth temperature. On the other hand, this implies that the As atoms can diffuse into the Ge layer easily and react with the Ge atoms. The incorporation probability of As atoms in the GaAs/Ge system could be described by Barnett et al. [39] and shown in Equation (5-3).
75
Jnet=αIn+dθs/dt (5-3) The incorporation rate αIn = N·GT, where N and GT are the As concentration and growth rate
in the film respectively. The net flux Jnet = Jsup-Jdes, where Jsup represents the supplying flux of AsH3 and Jdes is the total desorption flux. The As surface coverage, dθs/dt, is zero at steady state. At steady state, this net flux represents a flux of AsH3 (Jnet) which is successfully decomposed and incorporated and should be equal to the incorporation rate (αIn). As the As concentration N is increased at higher III-V ratio, the incorporation rate αIn and the net flux Jnet increases according to the equation. For V/III ratios larger than 20 (i.e., larger As flux), the larger Jnet resulted in significant As interdiffusion as shown in Fig. 5-20(a)–(d). For GaAs epitaxy with a V/III ratio of 20 and the graded-temperature As prelayer on the Ge/Si heterostructure annealed at 650°C, virtually no As interdiffusion was observed as shown in Fig. 5-20(e). As judged from the SIMS and TEM results, the As prelayer grown using graded-temperature technique is also an excellent candidate for suppressing interdiffusion of the Ga, As, and Ge atoms.
76
5.4 Summary
In summary, we have demonstrated that the As prelayer grown using graded-temperature technique on the Ge/Si substrate annealed at 650°C effectively improves the surface morphology of GaAs epitaxy (roughness: 1.1 nm) and avoids the need for high V/III ratios, unlike in traditional growth techniques [31,35]. The thin GaAs epitaxy grown on the Ge/Si substrate also contains lower APD density (~2x107cm-2) and lower carbon incorporation when the graded-temperature As prelayer and substrate annealing process were adopted. These results suggest that the generation of atomic steps on the Ge surface promotes As deposition at lower growth temperature and boosts single-domain GaAs-A growth during the heterostructure growth of GaAs/As/Ge/Si. Furthermore, we also demonstrate that the interdiffusion of Ge and As atoms in the GaAs/Ge/Si heterostructure can be effectively suppressed by the graded-temperature As prelayer because of the difference in energies between As-Ge and Ga-Ge bonds and low As flux. These excellent results suggest that the graded-temperature As prelayer grown on Ge/Si substrate has great potential for use in the growth of III-V nanoelectronic devices and optoelectronic devices on the Si substrate.
77
References
[1] Carrie L. Andre, John A. Carlin, John J. Boeckl, David M. Wilt, M. A. Smith, A. J. Pitera, M. L. Lee, Eugene A. Fitzgerald, and and Steven A. Ringel, IEEE TRANSACTIONS ON ELECTRON DEVICES, 52, 1055 (2005)
[2] M. R. Lueck, C. L. Andre, A. J. Pitera, M. L. Lee, E. A. Fitzgerald, and S. A. Ringel, IEEE TRANSACTIONS ON ELECTRON DEVICES, 27, 142 (2006)
[3] D. Lubyshev, J. M. Fastenau, Y. Wu, W. K. Liu, M. T. Bulsara, E. A. Fitzgerald and W. E.
Hoke, J. Vac. Sci. Technol. B 26, 1115 (2008)
[4] Yuan Li, L. Lazzarini, L. J. Giling and G. Salviati, J. Appl. Phys. 76, 5748 (1994)
[5] Guang-Li Luo, Yen-Chang Hsieh, Edward Yi Chang, M. H. Pilkuhn, Chao-Hsin Chien, Tsung-His Yang, Chao-Ching Cheng and Chun-Yen Chang, J. Appl. Phys. 101, 084501 (2007)
[6] R. Fischer, H. Morkoc, D. A. Neumaan, H. Zabel, C. Choi, N. Otsuka, M. Longerbone and L. P. Erichson, J. Appl. Phys. 60, 1640 (1986)
[7] M. K. Hudait, and S. B. Krupanidhi, J. Appl. Phys. 89, 5972 (2001)
[8] S. Scholz, J. Bauer1, G. Leibiger, H. Herrnberger, D. Hirsch, and V. Gottschalch .Cryst.
Res. Technol. 41, No. 2, 111 – 116 (2006)
[9] J. E. Griffith and G. P. Kochanski, Crit. Rev. solid state Mater. Sci. 16, 255 (1990)
[10] J. E. Griffith, J. A. Kubby, P. E. Wierenga, R. S. Becker and J. S. Vickers, J. Vac. Sci.
Technol. A6, 493 (1998)
[11] H. Doscher, B. Borkenhagen, G. Lilienkamp, W. Daum, T. Hannappel, surface Science 605, L38 (2011)
[12] L. Lazzarini, Y. Li, P. Franzosi , L.J. Giling, L. Nasi, F. Longo, M. Urchulutegui, G.
Salviat, Mater. Sci. Eng. B 28, 502 (1994) [13] H. Kroemer, J. Cryst. Growth 81, 193 (1987)
78
[14] R.M. Sieg, S.A. Ringel, S.M. Ting, E.A. Fitzgerald, and R.N. Sacks, J. Electron. Mater.
27, 900 (1998)
[15] DJ. Chadi, Phys. Rev . Lett. 59, 1691 (1987)
[16] D. E. Aspnes and J. Ihm, J. Vac. Sci. Technol. B 5, 939 (1987)
[17] C. K. Chia, A. Sridhara, M. Suryana, J. R. Dong, B. Z. Wang, G. K. Dalapati, and D. Z.
Chi, " GaAs-Ge Materials Integration for Electronic and Photonic Applications”, Group IV Photonics, 5th IEEE International conference, Cardiff, 17-19 Sept. 2008, 294-296 [18] T. Kawai, H. Yonezu, H. Yoshida and K. Pak, Appl. Phys. Lett. 61, 1216 (1992)
[19] B. Galiana, K. Volz, I. Rey-stolle , W. Stolz and C. Algora, IEEE Proceedings of the 4th Word Conference on Photovoltaic Energy Conversion (PVEC), Hawaii, May 2006, Vol. 1, P. 807
[20] M. Schwaab, J. C. Pinto, chemical engineering science 62, 2750 (2007)
[21] E. Vainonen-Ahlgren, T. Ahlgren, J. Likonen, S. Lehto, J. Keinonen, W. Li and J.
Haapamaa, Appl. Phys. Lett. 77, 690 (2000)
[22] J. S. Harris, Y. Nannichi and G. L. Pearson, J. Appl.Phys. 40, 4575 (1969) [23] R. M. Feenstra, J. M. Woodall, and G. D. Pettit, Phys. Rev. Lett. 71, 1176 (1993)
[24] H. Liu, T. Wang, Q. Jiang, R. Hogg, F. Tutu, F. Pozz and A. Seeds, Nature Photon. 5, 416 (2011)
[25] D. Choi, J. S. Harris, E. Kim, P. C. McIntyre, J. Cagnon, S. Stemmer, J. Crst. growth 311, 1962 (2009)
[26] R.D. Bringans, D.K. Biegelsen, L.-E. Swartz, Phys. Rev. B 44, 3054 (1991).
[27] R.D. Bringans, R.I.G. Uhrberg, R.Z. Bachrach, J.E. Northrup, Phys. Rev. Lett. 55, 533 (1985).
[28] R.S. Becker, T. Klitsner, J.S. Vickers, J. Microsc. (Oxford) 152, 157 (1988) [29] T.R. Ohno, E.D. Williams, J. Vac. Sci. Technol. B 8, 874 (1990)
[30] Y. Yamamoto, P. Zaumseil, T. Arguirov, M. Kittler and B. Tillack, Solid-State Electronics
79
60, 2 (2011)
[31] Yuan Li, G. Salviati, M. M. G. Bongers, L. Lazzarini, L. Nasi, and L. J. Giling, J. Cryst.
Growth 163, 195 (1996)
[32] M. Kushibe, K. Eguchi, M. Funamizu, and Y. Ohba, Appl. Phys. Lett. 56, 1248 (1990) [33] H. Asai, J. Cryst. Growth 80, 425 (1987)
[34] G. B. Stringfellow, J. Cryst. Growth 128, 503 (1993)
[35] R. Tyagi, M. Sihgh, M. Thirumavalavan, T. Srinivasan, and S. K. Agarwal, J. Electron.
Mater. 31, 234 (2002)
[36] H. W. Yu, E. Y. Chang, H. Q. Nguyen, J. T. Chang, C. C. Chung, C. I. Kuo, Y. Y. Wong, and W. C. Wang, Appl. Phys. Lett. 97, 231903 (2010)
[37] S. M. Ting, E. A. Fitzgerald, R. M. Sieg, and S. A. Ringel, J. Electron Mater. 27,451 (1998)
[38] Yasuo Seki, Hisao Watanabe, and Junji Matsui, J. Appl. Phys. 49, 822 (1978) [39] S. A. Barnett and J. E. Greene, Surf. Sci. 151, 57 (1985)
80
Table 5-1 Lattice constants and thermal expansion coefficients of GaAs and Ge
Table 5-2 Step formation energies per unit length on Ge (001) surface [15]
81
Table 5-3 Single-bond energy used for the calculation [38]
82
Figure 5-1 Anti-pahase formation of polar semiconductor materials on non-polar semiconductor materails
Figure 5-2 Schematic drawings of GaAs crystal structure
83
Figure 5-3 The two possible sublattice locations of Ga and As atoms in GaAs grown on Ge epitaxy
Figure 5-4 Sublattice location phase diagram as a fuction of growth temperature and disorientation angle for GaAs on Ge (100) off towards (111) [6]
84
Figure 5-5 2-D and 3-D AFM topographical images of the GaAs epitaxial layers grown on 6°
off-oriented Ge substrate with growth temperature at (a)(b) (b) 650°C and (c)(d) 750°C. [4]
Figure 5-6 TEM images of GaAs grown on Ge substrate with different misorientation angles (a) 6° and (b) 0°. [5]
85
Figure 5-7 A model to explain the reversal of the sublattice locations between GaAs grown on (100) Ge off toward (111) substrates with small and larger misoriented angles. (a) Nucleation on Ge substrate with larger misoriented angles: nuclei form only at steps. (b) Overgrowth on such surface results in that the initial nuclei are connected with each other so that single-phase domain of GaAs-A is achieved. (c) Nucleation on Ge substrate with small misoriented angles: nuclei form at steps and on the terraces.(d) Overgrowth on such surface resultsin that the initial nuclei at the steps are surrounded by theAPDs. [13]
Figure 5-8 Cross-sectional TEM micrographs of two 1μm thick GaAs films grown on Ge. (a) Film with high APDs densities extending to the surface, grown on an unannealed epitaxial Ge
layer. (b) APD-free film grown on an annealed epitaxial Ge layer. [14]
86
Figure 5-9 (a) SA (upper left) and SB (upper right) single atomic-layer steps. On a mixed domain surface (bottom) both types of single steps are evident. Note the rotation of dimerization axes and dimer rows on alternating terraces. (b) DA (upper left) and DB (upper right) double atomic-layer steps. Note that only DB steps are observed experimentally, DA
steps are energetically unfavorable. On the single-domain surface (below) the dimerization axis and dimer rows are invariant across the DB step. [15,16]
87
Figure 5-10 Diffusion coefficients and solid solubilities of Ga and As in Ge layer. [21]
88
Figure 5-11 SIMS profiles for GaAs/AlAs/Ge samples with AlAs nominal thickness of (a) 0, (b) 10, (c) 20, and (d) 30 nm. The corresponding TEM image for each sample is placed behind the graph to illustrate the position of the layers. [18]
89
Figure 5-12 All parametrs used in the study are shown in the chart, which include growth temperature, V/III ratio, substrate annealing temperature, substrate annealing time and growth temperature of As prelayer.
90
Figure 5-13 AFM images (5μm×5μm) of GaAs layer with different V/III ratios grown on a Ge/Si substrate using a graded-temperature As prelayer (a) V/III: 11, (b) V/III: 20, (c) V/III:
30, (d) V/III: 50, (e) V/III: 75, and (f) V/III: 20 and annealed at 650°C.
91
Figure 5-14 Lateral and vertical growth rates as a function of [AsH3] [33,34]
Figure 5-15 Schematic cross sections of (a) [110] and (b) [-110] steps [34]
92
Figure 5-16 TEM cross-sectional micrograph of GaAs/As/Ge/Si heterostructure grown at a V/III ratio of 20. (a) unannealed Ge/Si substrate and (b) Ge/Si substrate annealed at 650°C
93
Figure 5-17 SIMS profiles for GaAs epitaxy grown at different V/III ratios on a Ge/Si substrate with a graded-temperature As prelayer (a) V/III: 20, (b) V/III: 20 and annealed at 650°C
94
Figure 5-18 HRXRD rocking curves of the GaAs/As/Ge/Si heterostructure grown at a V/III ratio of 20. (a) unannealed Ge/Si substrate and (b) Ge/Si substrate annealed at 650°C
Figure 5-19 SIMS profile of carbon for the GaAs/As epitaxy grown on both the unannealed Ge/Si substrate and the Ge/Si substrate annealed at 650°C.
95
Figure 5-20 SIMS profiles for GaAs epitaxy grown at different V/III ratios on a Ge/Si substrate with a graded-temperature As prelayer (a) V/III: 20, (b) V/III: 30, (c) V/III: 50, (d) V/III: 75, (e) V/III: 20 and annealed at 650°C.
96
Chapter 6
Conclusion and future work
6.1 Conclusion
In conclusion, we have demonstrated that the misorientation of GaAs substrates has a direct effect on the material properties of the P++-AlGaAs/N++-GaAs tunnel diodes (TDs) for multijunction III-V solar cell application, as shown in chapter 3. The best surface morphology and interface sharpness for the TDs were obtained on the (100) tilted 10° off toward [111]
GaAs substrate. Results show that the TD materials grown on this misoriented substrate can overcome the limitation of high surface free energy and with reduced sticking coefficient for oxygen-incorporation in the N++-GaAs layers. Besides, we also found that this substrate has also reduced the anisotropic sites for oxygen-incorporation in the P++-AlGaAs layers.
On the other hand, we also proved that InGaP/GaAs dual junction solar cells with a P++-AlGaAs/N++-GaAs TD grown on 10°off GaAs substrates exhibit superior photovoltaic conversion efficiency (~20%) when operated at one sun, as shown in chapter 4. The cell design with a P++-AlGaAs/N++-GaAs TD grown on 10°off GaAs substrates produces higher EQE (~82% for InGaP top cell and 85% for GaAs bottom cell) as compared to the P++-GaAs/N++-InGaP TD. Furthermore, when these solar cell devices were operated at higher concentration ratios, they displayed superior I-V characteristics compared to the traditional dual-junction solar cell grown on 6° off misorientation GaAs substrates, as shown in chapter 4.
97
These results suggest that 10° off misorientation GaAs substrates for cell design with a P++-AlGaAs/N++-GaAs TD not only produce high light-trapping and carrier-collection efficiencies but also generate higher peak current density (Jpeak) at higher concentration ratios (185×) than that of a P++-GaAs/N++-InGaP TD grown on 6° off GaAs substrate, even if the thickness of ohmic contact in the study is not sufficient.
To decrease the cost of concentrated photovoltaic solar cells (CPVSCs), we try to grow III-V materials, such as GaAs, on the Ge/Si substrate by low-pressure metal organic chemical vapor deposition to replace traditional InGaP/(In)GaAs/Ge triple-junction solar cells. We have demonstrated that the As prelayer grown using graded-temperature technique on the Ge/Si substrate annealed at 650°C effectively improves the surface morphology of GaAs epitaxy (roughness: 1.1 nm) and avoids the need for high V/III ratios, as shown in chapter 5. The thin GaAs epitaxy grown on the Ge/Si substrate also contains lower APD density (~2x107cm-2) and lower carbon incorporation when the graded-temperature As prelayer and substrate annealing process were adopted. Furthermore, we also demonstrate that the interdiffusion of Ge and As atoms in the GaAs/Ge/Si heterostructure can be effectively suppressed by the graded-temperature As prelayer because of the difference in energies between As-Ge and Ga-Ge bonds and low As flux. These results suggest that the graded-temperature As prelayer grown on Ge/Si substrate has great potential for use in the growth of III-V nanoelectronic devices and optoelectronic devices on the Si substrate.
98
6.2 Future work
The purpose of the study in this thesis was to investigate some advanced techniques that can enhance the conversion efficiency and reduce production cost of III-V multijunction solar cells. Following the invesigations desrcibed in the thesis, some projects could be propose in the future.
(A) (100) tilted 10° off toward [111] GaAs substrates can be used for the growth of inverted metamorphic multijunction solar cell structures, which is built on GaAs based substrates and inverted onto other substrates.
(B) The GaAs epitaxy can be grown on Ge substrate using graded-temperature As prelayer and substrate annealing technique to replace traditional InGaP nucleation layer in InGaP/(In)GaAs/Ge triple junction solar cell. The thin GaAs epitaxy on Ge substrate using this technique is very stable, and it doesn’t encroach on Spectrol-Lab’s patent (US 6,380,601 B1).
(C) III-V multijunction solar cells can be grown on Ge/Si substrate using GaAs buffer layer, which decreases the cost of PVSCs and increase its competitiveness in this field.
99
Publication List
Journal papers
[1] H. W. Yu, E. Y. Chang, H. Q. Nguyen, J. T. Chang, C. C. Chung, C. I. Kuo, Y. Y. Wong and W. C. Wang, “Effect of substrate misorientation on the material properties of GaAs/Al0.3Ga0.7As tunnel diodes” APPLIED PHYSICS LETTERS 97, 231903 (2010)
[2] H. W. Yu, E. Y. Chang, Y. Yamamoto, B. Tillack, W. C. Wang, C. I. Kuo, Y. Y. Wong, and H. Q. Nguyen, “Effect of graded-temperature arsenic prelayer on quality of GaAs on Ge/Si substrates by metalorganic vapor phase epitaxy” APPLIED PHYSICS LETTERS 99, 171908 (2011)
[3] Hung Wei Yu, Chen Chen Chung, Chin Te Wang, Hong Quan Nguyen, Binh Tinh Tran, Kung Liang Lin, Chang Fu Dee, Burhanuddin Yeop Majlis, and Edward Yi Chang, “An InGap/GaAs dual-junction solar cell with AlGaAs/GaAs tunnel diode grown on 10° off misorientation GaAs substrate” Japanese Journal of Applied Physics 2012 (acceptance)
[4]Hong Quan Nguyen, Edward Yi Chang, Hung Wei Yu, Kung Liang Lin, and Chen Chen Chung, “High-Quality 1 eV In0.3Ga0.7As on GaAs Substrate by Metalorganic Chemical Vapor Deposition for Inverted Metamorphic Solar Cell Application” Applied Physics Express 4 (2011) 075501
[5] Hong Quan Nguyen, Edward Yi Chang, Hung Wei Yu, Hai-Dang Trinh, Hai-Dang Trinh, Yuen-Yee Wong, Ching-Hsiang Hsu, Binh-Tinh Tran, and Chen-Chen Chung, “Threading Dislocation Blocking in Metamorphic InGaAs/GaAs for Growing High-Quality In0:5Ga0:5As and In0:3Ga0:7As on GaAs Substrate by Using Metal Organic Chemical
100
Vapor Deposition” Applied Physics Express 5 (2012) 055503
[6] Binh-Tinh Tran, Edward-Yi Chang, Hai-Dang Trinh, Ching-Ting Lee, Kartika Chandra Sahoo, Kung-Liang Lin, Man-Chi Huang, Hung-Wei Yu, Tien-Tung Luong, Chen-Chen Chung, and Chi-Lang Nguyen, "Fabrication and Characterization of n-In0.4Ga0.6N/p-Si Solar Cell", Solar Energy Materials and Solar Cells, 2012 (acceptance)
Conference Papers
[1] Hung-Wei Yu, Chen-Chen Chung, Nguyen Hong Quan, Wei-Chieh Wang , E. Y. Chang,
“ Investigation of AlxGa1-xAs/GaAs Heterostructures” 2009 5th NTT-BRL School in Japan.
[2] Hung-Wei Yu, H.Q. Nguyen, J. T. Chang, C. C. Chung, W. C. Wang , C. H. Hsu, E. Y.
Chang, “ Investigation of Misorientation Substrates on a GaAs/Al0.3Ga0.7As Tunnel Diode”
2010 Taiwan Int’I Photovoltaic Exhibition
[3] Hung Wei Yu, Tsun Ming Wang, Hong Quan Nguyen,Binh Tinh Tran, Chen Chen Chung, Ching Hsiang Hsu,Dao Yuan Chiuo, Phan Van Thanh Hoa and Edward Yi Chang, “AlGaAs/
GaAs Tunnel diodes grown on misorientated GaAs substrates for InGaP/ GaAs dual-junction solar cell applications” The Energy&Materials Research Conference-EMR2012, 20 to 22 June 2012 in Torremolinos, Spain.
[4] Chen-Chen Chung, Hung-Wei Yu, Li-Han Hsu, Chien-I Kuo, Nguyen-Hong Quan,
[4] Chen-Chen Chung, Hung-Wei Yu, Li-Han Hsu, Chien-I Kuo, Nguyen-Hong Quan,