• 沒有找到結果。

Chapter 4 RF Noise Modeling and Characterization for SOI Dynamic Threshold

4.3 RF Small-Signal and Noise Modeling

The RF small-signal and noise equivalent circuit suitable for the DT MOSFET modeling and characterization will be described in this section. Then, a set of simple and analytic expressions of Y parameters beneficial to the model parameter extraction will be presented accordingly [11].

66

analytic two-port admittance ( Y ) parameters can be derived when the effect of series resistances compared to access body resistance (Rb) can be neglected. Following especially shows the expressions benefiting the parameter extraction:

   

procedure shown in Fig. 4-4 is then proposed. Compared to the method proposed in reference [12], which needs some parameters determined from DC characteristics, our extraction method relies only on local optimizations using definite RF fitting targets to obtain all model parameters, so the excellent modeling results with less than 10% relative root-mean-square errors for each real and imaginary part of Y parameters, as shown in Fig. 4-5, can be expected. For the reader’s reference, the extracted model parameters are listed in Table 4-1.

Besides, as shown in Fig. 4-6, based on the RF small-signal equivalent circuit, the RF noise equivalent circuit can be built by adding the corresponding noise current sources. In this noise equivalent circuit, id stands for the intrinsic channel noise current, and the assumption

that the high-frequency prominent drain-induced gate noise can be neglected is adopted. This assumption had been shown to be reasonable especially for deep sub-micrometer devices [15], and its validity will also be examined in Chapter 6. Furthermore, the noise current sources related to series resistances and access body resistance are considered as thermal noise current sources (i 4kT R, R : resistance value). Finally, the inherent shot noise current caused by the source-side junction current is estimated using shot noise current formula (ij,sb  2qIb  2qIg ).

The only one unknown model parameter id can be directly obtained by optimizing the four measured high-frequency noise parameters (minimum noise figure NFmin, equivalent noise resistance R , magnitude of the optimum reflection coefficient nopt , and phase of the optimum reflection coefficient opt). The good noise modeling results are shown in Fig.

4-7.

4.3.2 Verification of the Extraction Results

To further examine the accuracy of the modeling results, some important model parameters versus VDD for different channel lengths are examined. Note that we let

V

V VDD

VGSBSDS  to keep the device operating in the saturation region. Figure 4-8(a) shows that compared to the standard device, the DT device has larger trans-conductance (g ) m

68

channel resistance (R ) for shorter channel devices in Fig. 4-8(b). ds

Besides, lower threshold voltage also increases the channel charge, and hence increases the intrinsic capacitance [1]. Therefore, as shown in Fig. 4-8(c), the DT device would have larger gate-to-source capacitance (C ) than the standard one. Figure 4-9(a) shows that the gs body trans-conductance (g ) tends to increase with mb VDD. However, in the low-voltage regime where the DT device normally operates, compared to g , its value is small and hence m its contribution to the total device performance could be negligible.

Finally, the source- and drain-side junction capacitances (Cj,sb and Cj,db) as well as

access body resistance (R ) versus b VDD are examined. In Fig. 4-9(b), Cj,sb tends to exponentially increase as VDD increases due to the nature of its forward-biased diffusion capacitance, while Cj,db shows less bias dependence. Besides, decreasing channel length can

help decrease Cj,sb, but increase Cj,db. Figure 4-9(c) shows that R may decrease with b increasing VDD, which results from the abundant positive charge supplied by the external DC source through the body contact. This figure also supports that because the shorter device has a smaller cross-section for current flowing into the body, it has larger R . Note that all b the channel length dependences for Cj,sb, Cj,db, and R become weak for channel length b below 0.12 μm .

4.4 RF Small-Signal Characterization

In this section, using the extraction methodology proposed in the previous section, we will study the temperature dependences of the extracted small-signal parameters for the RF SOI DT MOSFET.

4.4.1 Temperature Dependences of Small-Signal Parameters

Figure 4-10 shows the temperature dependences of gate-to-source capacitance C , gs channel resistance R , and trans-conductance ds g for the DT MOSFET. Lower threshold m voltage at higher temperature can induce more charges in the channel and hence larger C gs [1] and lower R as shown in Figs. 4-10(a) and (b), respectively. This also results in ds positive temperature dependence for g in the low m VDD regime as shown in Fig. 4-10(c) [4]. At high VDD, however, the lower mobility at higher temperature would degrade g , so m g tends to decrease with increasing temperature in the high m VDD regime [4][17]. Also note that at all bias conditions where saturation holds, C shows much less temperature gs dependence than g . m

The temperature dependences of inherent body-related parasitics of the DT MOSFET are shown in Fig. 4-11. Due to the more leaky behavior encountered in source-to-body junction at higher temperature, the source-to-body junction capacitance Cj,sb would increase with temperature. On the other hand, compared to Cj,sb, the drain-to-body junction capacitance

db

Cj, shows less temperature dependence (see Fig. 4-11(a)). Besides, at higher temperature and larger VDD (and hence, larger V ), more charge would be injected into the body BS region through source-to-body junction, and this could contribute to the observation that the body resistance R tends to decrease with increasing temperature and b VDD as shown in

70

figures of merit used to characterize the RF performance of a device. To derive out simple and analytical equations for analysis, the series resistances have been omitted at the moment, and also de-embeded from the maseured data for model comparison. Based on the equivalent circuit shown in Fig. 4-6 without considering series resistances R , s R , and d R , the g f t and fmax for the DT MOSFET biased in the low VDD regime can be approximately expressed as the following equations [18].

 

gs The approximation in Equs. (4-8) and (4-9) holds in the low VDD regime, where

1

mb

m g

g , Rb Ri1, gmbRb Cj,db Cj , and RbCj 1 around fmax, and the good modeling results for f and t fmax in the low VDD regime are shown in Figs. 4-12(a) and (b), respectively.

Equation (4-8) implies that the inherent body-related parasitics of the DT MOSFET would have little influence on f . In the low t VDD regime, since g tends to increase m with temperature, f would have a positive temperature coefficient as shown in Fig. 4-13(a) t for VDD below 0.4V.

On the other hand, Equation (4-9) implies that the body-related parasitics would degrade

fmax through the degradation factor DT , which is about 3/4 and almost bias and temperature independent as shown in Fig. 4-14. In addition, due to the less temperature dependent behavior of Rds Ri (also shown in Fig. 4-14), fmax tends to have the same temperature dependence as f (see Fig. 4-13(b)). That is, in the low t VDD regime, both

fmax and f would tend to become larger at higher temperature. t

4.4.3 Series Resistance Effect

In the previous sub-section, we have focused on the ‘inner’ device performance without considering the series resistance effect. To judge the series resistance effect on the overall performance and complete the characterization, this effect will be considered in this sub-section. Besides, to facilitate the examination of the temperature effect, we have normalized the related parameters with respect to their corresponding values at T  25C in the following discussions.

Figure 4-15 shows that the series resistance has much more significant effect on the unilateral power gain U (or fmax) than the short-circuit current gain H21 (or f ) at t

V 3 .

0

VDD . Compared to the series resistance, the much larger input and output impedance in the low VDD regime would dominate H21 , and hence, f . The little series resistance t effect on f can be also deduced in Fig. 4-16(a) and (b), where t f has nearly the same t temperature coefficient as g for each channel length device. This coincides with the m

72

fmax.

4.5 RF Noise Characterization

4.5.1 Channel Noise and Equivalent Noise Resistance

The extracted power spectral density for the channel noise current i (denoted as d S ) id is shown in Fig. 4-18, and usually expressed as follows [19].

4 B d0

id k T g

S   (4-12)

where J/KkB 1.381023 is Boltzmann constant, T is the ambient temperature in Kelvin,

0

g is the channel conductance at zero drain-source voltage, and d  is noise factor. Besides, reference [20] has shown that  has the weak temperature dependence, and the temperature dependence of S is dominated by that of id g and T . d0

Figure 4-19(a) and (b) respectively show the temperature dependences of S and id g . d0 In the low VDD regime, since g tends to increase with temperature [18], d0 S would id increase accordingly as predicted by Equ. (4-12). Note that Equ. (4-12) was originally derived for the device operating in the strong inversion region. However, in our experiments, the consistent prediction results for the temperature dependence of S shows that it seems to id remain valid even for the medium or weak inversion applications.

The channel noise has significant effect on the equivalent noise resistance R for n conventional MOSFETs. In fact, by neglecting the body trans-conductance, the R for DT n MOSFETs would be approximately the same as that for conventional MOSFETs as expressed in the following.

g m

B

n id R

T T g T k R S

0 2

4 0

(4-13) where T0 290K is the reference temperature. Note that Equ. (4-13) indicates that in the

low VDD regime, the body-related parasitics would have little influence on R . n

Figure 4-20(a) shows R versus temperature curves for each channel length device. n Since VT for L60nm device is about 0.1V higher than those for L120nm and

nm

240

L devices in the whole temperature range (see Fig. 4-1), we first consider V

3 .

0

VDD for L120nm and L240nm devices, and VDD0.4V for L60nm device to keep approximately the same gate overdrive voltage. In this case, one can compare the temperature dependence for S in Fig. 4-19(a) and that for id g in Fig. 4-20(b). Since m2

S tends to have the similar temperature coefficient as id g , according to Equ. (4-13), m2 R n tends to increase with temperature mainly due to the increase of R and T . g

For L60nm device operating at weaker bias condition, that is, VDD0.3V, however, g tends to more deeply increase with increasing temperature than m2 S . This id could compete with or even overwhelm the contribution from “hot” R . Therefore, g R tends n to decrease with increasing temperature. This also shows the existence of the zero temperature coefficient for R , which occurs between n VDD0.3Vand VDD0.4V for L60nm device.

4.5.2 Output Noise Current and Minimum Noise Figure

Unlike R , the minimum noise figure n NFmin may be strongly influenced by R . b Although the analytical expression for NFmin is not easily derived, the noise contribution arising from R to the output noise current flowing into the drain terminal can be analyzed

74

counterpart to the output noise current and are shown in Fig. 4-21(a) and (b), respectively. We found that larger R in the low b VDD regime would have less S noise contribution for iRb each length device. This figure also shows that the shorter device with larger R would have b more S contribution. It is worth noting that the smaller body cross-section area seen in the iRb direction perpendicular to the channel current flow can account for the larger R present in b the shorter device.

Through the sensitivity analysis of the variation of R to its noise contribution as b shown in Fig. 4-22, we can see that its noise contribution could be reduced with increasing

R . In fact, the noise equivalent circuit for DT MOSFETs would be equivalent to that for b

conventional MOSFETs when R approaches infinity and can be removed in the equivalent b circuit. Therefore, the larger R would play an insignificant role in determining b NFmin.

The minimum noise figure NFmin versus VDD is shown in Fig. 4-23. The NFmin is sharply increased towards the weak inversion region, and this trend is consistent with that for the conventional bulk MOSFET [21]. Moreover, our experimental results show that NFmin has less temperature dependence in the low VDD regime. As shown in Fig. 4-22, in the low VDD regime, since the noise contribution of S to the output noise current for each iRb temperature is not significant, R would have little effect on the temperature dependence of b

NFmin.

4.6 Summary

We have demonstrated the RF small-signal and noise modeling for SOI DT MOSFETs.

Based on a set of simple and analytic expressions of Y parameters, model parameters can be physically extracted, and the model has been shown to be valid up to 12 GHz.

The temperature dependences of RF small-signal and noise behaviors for the DT MOSFET have been investigated. In the low VDD regime, since g tends to increase with m temperature, f would have a positive temperature coefficient. On the other hand, due to the t

less temperature dependent behavior of  and DT Rds Ri , fmax is found to increase with temperature as well. Moreover, the body-related parasitics and the series resistances are found to have more impact on fmax than f . t

In the low VDD regime, the channel noise S has a positive temperature coefficient id due to larger g at higher temperature. In addition, compared to d0 S , the much higher id g m2 towards the weaker inversion region can cause R to have a negative temperature coefficient. n Finally, it shows that, in the low VDD regime, the large R would have little impact on the b temperature dependence of NFmin.

76

References

[1] F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. K. Ko, and C. Hu, “Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI,” IEEE Trans.

Electron Devices, vol. 44, pp. 414–422, Mar. 1997.

[2] S. S. Rofail and K. S. Yeo, “Experimentally-based analytical model of deep submicron LDD MOSFETs in a Bi-MOS hybrid-mode environment,” IEEE Trans. Electron Devices, vol. 44, pp. 1473–1482, Sept. 1997.

[3] J. B. Kuo, K. H. Yuan, and S. C. Lin, “Compact threshold-voltage model for short-channel partially-depleted (PD) SOI dynamic-threshold MOS (DTMOS) devices,”

IEEE Trans. Electron Devices, vol. 49, pp. 190–196, Jan. 2002.

[4] J.-K. Lee, N.-J. Choi, C.-G. Yu, J.-P. Colinge, and J.-T. Park, “Temperature dependence of DTMOS transistor characteristics,” Solid-State Electronics, vol. 48, pp. 183-187,2004.

[5] C. Wann, F. Assaderaghi, R. Dennard, C. Hu, G. Shahidi, and Y. Taur, “Channel profile optimization and device design for low-power high-performance dynamic threshold MOSFET,” in IEDM Tech. Dig., Dec.1996, pp. 113–116.

[6] A. Shibata, T. Matsuoka, S. Kakimoto, H. Kotaki, M. Nakono, K. Adachi, K. Ohta, and N. Hashizume, “Ultra low power supply voltage (0.3V) operation with extreme high speed using bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced fast-signal-transmission shallow well,” in VLSI Technol. Tech. Symp. Dig., 1998, pp.

76–77.

[7] Y. Momiyama, T. Hirose, H. Kurata, K. Goto, Y. Watanabe, and T. Sugii, “A 140 GHz ft and 60 GHz fmax DTMOS integrated with high-performance SOI logic technology,” in IEDM Tech. Dig., 2000, pp. 451–454.

[8] T. Hirose, Y. Momiyama, M. Kosuhi, H. Kano, Y. Watanabe, T. Sugii, “A 185 GHz fmax SOI DTMOS with a new metallic overlay-gate for low-power rf applications,” in IEDM Tech. Dig., 2001, pp. 33.5.1-33.5.3.

[9] C.-Y. Chang, J.-G. Su, H.-M. Hsu, S.-C. Wong, T.-Y. Huang, and Y.-C. Sun,

“Investigation of bulk dynamic threshold-voltage MOSFET with 65 GHz ‘nomal mode’

ft and 220 GHz ‘over-drive mode’ ft for RF applications,” in VLSI Technol. Tech. Symp.

Dig., 2001, pp. 89–90.

[10] S.-C. Wang, P. Su, K.-M. Chen, K.-H. Liao, B.-Y. Chen, S.-Y. Huang, C.-C. Hung, and G.-W. Huang, “Temperature-dependent RF small-signal and noise characteristics of SOI dynamic threshold voltage MOSFETs,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 9, pp. 2319–2325, Sep. 2010.

[11] S.-C. Wang, P. Su, K.-M. Chen, S.-Y. Huang, C.-C. Hung, G.-W. Huang,

“Radio-frequency small-signal and noise modeling for silicon-on-insulator dynamic threshold voltage metal–oxide–semiconductor field-effect transistors,” Jpn. J. Appl.

Phys., vol. 48, no. 4, pp. 04C041-1 - 04C041-4, April 2009.

[12] M. Dehan and J.-P. Raskin, “Dynamic threshold voltage MOS in partially depleted SOI technology: A wide frequency band analysis”, Solid-State Electronics, vol. 49, pp. 67-72, 2005.

[13] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “On the RF extrinsic resistance extraction for partially-depleted SOI MOSFETs,” IEEE Microw.

Wireless Comp. Lett., vol. 17, pp. 364-366, May 2007.

[14] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang,

“Radio-frequency silicon-on-insulator modeling considering the neutral-body effect,”

78

Dig., 1997, p. 423-426.

[17] A. A. Osman and M. A. Osman, “Investigation of high temperature effects on MOSFET transconductance (gm),” in Proc. 4th Int. High Temperature Electronics Conf. (HITEC), Albuquerque, NM, Jun. 1998, pp. 301–304.

[18] S.-C. Wang, P. Su, K.-M. Chen, S.-Y. Huang, C.-C. Hung, G.-W. Huang, “Temperature dependences of RF small-signal characteristics for the SOI dynamic threshold voltage MOSFET,” in Proc. 4th European Microave Integrated Circuits Conf., Sep. 2009, pp 69-72.

[19] A. F. Tong, W. M. Lim, K. S. Yeo, C. B. Sia, and W. C. Zhou, “A scalable RFCMOS noise model, ” IEEE Trans. Microw. Theory Tech., vol. 57, no. 5, pp. 1009-1019, May 2009.

[20] S.-C. Wang, P. Su, K.-M. Chen, C.-T. Lin, V. Liang, and G.-W. Huang, “Temperature dependence of high frequency noise behaviors for RF MOSFETs,” IEEE Microw.

Wireless Comp. Lett., vol. 18, pp. 530-532, Aug. 2008.

[21] K.-H. To, Y.-B. Park, T. Rainer,W. Brown, and M.W. Huang, “High frequency noise characteristics of RF MOSFET’s in subthreshold region, in IEEE RF Integrated Circuits Symp. Dig., Jun. 2003, pp. 163–167.

Table 4-1 Extracted model parameters for bias condition VGS 0.8V,andVDS 1V . (L/WF /NF /NG=0.24μm/1μm/8/16)

 

mS gm

 

Rds

 

fF Cgs

 

fF Cgd

 

fF Cds

 

ps

 

mS gmb

 

Rb

 

,sb

Rj

 

fF

,sb

Cj

 

fF

,db

Cj

pAid Hz

127 93 550 79 1.3 1.6 38 597 2083 246 20 60

80

-40 -20 0 20 40 60 80 100 120 140 0.00

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40

Thr e shold Voltage, V

T

(V)

Temperature, T (

C)

L = 60nm L = 120nm L = 240nm VDS = 0.1V

Figure 4-1 Temperature dependence of the threshold voltage for SOI DT MOSFETs.

C

gs

C

gd

gm gmb Cds Rds

R

g Rd

Rs

j,s b

C Rj,s b Rb

db

Cj,

vgs

vbs

1 P ort Ga te

2 P ort Dra in

Figure 4-2 RF small-signal equivalent circuit for the SOI DT MOSFET.

82

Lines for modeling resutls

Rd=6.4

Re(Z 12) and Re(Z 22-Z 12) ()

Frequency (GHz)

Figure 4-3 Model-data comparison for the extraction of series resistances using zero method. (L/WF /NF /NG 0.24μm/1μm/8/16, and VGSVDS 0V)

Figure 4-4 Proposed parameter extraction flow.

84

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -0.02

0.00 0.02 0.04 0.06 0.08 0.10

Symbols for measured data Lines for simulated data

Real parts of Y parameters (S)

Freqeuncy (GHz) Re(Y11)

Re(Y22) Re(Y21) Re(Y12)

VGS=0.8V, VDS=1V

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

-0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08

Imaginary parts of Y parameters (S)

Freqeuncy (GHz) Im(Y11)

Im(Y22) Im(Y21) Im(Y12)

VGS=0.8V, VDS=1V Symbols for measured data Lines for simulated data

Figure 4-5 Modeling results for (a) Re

 

Y and (b) Im

 

Y . (L/WF /NF /NG=0.24μm/1μm/8/16).

(a)

(b)

Cgs

Cgd

gm gmb Cds Rds

Rg Rd

Rs

j,s b

C Rj,s b Rb

db

Cj,

vgs

vbs

1 P ort G a te

2 P ort Dra in

id

j,s b

i

Figure 4-6 RF small-signal and noise equivalent circuit for the SOI DT MOSFET.

86

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0.0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

0.2 0.3 0.4 0.5 0.6 0.7 0.8

NF min (dB)

Freqeuncy (GHz)

Normalized Rn

VGS=0.8V, VDS=1V

Symbols for measured data Lines for simulated data

VGS=0.8V, VDS=1V

Symbols for measured data Line for simulated data

Figure 4-7 Noise modeling results for (a) NFmin, R , and (b) n  . opt (id = 60 pA Hz, and L/WF /NF /NG=0.24μm/1μm/8/16)

(a)

(b)

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Symbols for DT MOSFETs Lines for stanard MOSFETs

g m(mS)

Symbols for DT MOSFETs Lines for stanard MOSFETs

Rds()

Symbols for DT MOSFETs Lines for control devices

L=0.06m

88

-40 -20 0 20 40 60 80 100 120 140

Trans-conductance, g m (mS)

Temperature, T (C)

90

C j,sb and C j,db(fF)

Temperature, T (C)

0.0 0.2 0.4 0.6 0.8 1.0 0

20 40 60 80 100

Extracted data Equ. (4-8)

f t (GHz)

VDD (V)

T=25C L = 120nm

0.0 0.2 0.4 0.6 0.8 1.0

0 20 40 60 80 100 120 140 160 180 200 220 240

T=25C

f max

(GHz)

VDD (V)

Extracted data Equ. (4-9) L = 120nm

Figure 4-12 (a) Model-data comparison for (a) f , and (b) t fmax.

(a)

(b)

92

Short-Cir c uit C u rr ent Gain, |H

21

| (dB)

Frequency (GHz)

Unilateral Gain, U (dB)

Frequency (GHz)

-40 -20 0 20 40 60 80 100 120 140 0

2 4 6 8 10 12 14 16 18 20

-40 -20 0 20 40 60 80 100 120 1400.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

(R

ds

/R

i

)

Temperature (

C)

VDD = 0.3V VDD = 0.4V

VDD = 0.5V DT

Figure 4-14 Temperature dependences of Rds Ri and  . DT

94

1 10 100

0 5 10 15 20 25 30

|H

21

| (dB)

Frequency (GHz)

L = 60nm L = 120nm L = 240nm VDD = 0.3V T = 25C

1 10 100

0 5 10 15 20 25 30

VDD = 0.3V T = 25C

L = 60nm L = 120nm L = 240nm

U ( d B)

Frequency (GHz)

Figure 4-15 (a) The short-circuit current gain H21 with (symbols) and without (lines) considering the series resistance effect. (b) The unilateral power gain U with (symbols) and without (lines) considering the series resistance effect.

(a)

(b)

0 50 100 150

Normalized f t

Temperature (C)

0 50 100 150

Normalized g m

Temperature (C)

0 50 100 150

96

60nm 120nm 240nm 25C

Normalized f max

Temperature (C)

0 50 100 150

0.2 0.3 0.4 0.5 0.6 0.7 0

1 2 3 4

T = 25C

S

id

(10

-21

A

2

/Hz)

VDD (V)

L = 240nm L = 120nm L = 60nm

Figure 4-18 Channel noise versus VDD. (WF /NF /NG= μm/8/161 )

98

Normalized S id

Temperature (C)

L = 240nm

Normalized g d0

Temperature (C)

VDD=0.3V

20 40 60 80 100 120 140

Temperature (C)

L = 240nm, VDD =0.3V

L = 120nm, VDD=0.3V L = 60nm, VDD = 0.3V

Normalized g2 m

Temperature (C)

VDD=0.3V

100

0.2 0.3 0.4 0.5 0.6 0.7

0 5 10 15 20 25 30 35 40

L = 240nm L = 120nm

S iRB Noise Contribution w.r.t. S id (%)

VDD (V)

L = 60nm T = 25C

F = 6GHz

s = opt

0 2 4 6 8 10 12 14 16

0.2 0.3 0.4 0.5 0.6 0.7

R b (k)

VDD (V)

L = 240nm L = 120nm

T = 25C L = 60nm

Figure 4-21 (a) The noise contribution from the body noise to the output noise current with respect to that from the channel noise. (b) The extracted body resistance as a function of VDD. (WF /NF /NG= μm/8/161 )

(a)

(b)

x0.1 x1 x10 0.1

1 10 100

L = 120nm VDD = 0.3V

s =

opt

Frequency = 6GHz

T = 75C T = 125C

Si

Rb

Nois e Contri bution w .r.t. Si

d

(% )

Multiple of R

b

T = 25C

Figure 4-22 Sensitivity analysis of the variation of R to its noise contribution. b (WF /NF /NG= μm/8/161 )

102

NF

min

@6GHz (dB)

VDD (V)

Figure 4-23 NFmin as a function of VDD at different temperatures for various channel length devices. (WF /NF /NG= μm/8/161 )

Chapter 5

RF Noise Characterization for the Tensile-Strained nMOSFET

5.1 Introduction

As the gate length of CMOS transistors is down-scaled to decananometer regime, device scaling is becoming extremely difficult due to many physical and technological problems [1].

Strain-engineering technology is one way to maintain the scaling trends of CMOS devices. It is well known that the strained-channel MOSFETs have larger carrier mobility and drain current than the unstrained counterparts [2]-[6]. It is expected that the improved DC performances can also enhance the RF performances.

Recently, CMOS technologies with the incorporation of high-tensile contact etch stop layer (CESL) stressors have been demonstrated for RF applications and a very high cut-off frequency ( f ) has been reported [7][8]. There have been many studies on the high frequency t noise characterization and modeling for the conventional MOSFET devices [9]-[17]. However, the effects of the highly tensile stressors on the high-frequency noise characteristics have rarely been known. In this chapter, the high-frequency noise characteristics of tensile-strained nMOSFETs including their temperature dependences will be investigated and analyzed for the first time [18].

104

CESL layer was used.

The gate length of the test devices varies from 60nm to 240nm, and the total gate width of the test devices is 128 µm (4 µm by 32 gate fingers). The noise parameters of the MOSFET under different temperatures were measured using Auriga scattering and noise parameter

The gate length of the test devices varies from 60nm to 240nm, and the total gate width of the test devices is 128 µm (4 µm by 32 gate fingers). The noise parameters of the MOSFET under different temperatures were measured using Auriga scattering and noise parameter

相關文件